1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
39 #if V8_TARGET_ARCH_IA32
41 #include "src/base/bits.h"
42 #include "src/base/cpu.h"
43 #include "src/disassembler.h"
44 #include "src/macro-assembler.h"
45 #include "src/serialize.h"
50 // -----------------------------------------------------------------------------
51 // Implementation of CpuFeatures
53 void CpuFeatures::ProbeImpl(bool cross_compile) {
55 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
56 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
58 // Only use statically determined features for cross compile (snapshot).
59 if (cross_compile) return;
61 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
62 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
66 void CpuFeatures::PrintTarget() { }
67 void CpuFeatures::PrintFeatures() { }
70 // -----------------------------------------------------------------------------
71 // Implementation of Displacement
73 void Displacement::init(Label* L, Type type) {
74 DCHECK(!L->is_bound());
78 DCHECK(next > 0); // Displacements must be at positions > 0
80 // Ensure that we _never_ overflow the next field.
81 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
82 data_ = NextField::encode(next) | TypeField::encode(type);
86 // -----------------------------------------------------------------------------
87 // Implementation of RelocInfo
90 const int RelocInfo::kApplyMask =
91 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
92 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
93 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
96 bool RelocInfo::IsCodedSpecially() {
97 // The deserializer needs to know whether a pointer is specially coded. Being
98 // specially coded on IA32 means that it is a relative address, as used by
99 // branch instructions. These are also the ones that need changing when a
100 // code object moves.
101 return (1 << rmode_) & kApplyMask;
105 bool RelocInfo::IsInConstantPool() {
110 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
111 // Patch the code at the current address with the supplied instructions.
112 for (int i = 0; i < instruction_count; i++) {
113 *(pc_ + i) = *(instructions + i);
116 // Indicate that code has changed.
117 CpuFeatures::FlushICache(pc_, instruction_count);
121 // Patch the code at the current PC with a call to the target address.
122 // Additional guard int3 instructions can be added if required.
123 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
124 // Call instruction takes up 5 bytes and int3 takes up one byte.
125 static const int kCallCodeSize = 5;
126 int code_size = kCallCodeSize + guard_bytes;
128 // Create a code patcher.
129 CodePatcher patcher(pc_, code_size);
131 // Add a label for checking the size of the code used for returning.
133 Label check_codesize;
134 patcher.masm()->bind(&check_codesize);
138 patcher.masm()->call(target, RelocInfo::NONE32);
140 // Check that the size of the code generated is as expected.
141 DCHECK_EQ(kCallCodeSize,
142 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
144 // Add the requested number of int3 instructions after the call.
145 DCHECK_GE(guard_bytes, 0);
146 for (int i = 0; i < guard_bytes; i++) {
147 patcher.masm()->int3();
152 // -----------------------------------------------------------------------------
153 // Implementation of Operand
155 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
157 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
160 if (base.is(esp)) set_sib(times_1, esp, base);
161 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
164 if (base.is(esp)) set_sib(times_1, esp, base);
169 if (base.is(esp)) set_sib(times_1, esp, base);
170 set_dispr(disp, rmode);
175 Operand::Operand(Register base,
179 RelocInfo::Mode rmode) {
180 DCHECK(!index.is(esp)); // illegal addressing mode
181 // [base + index*scale + disp/r]
182 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
183 // [base + index*scale]
185 set_sib(scale, index, base);
186 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
187 // [base + index*scale + disp8]
189 set_sib(scale, index, base);
192 // [base + index*scale + disp/r]
194 set_sib(scale, index, base);
195 set_dispr(disp, rmode);
200 Operand::Operand(Register index,
203 RelocInfo::Mode rmode) {
204 DCHECK(!index.is(esp)); // illegal addressing mode
205 // [index*scale + disp/r]
207 set_sib(scale, index, ebp);
208 set_dispr(disp, rmode);
212 bool Operand::is_reg(Register reg) const {
213 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
214 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
218 bool Operand::is_reg_only() const {
219 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
223 Register Operand::reg() const {
224 DCHECK(is_reg_only());
225 return Register::from_code(buf_[0] & 0x07);
229 // -----------------------------------------------------------------------------
230 // Implementation of Assembler.
232 // Emit a single byte. Must always be inlined.
237 #ifdef GENERATED_CODE_COVERAGE
238 static void InitCoverageLog();
241 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
242 : AssemblerBase(isolate, buffer, buffer_size),
243 positions_recorder_(this) {
244 // Clear the buffer in debug mode unless it was provided by the
245 // caller in which case we can't be sure it's okay to overwrite
246 // existing code in it; see CodePatcher::CodePatcher(...).
249 memset(buffer_, 0xCC, buffer_size_); // int3
253 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
255 #ifdef GENERATED_CODE_COVERAGE
261 void Assembler::GetCode(CodeDesc* desc) {
262 // Finalize code (at this point overflow() may be true, but the gap ensures
263 // that we are still not overlapping instructions and relocation info).
264 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
265 // Set up code descriptor.
266 desc->buffer = buffer_;
267 desc->buffer_size = buffer_size_;
268 desc->instr_size = pc_offset();
269 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
274 void Assembler::Align(int m) {
275 DCHECK(base::bits::IsPowerOfTwo32(m));
277 int addr = pc_offset();
278 Nop((m - (addr & mask)) & mask);
282 bool Assembler::IsNop(Address addr) {
284 while (*a == 0x66) a++;
285 if (*a == 0x90) return true;
286 if (a[0] == 0xf && a[1] == 0x1f) return true;
291 void Assembler::Nop(int bytes) {
292 EnsureSpace ensure_space(this);
294 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
356 void Assembler::CodeTargetAlign() {
357 Align(16); // Preferred alignment of jump targets on ia32.
361 void Assembler::cpuid() {
362 EnsureSpace ensure_space(this);
368 void Assembler::pushad() {
369 EnsureSpace ensure_space(this);
374 void Assembler::popad() {
375 EnsureSpace ensure_space(this);
380 void Assembler::pushfd() {
381 EnsureSpace ensure_space(this);
386 void Assembler::popfd() {
387 EnsureSpace ensure_space(this);
392 void Assembler::push(const Immediate& x) {
393 EnsureSpace ensure_space(this);
404 void Assembler::push_imm32(int32_t imm32) {
405 EnsureSpace ensure_space(this);
411 void Assembler::push(Register src) {
412 EnsureSpace ensure_space(this);
413 EMIT(0x50 | src.code());
417 void Assembler::push(const Operand& src) {
418 EnsureSpace ensure_space(this);
420 emit_operand(esi, src);
424 void Assembler::pop(Register dst) {
425 DCHECK(reloc_info_writer.last_pc() != NULL);
426 EnsureSpace ensure_space(this);
427 EMIT(0x58 | dst.code());
431 void Assembler::pop(const Operand& dst) {
432 EnsureSpace ensure_space(this);
434 emit_operand(eax, dst);
438 void Assembler::enter(const Immediate& size) {
439 EnsureSpace ensure_space(this);
446 void Assembler::leave() {
447 EnsureSpace ensure_space(this);
452 void Assembler::mov_b(Register dst, const Operand& src) {
453 CHECK(dst.is_byte_register());
454 EnsureSpace ensure_space(this);
456 emit_operand(dst, src);
460 void Assembler::mov_b(const Operand& dst, int8_t imm8) {
461 EnsureSpace ensure_space(this);
463 emit_operand(eax, dst);
468 void Assembler::mov_b(const Operand& dst, Register src) {
469 CHECK(src.is_byte_register());
470 EnsureSpace ensure_space(this);
472 emit_operand(src, dst);
476 void Assembler::mov_w(Register dst, const Operand& src) {
477 EnsureSpace ensure_space(this);
480 emit_operand(dst, src);
484 void Assembler::mov_w(const Operand& dst, Register src) {
485 EnsureSpace ensure_space(this);
488 emit_operand(src, dst);
492 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
493 EnsureSpace ensure_space(this);
496 emit_operand(eax, dst);
497 EMIT(static_cast<int8_t>(imm16 & 0xff));
498 EMIT(static_cast<int8_t>(imm16 >> 8));
502 void Assembler::mov(Register dst, int32_t imm32) {
503 EnsureSpace ensure_space(this);
504 EMIT(0xB8 | dst.code());
509 void Assembler::mov(Register dst, const Immediate& x) {
510 EnsureSpace ensure_space(this);
511 EMIT(0xB8 | dst.code());
516 void Assembler::mov(Register dst, Handle<Object> handle) {
517 EnsureSpace ensure_space(this);
518 EMIT(0xB8 | dst.code());
523 void Assembler::mov(Register dst, const Operand& src) {
524 EnsureSpace ensure_space(this);
526 emit_operand(dst, src);
530 void Assembler::mov(Register dst, Register src) {
531 EnsureSpace ensure_space(this);
533 EMIT(0xC0 | src.code() << 3 | dst.code());
537 void Assembler::mov(const Operand& dst, const Immediate& x) {
538 EnsureSpace ensure_space(this);
540 emit_operand(eax, dst);
545 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
546 EnsureSpace ensure_space(this);
548 emit_operand(eax, dst);
553 void Assembler::mov(const Operand& dst, Register src) {
554 EnsureSpace ensure_space(this);
556 emit_operand(src, dst);
560 void Assembler::movsx_b(Register dst, const Operand& src) {
561 EnsureSpace ensure_space(this);
564 emit_operand(dst, src);
568 void Assembler::movsx_w(Register dst, const Operand& src) {
569 EnsureSpace ensure_space(this);
572 emit_operand(dst, src);
576 void Assembler::movzx_b(Register dst, const Operand& src) {
577 EnsureSpace ensure_space(this);
580 emit_operand(dst, src);
584 void Assembler::movzx_w(Register dst, const Operand& src) {
585 EnsureSpace ensure_space(this);
588 emit_operand(dst, src);
592 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
593 EnsureSpace ensure_space(this);
594 // Opcode: 0f 40 + cc /r.
597 emit_operand(dst, src);
601 void Assembler::cld() {
602 EnsureSpace ensure_space(this);
607 void Assembler::rep_movs() {
608 EnsureSpace ensure_space(this);
614 void Assembler::rep_stos() {
615 EnsureSpace ensure_space(this);
621 void Assembler::stos() {
622 EnsureSpace ensure_space(this);
627 void Assembler::xchg(Register dst, Register src) {
628 EnsureSpace ensure_space(this);
629 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
630 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
633 EMIT(0xC0 | src.code() << 3 | dst.code());
638 void Assembler::xchg(Register dst, const Operand& src) {
639 EnsureSpace ensure_space(this);
641 emit_operand(dst, src);
645 void Assembler::adc(Register dst, int32_t imm32) {
646 EnsureSpace ensure_space(this);
647 emit_arith(2, Operand(dst), Immediate(imm32));
651 void Assembler::adc(Register dst, const Operand& src) {
652 EnsureSpace ensure_space(this);
654 emit_operand(dst, src);
658 void Assembler::add(Register dst, const Operand& src) {
659 EnsureSpace ensure_space(this);
661 emit_operand(dst, src);
665 void Assembler::add(const Operand& dst, Register src) {
666 EnsureSpace ensure_space(this);
668 emit_operand(src, dst);
672 void Assembler::add(const Operand& dst, const Immediate& x) {
673 DCHECK(reloc_info_writer.last_pc() != NULL);
674 EnsureSpace ensure_space(this);
675 emit_arith(0, dst, x);
679 void Assembler::and_(Register dst, int32_t imm32) {
680 and_(dst, Immediate(imm32));
684 void Assembler::and_(Register dst, const Immediate& x) {
685 EnsureSpace ensure_space(this);
686 emit_arith(4, Operand(dst), x);
690 void Assembler::and_(Register dst, const Operand& src) {
691 EnsureSpace ensure_space(this);
693 emit_operand(dst, src);
697 void Assembler::and_(const Operand& dst, const Immediate& x) {
698 EnsureSpace ensure_space(this);
699 emit_arith(4, dst, x);
703 void Assembler::and_(const Operand& dst, Register src) {
704 EnsureSpace ensure_space(this);
706 emit_operand(src, dst);
710 void Assembler::cmpb(const Operand& op, int8_t imm8) {
711 EnsureSpace ensure_space(this);
712 if (op.is_reg(eax)) {
716 emit_operand(edi, op); // edi == 7
722 void Assembler::cmpb(const Operand& op, Register reg) {
723 CHECK(reg.is_byte_register());
724 EnsureSpace ensure_space(this);
726 emit_operand(reg, op);
730 void Assembler::cmpb(Register reg, const Operand& op) {
731 CHECK(reg.is_byte_register());
732 EnsureSpace ensure_space(this);
734 emit_operand(reg, op);
738 void Assembler::cmpw(const Operand& op, Immediate imm16) {
739 DCHECK(imm16.is_int16());
740 EnsureSpace ensure_space(this);
743 emit_operand(edi, op);
748 void Assembler::cmp(Register reg, int32_t imm32) {
749 EnsureSpace ensure_space(this);
750 emit_arith(7, Operand(reg), Immediate(imm32));
754 void Assembler::cmp(Register reg, Handle<Object> handle) {
755 EnsureSpace ensure_space(this);
756 emit_arith(7, Operand(reg), Immediate(handle));
760 void Assembler::cmp(Register reg, const Operand& op) {
761 EnsureSpace ensure_space(this);
763 emit_operand(reg, op);
767 void Assembler::cmp(const Operand& op, const Immediate& imm) {
768 EnsureSpace ensure_space(this);
769 emit_arith(7, op, imm);
773 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
774 EnsureSpace ensure_space(this);
775 emit_arith(7, op, Immediate(handle));
779 void Assembler::cmpb_al(const Operand& op) {
780 EnsureSpace ensure_space(this);
781 EMIT(0x38); // CMP r/m8, r8
782 emit_operand(eax, op); // eax has same code as register al.
786 void Assembler::cmpw_ax(const Operand& op) {
787 EnsureSpace ensure_space(this);
789 EMIT(0x39); // CMP r/m16, r16
790 emit_operand(eax, op); // eax has same code as register ax.
794 void Assembler::dec_b(Register dst) {
795 CHECK(dst.is_byte_register());
796 EnsureSpace ensure_space(this);
798 EMIT(0xC8 | dst.code());
802 void Assembler::dec_b(const Operand& dst) {
803 EnsureSpace ensure_space(this);
805 emit_operand(ecx, dst);
809 void Assembler::dec(Register dst) {
810 EnsureSpace ensure_space(this);
811 EMIT(0x48 | dst.code());
815 void Assembler::dec(const Operand& dst) {
816 EnsureSpace ensure_space(this);
818 emit_operand(ecx, dst);
822 void Assembler::cdq() {
823 EnsureSpace ensure_space(this);
828 void Assembler::idiv(const Operand& src) {
829 EnsureSpace ensure_space(this);
831 emit_operand(edi, src);
835 void Assembler::div(const Operand& src) {
836 EnsureSpace ensure_space(this);
838 emit_operand(esi, src);
842 void Assembler::imul(Register reg) {
843 EnsureSpace ensure_space(this);
845 EMIT(0xE8 | reg.code());
849 void Assembler::imul(Register dst, const Operand& src) {
850 EnsureSpace ensure_space(this);
853 emit_operand(dst, src);
857 void Assembler::imul(Register dst, Register src, int32_t imm32) {
858 imul(dst, Operand(src), imm32);
862 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
863 EnsureSpace ensure_space(this);
864 if (is_int8(imm32)) {
866 emit_operand(dst, src);
870 emit_operand(dst, src);
876 void Assembler::inc(Register dst) {
877 EnsureSpace ensure_space(this);
878 EMIT(0x40 | dst.code());
882 void Assembler::inc(const Operand& dst) {
883 EnsureSpace ensure_space(this);
885 emit_operand(eax, dst);
889 void Assembler::lea(Register dst, const Operand& src) {
890 EnsureSpace ensure_space(this);
892 emit_operand(dst, src);
896 void Assembler::mul(Register src) {
897 EnsureSpace ensure_space(this);
899 EMIT(0xE0 | src.code());
903 void Assembler::neg(Register dst) {
904 EnsureSpace ensure_space(this);
906 EMIT(0xD8 | dst.code());
910 void Assembler::neg(const Operand& dst) {
911 EnsureSpace ensure_space(this);
913 emit_operand(ebx, dst);
917 void Assembler::not_(Register dst) {
918 EnsureSpace ensure_space(this);
920 EMIT(0xD0 | dst.code());
924 void Assembler::not_(const Operand& dst) {
925 EnsureSpace ensure_space(this);
927 emit_operand(edx, dst);
931 void Assembler::or_(Register dst, int32_t imm32) {
932 EnsureSpace ensure_space(this);
933 emit_arith(1, Operand(dst), Immediate(imm32));
937 void Assembler::or_(Register dst, const Operand& src) {
938 EnsureSpace ensure_space(this);
940 emit_operand(dst, src);
944 void Assembler::or_(const Operand& dst, const Immediate& x) {
945 EnsureSpace ensure_space(this);
946 emit_arith(1, dst, x);
950 void Assembler::or_(const Operand& dst, Register src) {
951 EnsureSpace ensure_space(this);
953 emit_operand(src, dst);
957 void Assembler::rcl(Register dst, uint8_t imm8) {
958 EnsureSpace ensure_space(this);
959 DCHECK(is_uint5(imm8)); // illegal shift count
962 EMIT(0xD0 | dst.code());
965 EMIT(0xD0 | dst.code());
971 void Assembler::rcr(Register dst, uint8_t imm8) {
972 EnsureSpace ensure_space(this);
973 DCHECK(is_uint5(imm8)); // illegal shift count
976 EMIT(0xD8 | dst.code());
979 EMIT(0xD8 | dst.code());
985 void Assembler::ror(Register dst, uint8_t imm8) {
986 EnsureSpace ensure_space(this);
987 DCHECK(is_uint5(imm8)); // illegal shift count
990 EMIT(0xC8 | dst.code());
993 EMIT(0xC8 | dst.code());
999 void Assembler::ror_cl(Register dst) {
1000 EnsureSpace ensure_space(this);
1002 EMIT(0xC8 | dst.code());
1006 void Assembler::sar(const Operand& dst, uint8_t imm8) {
1007 EnsureSpace ensure_space(this);
1008 DCHECK(is_uint5(imm8)); // illegal shift count
1011 emit_operand(edi, dst);
1014 emit_operand(edi, dst);
1020 void Assembler::sar_cl(const Operand& dst) {
1021 EnsureSpace ensure_space(this);
1023 emit_operand(edi, dst);
1027 void Assembler::sbb(Register dst, const Operand& src) {
1028 EnsureSpace ensure_space(this);
1030 emit_operand(dst, src);
1034 void Assembler::shld(Register dst, const Operand& src) {
1035 EnsureSpace ensure_space(this);
1038 emit_operand(dst, src);
1042 void Assembler::shl(const Operand& dst, uint8_t imm8) {
1043 EnsureSpace ensure_space(this);
1044 DCHECK(is_uint5(imm8)); // illegal shift count
1047 emit_operand(esp, dst);
1050 emit_operand(esp, dst);
1056 void Assembler::shl_cl(const Operand& dst) {
1057 EnsureSpace ensure_space(this);
1059 emit_operand(esp, dst);
1063 void Assembler::shrd(Register dst, const Operand& src) {
1064 EnsureSpace ensure_space(this);
1067 emit_operand(dst, src);
1071 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1072 EnsureSpace ensure_space(this);
1073 DCHECK(is_uint5(imm8)); // illegal shift count
1076 emit_operand(ebp, dst);
1079 emit_operand(ebp, dst);
1085 void Assembler::shr_cl(const Operand& dst) {
1086 EnsureSpace ensure_space(this);
1088 emit_operand(ebp, dst);
1092 void Assembler::sub(const Operand& dst, const Immediate& x) {
1093 EnsureSpace ensure_space(this);
1094 emit_arith(5, dst, x);
1098 void Assembler::sub(Register dst, const Operand& src) {
1099 EnsureSpace ensure_space(this);
1101 emit_operand(dst, src);
1105 void Assembler::sub(const Operand& dst, Register src) {
1106 EnsureSpace ensure_space(this);
1108 emit_operand(src, dst);
1112 void Assembler::test(Register reg, const Immediate& imm) {
1113 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1114 test_b(reg, imm.x_);
1118 EnsureSpace ensure_space(this);
1119 // This is not using emit_arith because test doesn't support
1120 // sign-extension of 8-bit operands.
1125 EMIT(0xC0 | reg.code());
1131 void Assembler::test(Register reg, const Operand& op) {
1132 EnsureSpace ensure_space(this);
1134 emit_operand(reg, op);
1138 void Assembler::test_b(Register reg, const Operand& op) {
1139 CHECK(reg.is_byte_register());
1140 EnsureSpace ensure_space(this);
1142 emit_operand(reg, op);
1146 void Assembler::test(const Operand& op, const Immediate& imm) {
1147 if (op.is_reg_only()) {
1148 test(op.reg(), imm);
1151 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1152 return test_b(op, imm.x_);
1154 EnsureSpace ensure_space(this);
1156 emit_operand(eax, op);
1161 void Assembler::test_b(Register reg, uint8_t imm8) {
1162 EnsureSpace ensure_space(this);
1163 // Only use test against byte for registers that have a byte
1164 // variant: eax, ebx, ecx, and edx.
1168 } else if (reg.is_byte_register()) {
1169 emit_arith_b(0xF6, 0xC0, reg, imm8);
1172 EMIT(0xC0 | reg.code());
1178 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1179 if (op.is_reg_only()) {
1180 test_b(op.reg(), imm8);
1183 EnsureSpace ensure_space(this);
1185 emit_operand(eax, op);
1190 void Assembler::xor_(Register dst, int32_t imm32) {
1191 EnsureSpace ensure_space(this);
1192 emit_arith(6, Operand(dst), Immediate(imm32));
1196 void Assembler::xor_(Register dst, const Operand& src) {
1197 EnsureSpace ensure_space(this);
1199 emit_operand(dst, src);
1203 void Assembler::xor_(const Operand& dst, Register src) {
1204 EnsureSpace ensure_space(this);
1206 emit_operand(src, dst);
1210 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1211 EnsureSpace ensure_space(this);
1212 emit_arith(6, dst, x);
1216 void Assembler::bt(const Operand& dst, Register src) {
1217 EnsureSpace ensure_space(this);
1220 emit_operand(src, dst);
1224 void Assembler::bts(const Operand& dst, Register src) {
1225 EnsureSpace ensure_space(this);
1228 emit_operand(src, dst);
1232 void Assembler::bsr(Register dst, const Operand& src) {
1233 EnsureSpace ensure_space(this);
1236 emit_operand(dst, src);
1240 void Assembler::hlt() {
1241 EnsureSpace ensure_space(this);
1246 void Assembler::int3() {
1247 EnsureSpace ensure_space(this);
1252 void Assembler::nop() {
1253 EnsureSpace ensure_space(this);
1258 void Assembler::ret(int imm16) {
1259 EnsureSpace ensure_space(this);
1260 DCHECK(is_uint16(imm16));
1266 EMIT((imm16 >> 8) & 0xFF);
1271 // Labels refer to positions in the (to be) generated code.
1272 // There are bound, linked, and unused labels.
1274 // Bound labels refer to known positions in the already
1275 // generated code. pos() is the position the label refers to.
1277 // Linked labels refer to unknown positions in the code
1278 // to be generated; pos() is the position of the 32bit
1279 // Displacement of the last instruction using the label.
1282 void Assembler::print(Label* L) {
1283 if (L->is_unused()) {
1284 PrintF("unused label\n");
1285 } else if (L->is_bound()) {
1286 PrintF("bound label to %d\n", L->pos());
1287 } else if (L->is_linked()) {
1289 PrintF("unbound label");
1290 while (l.is_linked()) {
1291 Displacement disp = disp_at(&l);
1292 PrintF("@ %d ", l.pos());
1298 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1303 void Assembler::bind_to(Label* L, int pos) {
1304 EnsureSpace ensure_space(this);
1305 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1306 while (L->is_linked()) {
1307 Displacement disp = disp_at(L);
1308 int fixup_pos = L->pos();
1309 if (disp.type() == Displacement::CODE_RELATIVE) {
1310 // Relative to Code* heap object pointer.
1311 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1313 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1314 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1316 // Relative address, relative to point after address.
1317 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1318 long_at_put(fixup_pos, imm32);
1322 while (L->is_near_linked()) {
1323 int fixup_pos = L->near_link_pos();
1324 int offset_to_next =
1325 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1326 DCHECK(offset_to_next <= 0);
1327 // Relative address, relative to point after address.
1328 int disp = pos - fixup_pos - sizeof(int8_t);
1329 CHECK(0 <= disp && disp <= 127);
1330 set_byte_at(fixup_pos, disp);
1331 if (offset_to_next < 0) {
1332 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1341 void Assembler::bind(Label* L) {
1342 EnsureSpace ensure_space(this);
1343 DCHECK(!L->is_bound()); // label can only be bound once
1344 bind_to(L, pc_offset());
1348 void Assembler::call(Label* L) {
1349 positions_recorder()->WriteRecordedPositions();
1350 EnsureSpace ensure_space(this);
1351 if (L->is_bound()) {
1352 const int long_size = 5;
1353 int offs = L->pos() - pc_offset();
1355 // 1110 1000 #32-bit disp.
1357 emit(offs - long_size);
1359 // 1110 1000 #32-bit disp.
1361 emit_disp(L, Displacement::OTHER);
1366 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1367 positions_recorder()->WriteRecordedPositions();
1368 EnsureSpace ensure_space(this);
1369 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1371 if (RelocInfo::IsRuntimeEntry(rmode)) {
1372 emit(reinterpret_cast<uint32_t>(entry), rmode);
1374 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1379 int Assembler::CallSize(const Operand& adr) {
1380 // Call size is 1 (opcode) + adr.len_ (operand).
1381 return 1 + adr.len_;
1385 void Assembler::call(const Operand& adr) {
1386 positions_recorder()->WriteRecordedPositions();
1387 EnsureSpace ensure_space(this);
1389 emit_operand(edx, adr);
1393 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1394 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1398 void Assembler::call(Handle<Code> code,
1399 RelocInfo::Mode rmode,
1400 TypeFeedbackId ast_id) {
1401 positions_recorder()->WriteRecordedPositions();
1402 EnsureSpace ensure_space(this);
1403 DCHECK(RelocInfo::IsCodeTarget(rmode)
1404 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1406 emit(code, rmode, ast_id);
1410 void Assembler::jmp(Label* L, Label::Distance distance) {
1411 EnsureSpace ensure_space(this);
1412 if (L->is_bound()) {
1413 const int short_size = 2;
1414 const int long_size = 5;
1415 int offs = L->pos() - pc_offset();
1417 if (is_int8(offs - short_size)) {
1418 // 1110 1011 #8-bit disp.
1420 EMIT((offs - short_size) & 0xFF);
1422 // 1110 1001 #32-bit disp.
1424 emit(offs - long_size);
1426 } else if (distance == Label::kNear) {
1430 // 1110 1001 #32-bit disp.
1432 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1437 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1438 EnsureSpace ensure_space(this);
1439 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1441 if (RelocInfo::IsRuntimeEntry(rmode)) {
1442 emit(reinterpret_cast<uint32_t>(entry), rmode);
1444 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1449 void Assembler::jmp(const Operand& adr) {
1450 EnsureSpace ensure_space(this);
1452 emit_operand(esp, adr);
1456 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1457 EnsureSpace ensure_space(this);
1458 DCHECK(RelocInfo::IsCodeTarget(rmode));
1464 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1465 EnsureSpace ensure_space(this);
1466 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1467 if (L->is_bound()) {
1468 const int short_size = 2;
1469 const int long_size = 6;
1470 int offs = L->pos() - pc_offset();
1472 if (is_int8(offs - short_size)) {
1473 // 0111 tttn #8-bit disp
1475 EMIT((offs - short_size) & 0xFF);
1477 // 0000 1111 1000 tttn #32-bit disp
1480 emit(offs - long_size);
1482 } else if (distance == Label::kNear) {
1486 // 0000 1111 1000 tttn #32-bit disp
1487 // Note: could eliminate cond. jumps to this jump if condition
1488 // is the same however, seems to be rather unlikely case.
1491 emit_disp(L, Displacement::OTHER);
1496 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1497 EnsureSpace ensure_space(this);
1498 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1499 // 0000 1111 1000 tttn #32-bit disp.
1502 if (RelocInfo::IsRuntimeEntry(rmode)) {
1503 emit(reinterpret_cast<uint32_t>(entry), rmode);
1505 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1510 void Assembler::j(Condition cc, Handle<Code> code) {
1511 EnsureSpace ensure_space(this);
1512 // 0000 1111 1000 tttn #32-bit disp
1515 emit(code, RelocInfo::CODE_TARGET);
1519 // FPU instructions.
1521 void Assembler::fld(int i) {
1522 EnsureSpace ensure_space(this);
1523 emit_farith(0xD9, 0xC0, i);
1527 void Assembler::fstp(int i) {
1528 EnsureSpace ensure_space(this);
1529 emit_farith(0xDD, 0xD8, i);
1533 void Assembler::fld1() {
1534 EnsureSpace ensure_space(this);
1540 void Assembler::fldpi() {
1541 EnsureSpace ensure_space(this);
1547 void Assembler::fldz() {
1548 EnsureSpace ensure_space(this);
1554 void Assembler::fldln2() {
1555 EnsureSpace ensure_space(this);
1561 void Assembler::fld_s(const Operand& adr) {
1562 EnsureSpace ensure_space(this);
1564 emit_operand(eax, adr);
1568 void Assembler::fld_d(const Operand& adr) {
1569 EnsureSpace ensure_space(this);
1571 emit_operand(eax, adr);
1575 void Assembler::fstp_s(const Operand& adr) {
1576 EnsureSpace ensure_space(this);
1578 emit_operand(ebx, adr);
1582 void Assembler::fst_s(const Operand& adr) {
1583 EnsureSpace ensure_space(this);
1585 emit_operand(edx, adr);
1589 void Assembler::fstp_d(const Operand& adr) {
1590 EnsureSpace ensure_space(this);
1592 emit_operand(ebx, adr);
1596 void Assembler::fst_d(const Operand& adr) {
1597 EnsureSpace ensure_space(this);
1599 emit_operand(edx, adr);
1603 void Assembler::fild_s(const Operand& adr) {
1604 EnsureSpace ensure_space(this);
1606 emit_operand(eax, adr);
1610 void Assembler::fild_d(const Operand& adr) {
1611 EnsureSpace ensure_space(this);
1613 emit_operand(ebp, adr);
1617 void Assembler::fistp_s(const Operand& adr) {
1618 EnsureSpace ensure_space(this);
1620 emit_operand(ebx, adr);
1624 void Assembler::fisttp_s(const Operand& adr) {
1625 DCHECK(IsEnabled(SSE3));
1626 EnsureSpace ensure_space(this);
1628 emit_operand(ecx, adr);
1632 void Assembler::fisttp_d(const Operand& adr) {
1633 DCHECK(IsEnabled(SSE3));
1634 EnsureSpace ensure_space(this);
1636 emit_operand(ecx, adr);
1640 void Assembler::fist_s(const Operand& adr) {
1641 EnsureSpace ensure_space(this);
1643 emit_operand(edx, adr);
1647 void Assembler::fistp_d(const Operand& adr) {
1648 EnsureSpace ensure_space(this);
1650 emit_operand(edi, adr);
1654 void Assembler::fabs() {
1655 EnsureSpace ensure_space(this);
1661 void Assembler::fchs() {
1662 EnsureSpace ensure_space(this);
1668 void Assembler::fcos() {
1669 EnsureSpace ensure_space(this);
1675 void Assembler::fsin() {
1676 EnsureSpace ensure_space(this);
1682 void Assembler::fptan() {
1683 EnsureSpace ensure_space(this);
1689 void Assembler::fyl2x() {
1690 EnsureSpace ensure_space(this);
1696 void Assembler::f2xm1() {
1697 EnsureSpace ensure_space(this);
1703 void Assembler::fscale() {
1704 EnsureSpace ensure_space(this);
1710 void Assembler::fninit() {
1711 EnsureSpace ensure_space(this);
1717 void Assembler::fadd(int i) {
1718 EnsureSpace ensure_space(this);
1719 emit_farith(0xDC, 0xC0, i);
1723 void Assembler::fadd_i(int i) {
1724 EnsureSpace ensure_space(this);
1725 emit_farith(0xD8, 0xC0, i);
1729 void Assembler::fsub(int i) {
1730 EnsureSpace ensure_space(this);
1731 emit_farith(0xDC, 0xE8, i);
1735 void Assembler::fsub_i(int i) {
1736 EnsureSpace ensure_space(this);
1737 emit_farith(0xD8, 0xE0, i);
1741 void Assembler::fisub_s(const Operand& adr) {
1742 EnsureSpace ensure_space(this);
1744 emit_operand(esp, adr);
1748 void Assembler::fmul_i(int i) {
1749 EnsureSpace ensure_space(this);
1750 emit_farith(0xD8, 0xC8, i);
1754 void Assembler::fmul(int i) {
1755 EnsureSpace ensure_space(this);
1756 emit_farith(0xDC, 0xC8, i);
1760 void Assembler::fdiv(int i) {
1761 EnsureSpace ensure_space(this);
1762 emit_farith(0xDC, 0xF8, i);
1766 void Assembler::fdiv_i(int i) {
1767 EnsureSpace ensure_space(this);
1768 emit_farith(0xD8, 0xF0, i);
1772 void Assembler::faddp(int i) {
1773 EnsureSpace ensure_space(this);
1774 emit_farith(0xDE, 0xC0, i);
1778 void Assembler::fsubp(int i) {
1779 EnsureSpace ensure_space(this);
1780 emit_farith(0xDE, 0xE8, i);
1784 void Assembler::fsubrp(int i) {
1785 EnsureSpace ensure_space(this);
1786 emit_farith(0xDE, 0xE0, i);
1790 void Assembler::fmulp(int i) {
1791 EnsureSpace ensure_space(this);
1792 emit_farith(0xDE, 0xC8, i);
1796 void Assembler::fdivp(int i) {
1797 EnsureSpace ensure_space(this);
1798 emit_farith(0xDE, 0xF8, i);
1802 void Assembler::fprem() {
1803 EnsureSpace ensure_space(this);
1809 void Assembler::fprem1() {
1810 EnsureSpace ensure_space(this);
1816 void Assembler::fxch(int i) {
1817 EnsureSpace ensure_space(this);
1818 emit_farith(0xD9, 0xC8, i);
1822 void Assembler::fincstp() {
1823 EnsureSpace ensure_space(this);
1829 void Assembler::ffree(int i) {
1830 EnsureSpace ensure_space(this);
1831 emit_farith(0xDD, 0xC0, i);
1835 void Assembler::ftst() {
1836 EnsureSpace ensure_space(this);
1842 void Assembler::fucomp(int i) {
1843 EnsureSpace ensure_space(this);
1844 emit_farith(0xDD, 0xE8, i);
1848 void Assembler::fucompp() {
1849 EnsureSpace ensure_space(this);
1855 void Assembler::fucomi(int i) {
1856 EnsureSpace ensure_space(this);
1862 void Assembler::fucomip() {
1863 EnsureSpace ensure_space(this);
1869 void Assembler::fcompp() {
1870 EnsureSpace ensure_space(this);
1876 void Assembler::fnstsw_ax() {
1877 EnsureSpace ensure_space(this);
1883 void Assembler::fwait() {
1884 EnsureSpace ensure_space(this);
1889 void Assembler::frndint() {
1890 EnsureSpace ensure_space(this);
1896 void Assembler::fnclex() {
1897 EnsureSpace ensure_space(this);
1903 void Assembler::sahf() {
1904 EnsureSpace ensure_space(this);
1909 void Assembler::setcc(Condition cc, Register reg) {
1910 DCHECK(reg.is_byte_register());
1911 EnsureSpace ensure_space(this);
1914 EMIT(0xC0 | reg.code());
1918 void Assembler::cvttss2si(Register dst, const Operand& src) {
1919 EnsureSpace ensure_space(this);
1923 emit_operand(dst, src);
1927 void Assembler::cvttsd2si(Register dst, const Operand& src) {
1928 EnsureSpace ensure_space(this);
1932 emit_operand(dst, src);
1936 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
1937 EnsureSpace ensure_space(this);
1941 emit_sse_operand(dst, src);
1945 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
1946 EnsureSpace ensure_space(this);
1950 emit_sse_operand(dst, src);
1954 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1955 EnsureSpace ensure_space(this);
1959 emit_sse_operand(dst, src);
1963 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1964 EnsureSpace ensure_space(this);
1968 emit_sse_operand(dst, src);
1972 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1973 EnsureSpace ensure_space(this);
1977 emit_sse_operand(dst, src);
1981 void Assembler::addsd(XMMRegister dst, const Operand& src) {
1982 EnsureSpace ensure_space(this);
1986 emit_sse_operand(dst, src);
1990 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1991 EnsureSpace ensure_space(this);
1995 emit_sse_operand(dst, src);
1999 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2000 EnsureSpace ensure_space(this);
2004 emit_sse_operand(dst, src);
2008 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2009 EnsureSpace ensure_space(this);
2013 emit_sse_operand(dst, src);
2017 void Assembler::subsd(XMMRegister dst, const Operand& src) {
2018 EnsureSpace ensure_space(this);
2022 emit_sse_operand(dst, src);
2026 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2027 EnsureSpace ensure_space(this);
2031 emit_sse_operand(dst, src);
2035 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2036 EnsureSpace ensure_space(this);
2040 emit_sse_operand(dst, src);
2044 void Assembler::andps(XMMRegister dst, const Operand& src) {
2045 EnsureSpace ensure_space(this);
2048 emit_sse_operand(dst, src);
2052 void Assembler::orps(XMMRegister dst, const Operand& src) {
2053 EnsureSpace ensure_space(this);
2056 emit_sse_operand(dst, src);
2060 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2061 EnsureSpace ensure_space(this);
2064 emit_sse_operand(dst, src);
2068 void Assembler::addps(XMMRegister dst, const Operand& src) {
2069 EnsureSpace ensure_space(this);
2072 emit_sse_operand(dst, src);
2076 void Assembler::subps(XMMRegister dst, const Operand& src) {
2077 EnsureSpace ensure_space(this);
2080 emit_sse_operand(dst, src);
2084 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2085 EnsureSpace ensure_space(this);
2088 emit_sse_operand(dst, src);
2092 void Assembler::divps(XMMRegister dst, const Operand& src) {
2093 EnsureSpace ensure_space(this);
2096 emit_sse_operand(dst, src);
2100 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2101 EnsureSpace ensure_space(this);
2105 emit_sse_operand(dst, src);
2109 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2110 EnsureSpace ensure_space(this);
2114 emit_sse_operand(dst, src);
2118 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2119 EnsureSpace ensure_space(this);
2123 emit_sse_operand(dst, src);
2127 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2128 EnsureSpace ensure_space(this);
2132 emit_sse_operand(dst, src);
2136 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2137 EnsureSpace ensure_space(this);
2141 emit_sse_operand(dst, src);
2145 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2146 DCHECK(IsEnabled(SSE4_1));
2147 EnsureSpace ensure_space(this);
2152 emit_sse_operand(dst, src);
2153 // Mask precision exeption.
2154 EMIT(static_cast<byte>(mode) | 0x8);
2158 void Assembler::movmskpd(Register dst, XMMRegister src) {
2159 EnsureSpace ensure_space(this);
2163 emit_sse_operand(dst, src);
2167 void Assembler::movmskps(Register dst, XMMRegister src) {
2168 EnsureSpace ensure_space(this);
2171 emit_sse_operand(dst, src);
2175 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2176 EnsureSpace ensure_space(this);
2180 emit_sse_operand(dst, src);
2184 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2185 EnsureSpace ensure_space(this);
2189 emit_sse_operand(dst, src);
2194 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2195 EnsureSpace ensure_space(this);
2198 emit_sse_operand(dst, src);
2202 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2203 DCHECK(is_uint8(imm8));
2204 EnsureSpace ensure_space(this);
2207 emit_sse_operand(dst, src);
2212 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2213 EnsureSpace ensure_space(this);
2217 emit_sse_operand(src, dst);
2221 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2222 EnsureSpace ensure_space(this);
2226 emit_sse_operand(dst, src);
2230 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2231 EnsureSpace ensure_space(this);
2235 emit_sse_operand(src, dst);
2239 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2240 EnsureSpace ensure_space(this);
2244 emit_sse_operand(dst, src);
2248 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2249 DCHECK(IsEnabled(SSE4_1));
2250 EnsureSpace ensure_space(this);
2255 emit_sse_operand(dst, src);
2259 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2260 EnsureSpace ensure_space(this);
2264 emit_sse_operand(src, dst);
2268 void Assembler::prefetch(const Operand& src, int level) {
2269 DCHECK(is_uint2(level));
2270 EnsureSpace ensure_space(this);
2273 // Emit hint number in Reg position of RegR/M.
2274 XMMRegister code = XMMRegister::from_code(level);
2275 emit_sse_operand(code, src);
2279 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2280 EnsureSpace ensure_space(this);
2281 EMIT(0xF2); // double
2283 EMIT(0x11); // store
2284 emit_sse_operand(src, dst);
2288 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2289 EnsureSpace ensure_space(this);
2290 EMIT(0xF2); // double
2293 emit_sse_operand(dst, src);
2297 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2298 EnsureSpace ensure_space(this);
2299 EMIT(0xF3); // float
2301 EMIT(0x11); // store
2302 emit_sse_operand(src, dst);
2306 void Assembler::movss(XMMRegister dst, const Operand& src) {
2307 EnsureSpace ensure_space(this);
2308 EMIT(0xF3); // float
2311 emit_sse_operand(dst, src);
2315 void Assembler::movd(XMMRegister dst, const Operand& src) {
2316 EnsureSpace ensure_space(this);
2320 emit_sse_operand(dst, src);
2324 void Assembler::movd(const Operand& dst, XMMRegister src) {
2325 EnsureSpace ensure_space(this);
2329 emit_sse_operand(src, dst);
2333 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2334 DCHECK(IsEnabled(SSE4_1));
2335 DCHECK(is_uint8(imm8));
2336 EnsureSpace ensure_space(this);
2341 emit_sse_operand(src, dst);
2346 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2347 EnsureSpace ensure_space(this);
2351 emit_sse_operand(dst, src);
2355 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2356 EnsureSpace ensure_space(this);
2360 emit_sse_operand(dst, src);
2364 void Assembler::por(XMMRegister dst, XMMRegister src) {
2365 EnsureSpace ensure_space(this);
2369 emit_sse_operand(dst, src);
2373 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2374 DCHECK(IsEnabled(SSE4_1));
2375 EnsureSpace ensure_space(this);
2380 emit_sse_operand(dst, src);
2384 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2385 EnsureSpace ensure_space(this);
2389 emit_sse_operand(esi, reg); // esi == 6
2394 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2395 EnsureSpace ensure_space(this);
2399 emit_sse_operand(dst, src);
2403 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2404 EnsureSpace ensure_space(this);
2408 emit_sse_operand(edx, reg); // edx == 2
2413 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2414 EnsureSpace ensure_space(this);
2418 emit_sse_operand(dst, src);
2422 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2423 EnsureSpace ensure_space(this);
2427 emit_sse_operand(dst, src);
2432 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2433 DCHECK(IsEnabled(SSE4_1));
2434 EnsureSpace ensure_space(this);
2439 emit_sse_operand(src, dst);
2444 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2445 DCHECK(IsEnabled(SSE4_1));
2446 EnsureSpace ensure_space(this);
2451 emit_sse_operand(dst, src);
2456 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2457 Register ireg = { reg.code() };
2458 emit_operand(ireg, adr);
2462 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2463 EMIT(0xC0 | dst.code() << 3 | src.code());
2467 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2468 EMIT(0xC0 | dst.code() << 3 | src.code());
2472 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2473 EMIT(0xC0 | (dst.code() << 3) | src.code());
2477 void Assembler::Print() {
2478 Disassembler::Decode(isolate(), stdout, buffer_, pc_);
2482 void Assembler::RecordJSReturn() {
2483 positions_recorder()->WriteRecordedPositions();
2484 EnsureSpace ensure_space(this);
2485 RecordRelocInfo(RelocInfo::JS_RETURN);
2489 void Assembler::RecordDebugBreakSlot() {
2490 positions_recorder()->WriteRecordedPositions();
2491 EnsureSpace ensure_space(this);
2492 RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
2496 void Assembler::RecordComment(const char* msg, bool force) {
2497 if (FLAG_code_comments || force) {
2498 EnsureSpace ensure_space(this);
2499 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
2504 void Assembler::GrowBuffer() {
2505 DCHECK(buffer_overflow());
2506 if (!own_buffer_) FATAL("external code buffer is too small");
2508 // Compute new buffer size.
2509 CodeDesc desc; // the new buffer
2510 desc.buffer_size = 2 * buffer_size_;
2512 // Some internal data structures overflow for very large buffers,
2513 // they must ensure that kMaximalBufferSize is not too large.
2514 if ((desc.buffer_size > kMaximalBufferSize) ||
2515 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2516 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2519 // Set up new buffer.
2520 desc.buffer = NewArray<byte>(desc.buffer_size);
2521 desc.instr_size = pc_offset();
2522 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2524 // Clear the buffer in debug mode. Use 'int3' instructions to make
2525 // sure to get into problems if we ever run uninitialized code.
2527 memset(desc.buffer, 0xCC, desc.buffer_size);
2531 int pc_delta = desc.buffer - buffer_;
2532 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2533 MemMove(desc.buffer, buffer_, desc.instr_size);
2534 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2538 DeleteArray(buffer_);
2539 buffer_ = desc.buffer;
2540 buffer_size_ = desc.buffer_size;
2542 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2543 reloc_info_writer.last_pc() + pc_delta);
2545 // Relocate runtime entries.
2546 for (RelocIterator it(desc); !it.done(); it.next()) {
2547 RelocInfo::Mode rmode = it.rinfo()->rmode();
2548 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
2549 int32_t* p = reinterpret_cast<int32_t*>(it.rinfo()->pc());
2550 if (*p != 0) { // 0 means uninitialized.
2556 DCHECK(!buffer_overflow());
2560 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2561 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2562 DCHECK(is_uint8(imm8));
2563 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
2565 EMIT(op2 | dst.code());
2570 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2571 DCHECK((0 <= sel) && (sel <= 7));
2572 Register ireg = { sel };
2574 EMIT(0x83); // using a sign-extended 8-bit immediate.
2575 emit_operand(ireg, dst);
2577 } else if (dst.is_reg(eax)) {
2578 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2581 EMIT(0x81); // using a literal 32-bit immediate.
2582 emit_operand(ireg, dst);
2588 void Assembler::emit_operand(Register reg, const Operand& adr) {
2589 const unsigned length = adr.len_;
2592 // Emit updated ModRM byte containing the given register.
2593 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2595 // Emit the rest of the encoded operand.
2596 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2599 // Emit relocation information if necessary.
2600 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2601 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2602 RecordRelocInfo(adr.rmode_);
2603 pc_ += sizeof(int32_t);
2608 void Assembler::emit_farith(int b1, int b2, int i) {
2609 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2610 DCHECK(0 <= i && i < 8); // illegal stack offset
2616 void Assembler::db(uint8_t data) {
2617 EnsureSpace ensure_space(this);
2622 void Assembler::dd(uint32_t data) {
2623 EnsureSpace ensure_space(this);
2628 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2629 DCHECK(!RelocInfo::IsNone(rmode));
2630 // Don't record external references unless the heap will be serialized.
2631 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2632 !serializer_enabled() && !emit_debug_code()) {
2635 RelocInfo rinfo(pc_, rmode, data, NULL);
2636 reloc_info_writer.Write(&rinfo);
2640 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2641 // No out-of-line constant pool support.
2642 DCHECK(!FLAG_enable_ool_constant_pool);
2643 return isolate->factory()->empty_constant_pool_array();
2647 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2648 // No out-of-line constant pool support.
2649 DCHECK(!FLAG_enable_ool_constant_pool);
2654 #ifdef GENERATED_CODE_COVERAGE
2655 static FILE* coverage_log = NULL;
2658 static void InitCoverageLog() {
2659 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2660 if (file_name != NULL) {
2661 coverage_log = fopen(file_name, "aw+");
2666 void LogGeneratedCodeCoverage(const char* file_line) {
2667 const char* return_address = (&file_line)[-1];
2668 char* push_insn = const_cast<char*>(return_address - 12);
2669 push_insn[0] = 0xeb; // Relative branch insn.
2670 push_insn[1] = 13; // Skip over coverage insns.
2671 if (coverage_log != NULL) {
2672 fprintf(coverage_log, "%s\n", file_line);
2673 fflush(coverage_log);
2679 } } // namespace v8::internal
2681 #endif // V8_TARGET_ARCH_IA32