1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
39 #if V8_TARGET_ARCH_IA32
41 #include "src/disassembler.h"
42 #include "src/macro-assembler.h"
43 #include "src/serialize.h"
48 // -----------------------------------------------------------------------------
49 // Implementation of CpuFeatures
51 void CpuFeatures::ProbeImpl(bool cross_compile) {
53 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
54 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
56 // Only use statically determined features for cross compile (snapshot).
57 if (cross_compile) return;
59 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
60 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
64 void CpuFeatures::PrintTarget() { }
65 void CpuFeatures::PrintFeatures() { }
68 // -----------------------------------------------------------------------------
69 // Implementation of Displacement
71 void Displacement::init(Label* L, Type type) {
72 ASSERT(!L->is_bound());
76 ASSERT(next > 0); // Displacements must be at positions > 0
78 // Ensure that we _never_ overflow the next field.
79 ASSERT(NextField::is_valid(Assembler::kMaximalBufferSize));
80 data_ = NextField::encode(next) | TypeField::encode(type);
84 // -----------------------------------------------------------------------------
85 // Implementation of RelocInfo
88 const int RelocInfo::kApplyMask =
89 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
90 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
91 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
94 bool RelocInfo::IsCodedSpecially() {
95 // The deserializer needs to know whether a pointer is specially coded. Being
96 // specially coded on IA32 means that it is a relative address, as used by
97 // branch instructions. These are also the ones that need changing when a
99 return (1 << rmode_) & kApplyMask;
103 bool RelocInfo::IsInConstantPool() {
108 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
109 // Patch the code at the current address with the supplied instructions.
110 for (int i = 0; i < instruction_count; i++) {
111 *(pc_ + i) = *(instructions + i);
114 // Indicate that code has changed.
115 CPU::FlushICache(pc_, instruction_count);
119 // Patch the code at the current PC with a call to the target address.
120 // Additional guard int3 instructions can be added if required.
121 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
122 // Call instruction takes up 5 bytes and int3 takes up one byte.
123 static const int kCallCodeSize = 5;
124 int code_size = kCallCodeSize + guard_bytes;
126 // Create a code patcher.
127 CodePatcher patcher(pc_, code_size);
129 // Add a label for checking the size of the code used for returning.
131 Label check_codesize;
132 patcher.masm()->bind(&check_codesize);
136 patcher.masm()->call(target, RelocInfo::NONE32);
138 // Check that the size of the code generated is as expected.
139 ASSERT_EQ(kCallCodeSize,
140 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
142 // Add the requested number of int3 instructions after the call.
143 ASSERT_GE(guard_bytes, 0);
144 for (int i = 0; i < guard_bytes; i++) {
145 patcher.masm()->int3();
150 // -----------------------------------------------------------------------------
151 // Implementation of Operand
153 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
155 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
158 if (base.is(esp)) set_sib(times_1, esp, base);
159 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
162 if (base.is(esp)) set_sib(times_1, esp, base);
167 if (base.is(esp)) set_sib(times_1, esp, base);
168 set_dispr(disp, rmode);
173 Operand::Operand(Register base,
177 RelocInfo::Mode rmode) {
178 ASSERT(!index.is(esp)); // illegal addressing mode
179 // [base + index*scale + disp/r]
180 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
181 // [base + index*scale]
183 set_sib(scale, index, base);
184 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
185 // [base + index*scale + disp8]
187 set_sib(scale, index, base);
190 // [base + index*scale + disp/r]
192 set_sib(scale, index, base);
193 set_dispr(disp, rmode);
198 Operand::Operand(Register index,
201 RelocInfo::Mode rmode) {
202 ASSERT(!index.is(esp)); // illegal addressing mode
203 // [index*scale + disp/r]
205 set_sib(scale, index, ebp);
206 set_dispr(disp, rmode);
210 Operand::Operand(const Operand& operand, int32_t offset) {
211 ASSERT(operand.len_ >= 1);
212 // Operand encodes REX ModR/M [SIB] [Disp].
213 byte modrm = operand.buf_[0];
214 ASSERT(modrm < 0xC0); // Disallow mode 3 (register target).
215 bool has_sib = ((modrm & 0x07) == 0x04);
216 byte mode = modrm & 0xC0;
217 int disp_offset = has_sib ? 2 : 1;
218 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
219 // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
221 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
222 int32_t disp_value = 0;
223 if (mode == 0x80 || is_baseless) {
224 // Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
225 disp_value = *BitCast<const int32_t*>(&operand.buf_[disp_offset]);
226 } else if (mode == 0x40) {
227 // Mode 1: Byte displacement.
228 disp_value = static_cast<signed char>(operand.buf_[disp_offset]);
231 // Write new operand with same registers, but with modified displacement.
232 ASSERT(offset >= 0 ? disp_value + offset >= disp_value
233 : disp_value + offset < disp_value); // No overflow.
234 disp_value += offset;
235 if (!is_int8(disp_value) || is_baseless) {
236 // Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
237 buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
238 len_ = disp_offset + 4;
239 Memory::int32_at(&buf_[disp_offset]) = disp_value;
240 } else if (disp_value != 0 || (base_reg == 0x05)) {
241 // Need 8 bits of displacement.
242 buf_[0] = (modrm & 0x3f) | 0x40; // Mode 1.
243 len_ = disp_offset + 1;
244 buf_[disp_offset] = static_cast<byte>(disp_value);
246 // Need no displacement.
247 buf_[0] = (modrm & 0x3f); // Mode 0.
251 buf_[1] = operand.buf_[1];
256 bool Operand::is_reg(Register reg) const {
257 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
258 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
262 bool Operand::is_reg_only() const {
263 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
267 Register Operand::reg() const {
268 ASSERT(is_reg_only());
269 return Register::from_code(buf_[0] & 0x07);
273 // -----------------------------------------------------------------------------
274 // Implementation of Assembler.
276 // Emit a single byte. Must always be inlined.
281 #ifdef GENERATED_CODE_COVERAGE
282 static void InitCoverageLog();
285 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
286 : AssemblerBase(isolate, buffer, buffer_size),
287 positions_recorder_(this) {
288 // Clear the buffer in debug mode unless it was provided by the
289 // caller in which case we can't be sure it's okay to overwrite
290 // existing code in it; see CodePatcher::CodePatcher(...).
293 memset(buffer_, 0xCC, buffer_size_); // int3
297 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
299 #ifdef GENERATED_CODE_COVERAGE
305 void Assembler::GetCode(CodeDesc* desc) {
306 // Finalize code (at this point overflow() may be true, but the gap ensures
307 // that we are still not overlapping instructions and relocation info).
308 ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.
309 // Set up code descriptor.
310 desc->buffer = buffer_;
311 desc->buffer_size = buffer_size_;
312 desc->instr_size = pc_offset();
313 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
318 void Assembler::Align(int m) {
319 ASSERT(IsPowerOf2(m));
321 int addr = pc_offset();
322 Nop((m - (addr & mask)) & mask);
326 bool Assembler::IsNop(Address addr) {
328 while (*a == 0x66) a++;
329 if (*a == 0x90) return true;
330 if (a[0] == 0xf && a[1] == 0x1f) return true;
335 void Assembler::Nop(int bytes) {
336 EnsureSpace ensure_space(this);
338 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
400 void Assembler::CodeTargetAlign() {
401 Align(16); // Preferred alignment of jump targets on ia32.
405 void Assembler::cpuid() {
406 EnsureSpace ensure_space(this);
412 void Assembler::pushad() {
413 EnsureSpace ensure_space(this);
418 void Assembler::popad() {
419 EnsureSpace ensure_space(this);
424 void Assembler::pushfd() {
425 EnsureSpace ensure_space(this);
430 void Assembler::popfd() {
431 EnsureSpace ensure_space(this);
436 void Assembler::push(const Immediate& x) {
437 EnsureSpace ensure_space(this);
448 void Assembler::push_imm32(int32_t imm32) {
449 EnsureSpace ensure_space(this);
455 void Assembler::push(Register src) {
456 EnsureSpace ensure_space(this);
457 EMIT(0x50 | src.code());
461 void Assembler::push(const Operand& src) {
462 EnsureSpace ensure_space(this);
464 emit_operand(esi, src);
468 void Assembler::pop(Register dst) {
469 ASSERT(reloc_info_writer.last_pc() != NULL);
470 EnsureSpace ensure_space(this);
471 EMIT(0x58 | dst.code());
475 void Assembler::pop(const Operand& dst) {
476 EnsureSpace ensure_space(this);
478 emit_operand(eax, dst);
482 void Assembler::enter(const Immediate& size) {
483 EnsureSpace ensure_space(this);
490 void Assembler::leave() {
491 EnsureSpace ensure_space(this);
496 void Assembler::mov_b(Register dst, const Operand& src) {
497 CHECK(dst.is_byte_register());
498 EnsureSpace ensure_space(this);
500 emit_operand(dst, src);
504 void Assembler::mov_b(const Operand& dst, int8_t imm8) {
505 EnsureSpace ensure_space(this);
507 emit_operand(eax, dst);
512 void Assembler::mov_b(const Operand& dst, Register src) {
513 CHECK(src.is_byte_register());
514 EnsureSpace ensure_space(this);
516 emit_operand(src, dst);
520 void Assembler::mov_w(Register dst, const Operand& src) {
521 EnsureSpace ensure_space(this);
524 emit_operand(dst, src);
528 void Assembler::mov_w(const Operand& dst, Register src) {
529 EnsureSpace ensure_space(this);
532 emit_operand(src, dst);
536 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
537 EnsureSpace ensure_space(this);
540 emit_operand(eax, dst);
541 EMIT(static_cast<int8_t>(imm16 & 0xff));
542 EMIT(static_cast<int8_t>(imm16 >> 8));
546 void Assembler::mov(Register dst, int32_t imm32) {
547 EnsureSpace ensure_space(this);
548 EMIT(0xB8 | dst.code());
553 void Assembler::mov(Register dst, const Immediate& x) {
554 EnsureSpace ensure_space(this);
555 EMIT(0xB8 | dst.code());
560 void Assembler::mov(Register dst, Handle<Object> handle) {
561 EnsureSpace ensure_space(this);
562 EMIT(0xB8 | dst.code());
567 void Assembler::mov(Register dst, const Operand& src) {
568 EnsureSpace ensure_space(this);
570 emit_operand(dst, src);
574 void Assembler::mov(Register dst, Register src) {
575 EnsureSpace ensure_space(this);
577 EMIT(0xC0 | src.code() << 3 | dst.code());
581 void Assembler::mov(const Operand& dst, const Immediate& x) {
582 EnsureSpace ensure_space(this);
584 emit_operand(eax, dst);
589 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
590 EnsureSpace ensure_space(this);
592 emit_operand(eax, dst);
597 void Assembler::mov(const Operand& dst, Register src) {
598 EnsureSpace ensure_space(this);
600 emit_operand(src, dst);
604 void Assembler::movsx_b(Register dst, const Operand& src) {
605 EnsureSpace ensure_space(this);
608 emit_operand(dst, src);
612 void Assembler::movsx_w(Register dst, const Operand& src) {
613 EnsureSpace ensure_space(this);
616 emit_operand(dst, src);
620 void Assembler::movzx_b(Register dst, const Operand& src) {
621 EnsureSpace ensure_space(this);
624 emit_operand(dst, src);
628 void Assembler::movzx_w(Register dst, const Operand& src) {
629 EnsureSpace ensure_space(this);
632 emit_operand(dst, src);
636 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
637 EnsureSpace ensure_space(this);
638 // Opcode: 0f 40 + cc /r.
641 emit_operand(dst, src);
645 void Assembler::cld() {
646 EnsureSpace ensure_space(this);
651 void Assembler::rep_movs() {
652 EnsureSpace ensure_space(this);
658 void Assembler::rep_stos() {
659 EnsureSpace ensure_space(this);
665 void Assembler::stos() {
666 EnsureSpace ensure_space(this);
671 void Assembler::xchg(Register dst, Register src) {
672 EnsureSpace ensure_space(this);
673 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
674 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
677 EMIT(0xC0 | src.code() << 3 | dst.code());
682 void Assembler::adc(Register dst, int32_t imm32) {
683 EnsureSpace ensure_space(this);
684 emit_arith(2, Operand(dst), Immediate(imm32));
688 void Assembler::adc(Register dst, const Operand& src) {
689 EnsureSpace ensure_space(this);
691 emit_operand(dst, src);
695 void Assembler::add(Register dst, const Operand& src) {
696 EnsureSpace ensure_space(this);
698 emit_operand(dst, src);
702 void Assembler::add(const Operand& dst, Register src) {
703 EnsureSpace ensure_space(this);
705 emit_operand(src, dst);
709 void Assembler::add(const Operand& dst, const Immediate& x) {
710 ASSERT(reloc_info_writer.last_pc() != NULL);
711 EnsureSpace ensure_space(this);
712 emit_arith(0, dst, x);
716 void Assembler::and_(Register dst, int32_t imm32) {
717 and_(dst, Immediate(imm32));
721 void Assembler::and_(Register dst, const Immediate& x) {
722 EnsureSpace ensure_space(this);
723 emit_arith(4, Operand(dst), x);
727 void Assembler::and_(Register dst, const Operand& src) {
728 EnsureSpace ensure_space(this);
730 emit_operand(dst, src);
734 void Assembler::and_(const Operand& dst, const Immediate& x) {
735 EnsureSpace ensure_space(this);
736 emit_arith(4, dst, x);
740 void Assembler::and_(const Operand& dst, Register src) {
741 EnsureSpace ensure_space(this);
743 emit_operand(src, dst);
747 void Assembler::cmpb(const Operand& op, int8_t imm8) {
748 EnsureSpace ensure_space(this);
749 if (op.is_reg(eax)) {
753 emit_operand(edi, op); // edi == 7
759 void Assembler::cmpb(const Operand& op, Register reg) {
760 CHECK(reg.is_byte_register());
761 EnsureSpace ensure_space(this);
763 emit_operand(reg, op);
767 void Assembler::cmpb(Register reg, const Operand& op) {
768 CHECK(reg.is_byte_register());
769 EnsureSpace ensure_space(this);
771 emit_operand(reg, op);
775 void Assembler::cmpw(const Operand& op, Immediate imm16) {
776 ASSERT(imm16.is_int16());
777 EnsureSpace ensure_space(this);
780 emit_operand(edi, op);
785 void Assembler::cmp(Register reg, int32_t imm32) {
786 EnsureSpace ensure_space(this);
787 emit_arith(7, Operand(reg), Immediate(imm32));
791 void Assembler::cmp(Register reg, Handle<Object> handle) {
792 EnsureSpace ensure_space(this);
793 emit_arith(7, Operand(reg), Immediate(handle));
797 void Assembler::cmp(Register reg, const Operand& op) {
798 EnsureSpace ensure_space(this);
800 emit_operand(reg, op);
804 void Assembler::cmp(const Operand& op, const Immediate& imm) {
805 EnsureSpace ensure_space(this);
806 emit_arith(7, op, imm);
810 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
811 EnsureSpace ensure_space(this);
812 emit_arith(7, op, Immediate(handle));
816 void Assembler::cmpb_al(const Operand& op) {
817 EnsureSpace ensure_space(this);
818 EMIT(0x38); // CMP r/m8, r8
819 emit_operand(eax, op); // eax has same code as register al.
823 void Assembler::cmpw_ax(const Operand& op) {
824 EnsureSpace ensure_space(this);
826 EMIT(0x39); // CMP r/m16, r16
827 emit_operand(eax, op); // eax has same code as register ax.
831 void Assembler::dec_b(Register dst) {
832 CHECK(dst.is_byte_register());
833 EnsureSpace ensure_space(this);
835 EMIT(0xC8 | dst.code());
839 void Assembler::dec_b(const Operand& dst) {
840 EnsureSpace ensure_space(this);
842 emit_operand(ecx, dst);
846 void Assembler::dec(Register dst) {
847 EnsureSpace ensure_space(this);
848 EMIT(0x48 | dst.code());
852 void Assembler::dec(const Operand& dst) {
853 EnsureSpace ensure_space(this);
855 emit_operand(ecx, dst);
859 void Assembler::cdq() {
860 EnsureSpace ensure_space(this);
865 void Assembler::idiv(Register src) {
866 EnsureSpace ensure_space(this);
868 EMIT(0xF8 | src.code());
872 void Assembler::imul(Register reg) {
873 EnsureSpace ensure_space(this);
875 EMIT(0xE8 | reg.code());
879 void Assembler::imul(Register dst, const Operand& src) {
880 EnsureSpace ensure_space(this);
883 emit_operand(dst, src);
887 void Assembler::imul(Register dst, Register src, int32_t imm32) {
888 EnsureSpace ensure_space(this);
889 if (is_int8(imm32)) {
891 EMIT(0xC0 | dst.code() << 3 | src.code());
895 EMIT(0xC0 | dst.code() << 3 | src.code());
901 void Assembler::inc(Register dst) {
902 EnsureSpace ensure_space(this);
903 EMIT(0x40 | dst.code());
907 void Assembler::inc(const Operand& dst) {
908 EnsureSpace ensure_space(this);
910 emit_operand(eax, dst);
914 void Assembler::lea(Register dst, const Operand& src) {
915 EnsureSpace ensure_space(this);
917 emit_operand(dst, src);
921 void Assembler::mul(Register src) {
922 EnsureSpace ensure_space(this);
924 EMIT(0xE0 | src.code());
928 void Assembler::neg(Register dst) {
929 EnsureSpace ensure_space(this);
931 EMIT(0xD8 | dst.code());
935 void Assembler::not_(Register dst) {
936 EnsureSpace ensure_space(this);
938 EMIT(0xD0 | dst.code());
942 void Assembler::or_(Register dst, int32_t imm32) {
943 EnsureSpace ensure_space(this);
944 emit_arith(1, Operand(dst), Immediate(imm32));
948 void Assembler::or_(Register dst, const Operand& src) {
949 EnsureSpace ensure_space(this);
951 emit_operand(dst, src);
955 void Assembler::or_(const Operand& dst, const Immediate& x) {
956 EnsureSpace ensure_space(this);
957 emit_arith(1, dst, x);
961 void Assembler::or_(const Operand& dst, Register src) {
962 EnsureSpace ensure_space(this);
964 emit_operand(src, dst);
968 void Assembler::rcl(Register dst, uint8_t imm8) {
969 EnsureSpace ensure_space(this);
970 ASSERT(is_uint5(imm8)); // illegal shift count
973 EMIT(0xD0 | dst.code());
976 EMIT(0xD0 | dst.code());
982 void Assembler::rcr(Register dst, uint8_t imm8) {
983 EnsureSpace ensure_space(this);
984 ASSERT(is_uint5(imm8)); // illegal shift count
987 EMIT(0xD8 | dst.code());
990 EMIT(0xD8 | dst.code());
996 void Assembler::ror(Register dst, uint8_t imm8) {
997 EnsureSpace ensure_space(this);
998 ASSERT(is_uint5(imm8)); // illegal shift count
1001 EMIT(0xC8 | dst.code());
1004 EMIT(0xC8 | dst.code());
1010 void Assembler::ror_cl(Register dst) {
1011 EnsureSpace ensure_space(this);
1013 EMIT(0xC8 | dst.code());
1017 void Assembler::sar(Register dst, uint8_t imm8) {
1018 EnsureSpace ensure_space(this);
1019 ASSERT(is_uint5(imm8)); // illegal shift count
1022 EMIT(0xF8 | dst.code());
1025 EMIT(0xF8 | dst.code());
1031 void Assembler::sar_cl(Register dst) {
1032 EnsureSpace ensure_space(this);
1034 EMIT(0xF8 | dst.code());
1038 void Assembler::sbb(Register dst, const Operand& src) {
1039 EnsureSpace ensure_space(this);
1041 emit_operand(dst, src);
1045 void Assembler::shld(Register dst, const Operand& src) {
1046 EnsureSpace ensure_space(this);
1049 emit_operand(dst, src);
1053 void Assembler::shl(Register dst, uint8_t imm8) {
1054 EnsureSpace ensure_space(this);
1055 ASSERT(is_uint5(imm8)); // illegal shift count
1058 EMIT(0xE0 | dst.code());
1061 EMIT(0xE0 | dst.code());
1067 void Assembler::shl_cl(Register dst) {
1068 EnsureSpace ensure_space(this);
1070 EMIT(0xE0 | dst.code());
1074 void Assembler::shrd(Register dst, const Operand& src) {
1075 EnsureSpace ensure_space(this);
1078 emit_operand(dst, src);
1082 void Assembler::shr(Register dst, uint8_t imm8) {
1083 EnsureSpace ensure_space(this);
1084 ASSERT(is_uint5(imm8)); // illegal shift count
1087 EMIT(0xE8 | dst.code());
1090 EMIT(0xE8 | dst.code());
1096 void Assembler::shr_cl(Register dst) {
1097 EnsureSpace ensure_space(this);
1099 EMIT(0xE8 | dst.code());
1103 void Assembler::sub(const Operand& dst, const Immediate& x) {
1104 EnsureSpace ensure_space(this);
1105 emit_arith(5, dst, x);
1109 void Assembler::sub(Register dst, const Operand& src) {
1110 EnsureSpace ensure_space(this);
1112 emit_operand(dst, src);
1116 void Assembler::sub(const Operand& dst, Register src) {
1117 EnsureSpace ensure_space(this);
1119 emit_operand(src, dst);
1123 void Assembler::test(Register reg, const Immediate& imm) {
1124 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1125 test_b(reg, imm.x_);
1129 EnsureSpace ensure_space(this);
1130 // This is not using emit_arith because test doesn't support
1131 // sign-extension of 8-bit operands.
1136 EMIT(0xC0 | reg.code());
1142 void Assembler::test(Register reg, const Operand& op) {
1143 EnsureSpace ensure_space(this);
1145 emit_operand(reg, op);
1149 void Assembler::test_b(Register reg, const Operand& op) {
1150 CHECK(reg.is_byte_register());
1151 EnsureSpace ensure_space(this);
1153 emit_operand(reg, op);
1157 void Assembler::test(const Operand& op, const Immediate& imm) {
1158 if (op.is_reg_only()) {
1159 test(op.reg(), imm);
1162 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1163 return test_b(op, imm.x_);
1165 EnsureSpace ensure_space(this);
1167 emit_operand(eax, op);
1172 void Assembler::test_b(Register reg, uint8_t imm8) {
1173 EnsureSpace ensure_space(this);
1174 // Only use test against byte for registers that have a byte
1175 // variant: eax, ebx, ecx, and edx.
1179 } else if (reg.is_byte_register()) {
1180 emit_arith_b(0xF6, 0xC0, reg, imm8);
1183 EMIT(0xC0 | reg.code());
1189 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1190 if (op.is_reg_only()) {
1191 test_b(op.reg(), imm8);
1194 EnsureSpace ensure_space(this);
1196 emit_operand(eax, op);
1201 void Assembler::xor_(Register dst, int32_t imm32) {
1202 EnsureSpace ensure_space(this);
1203 emit_arith(6, Operand(dst), Immediate(imm32));
1207 void Assembler::xor_(Register dst, const Operand& src) {
1208 EnsureSpace ensure_space(this);
1210 emit_operand(dst, src);
1214 void Assembler::xor_(const Operand& dst, Register src) {
1215 EnsureSpace ensure_space(this);
1217 emit_operand(src, dst);
1221 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1222 EnsureSpace ensure_space(this);
1223 emit_arith(6, dst, x);
1227 void Assembler::bt(const Operand& dst, Register src) {
1228 EnsureSpace ensure_space(this);
1231 emit_operand(src, dst);
1235 void Assembler::bts(const Operand& dst, Register src) {
1236 EnsureSpace ensure_space(this);
1239 emit_operand(src, dst);
1243 void Assembler::bsr(Register dst, const Operand& src) {
1244 EnsureSpace ensure_space(this);
1247 emit_operand(dst, src);
1251 void Assembler::hlt() {
1252 EnsureSpace ensure_space(this);
1257 void Assembler::int3() {
1258 EnsureSpace ensure_space(this);
1263 void Assembler::nop() {
1264 EnsureSpace ensure_space(this);
1269 void Assembler::ret(int imm16) {
1270 EnsureSpace ensure_space(this);
1271 ASSERT(is_uint16(imm16));
1277 EMIT((imm16 >> 8) & 0xFF);
1282 // Labels refer to positions in the (to be) generated code.
1283 // There are bound, linked, and unused labels.
1285 // Bound labels refer to known positions in the already
1286 // generated code. pos() is the position the label refers to.
1288 // Linked labels refer to unknown positions in the code
1289 // to be generated; pos() is the position of the 32bit
1290 // Displacement of the last instruction using the label.
1293 void Assembler::print(Label* L) {
1294 if (L->is_unused()) {
1295 PrintF("unused label\n");
1296 } else if (L->is_bound()) {
1297 PrintF("bound label to %d\n", L->pos());
1298 } else if (L->is_linked()) {
1300 PrintF("unbound label");
1301 while (l.is_linked()) {
1302 Displacement disp = disp_at(&l);
1303 PrintF("@ %d ", l.pos());
1309 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1314 void Assembler::bind_to(Label* L, int pos) {
1315 EnsureSpace ensure_space(this);
1316 ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1317 while (L->is_linked()) {
1318 Displacement disp = disp_at(L);
1319 int fixup_pos = L->pos();
1320 if (disp.type() == Displacement::CODE_RELATIVE) {
1321 // Relative to Code* heap object pointer.
1322 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1324 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1325 ASSERT(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1327 // Relative address, relative to point after address.
1328 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1329 long_at_put(fixup_pos, imm32);
1333 while (L->is_near_linked()) {
1334 int fixup_pos = L->near_link_pos();
1335 int offset_to_next =
1336 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1337 ASSERT(offset_to_next <= 0);
1338 // Relative address, relative to point after address.
1339 int disp = pos - fixup_pos - sizeof(int8_t);
1340 CHECK(0 <= disp && disp <= 127);
1341 set_byte_at(fixup_pos, disp);
1342 if (offset_to_next < 0) {
1343 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1352 void Assembler::bind(Label* L) {
1353 EnsureSpace ensure_space(this);
1354 ASSERT(!L->is_bound()); // label can only be bound once
1355 bind_to(L, pc_offset());
1359 void Assembler::call(Label* L) {
1360 positions_recorder()->WriteRecordedPositions();
1361 EnsureSpace ensure_space(this);
1362 if (L->is_bound()) {
1363 const int long_size = 5;
1364 int offs = L->pos() - pc_offset();
1366 // 1110 1000 #32-bit disp.
1368 emit(offs - long_size);
1370 // 1110 1000 #32-bit disp.
1372 emit_disp(L, Displacement::OTHER);
1377 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1378 positions_recorder()->WriteRecordedPositions();
1379 EnsureSpace ensure_space(this);
1380 ASSERT(!RelocInfo::IsCodeTarget(rmode));
1382 if (RelocInfo::IsRuntimeEntry(rmode)) {
1383 emit(reinterpret_cast<uint32_t>(entry), rmode);
1385 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1390 int Assembler::CallSize(const Operand& adr) {
1391 // Call size is 1 (opcode) + adr.len_ (operand).
1392 return 1 + adr.len_;
1396 void Assembler::call(const Operand& adr) {
1397 positions_recorder()->WriteRecordedPositions();
1398 EnsureSpace ensure_space(this);
1400 emit_operand(edx, adr);
1404 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1405 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1409 void Assembler::call(Handle<Code> code,
1410 RelocInfo::Mode rmode,
1411 TypeFeedbackId ast_id) {
1412 positions_recorder()->WriteRecordedPositions();
1413 EnsureSpace ensure_space(this);
1414 ASSERT(RelocInfo::IsCodeTarget(rmode)
1415 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1417 emit(code, rmode, ast_id);
1421 void Assembler::jmp(Label* L, Label::Distance distance) {
1422 EnsureSpace ensure_space(this);
1423 if (L->is_bound()) {
1424 const int short_size = 2;
1425 const int long_size = 5;
1426 int offs = L->pos() - pc_offset();
1428 if (is_int8(offs - short_size)) {
1429 // 1110 1011 #8-bit disp.
1431 EMIT((offs - short_size) & 0xFF);
1433 // 1110 1001 #32-bit disp.
1435 emit(offs - long_size);
1437 } else if (distance == Label::kNear) {
1441 // 1110 1001 #32-bit disp.
1443 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1448 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1449 EnsureSpace ensure_space(this);
1450 ASSERT(!RelocInfo::IsCodeTarget(rmode));
1452 if (RelocInfo::IsRuntimeEntry(rmode)) {
1453 emit(reinterpret_cast<uint32_t>(entry), rmode);
1455 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1460 void Assembler::jmp(const Operand& adr) {
1461 EnsureSpace ensure_space(this);
1463 emit_operand(esp, adr);
1467 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1468 EnsureSpace ensure_space(this);
1469 ASSERT(RelocInfo::IsCodeTarget(rmode));
1475 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1476 EnsureSpace ensure_space(this);
1477 ASSERT(0 <= cc && static_cast<int>(cc) < 16);
1478 if (L->is_bound()) {
1479 const int short_size = 2;
1480 const int long_size = 6;
1481 int offs = L->pos() - pc_offset();
1483 if (is_int8(offs - short_size)) {
1484 // 0111 tttn #8-bit disp
1486 EMIT((offs - short_size) & 0xFF);
1488 // 0000 1111 1000 tttn #32-bit disp
1491 emit(offs - long_size);
1493 } else if (distance == Label::kNear) {
1497 // 0000 1111 1000 tttn #32-bit disp
1498 // Note: could eliminate cond. jumps to this jump if condition
1499 // is the same however, seems to be rather unlikely case.
1502 emit_disp(L, Displacement::OTHER);
1507 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1508 EnsureSpace ensure_space(this);
1509 ASSERT((0 <= cc) && (static_cast<int>(cc) < 16));
1510 // 0000 1111 1000 tttn #32-bit disp.
1513 if (RelocInfo::IsRuntimeEntry(rmode)) {
1514 emit(reinterpret_cast<uint32_t>(entry), rmode);
1516 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1521 void Assembler::j(Condition cc, Handle<Code> code) {
1522 EnsureSpace ensure_space(this);
1523 // 0000 1111 1000 tttn #32-bit disp
1526 emit(code, RelocInfo::CODE_TARGET);
1530 // FPU instructions.
1532 void Assembler::fld(int i) {
1533 EnsureSpace ensure_space(this);
1534 emit_farith(0xD9, 0xC0, i);
1538 void Assembler::fstp(int i) {
1539 EnsureSpace ensure_space(this);
1540 emit_farith(0xDD, 0xD8, i);
1544 void Assembler::fld1() {
1545 EnsureSpace ensure_space(this);
1551 void Assembler::fldpi() {
1552 EnsureSpace ensure_space(this);
1558 void Assembler::fldz() {
1559 EnsureSpace ensure_space(this);
1565 void Assembler::fldln2() {
1566 EnsureSpace ensure_space(this);
1572 void Assembler::fld_s(const Operand& adr) {
1573 EnsureSpace ensure_space(this);
1575 emit_operand(eax, adr);
1579 void Assembler::fld_d(const Operand& adr) {
1580 EnsureSpace ensure_space(this);
1582 emit_operand(eax, adr);
1586 void Assembler::fstp_s(const Operand& adr) {
1587 EnsureSpace ensure_space(this);
1589 emit_operand(ebx, adr);
1593 void Assembler::fst_s(const Operand& adr) {
1594 EnsureSpace ensure_space(this);
1596 emit_operand(edx, adr);
1600 void Assembler::fstp_d(const Operand& adr) {
1601 EnsureSpace ensure_space(this);
1603 emit_operand(ebx, adr);
1607 void Assembler::fst_d(const Operand& adr) {
1608 EnsureSpace ensure_space(this);
1610 emit_operand(edx, adr);
1614 void Assembler::fild_s(const Operand& adr) {
1615 EnsureSpace ensure_space(this);
1617 emit_operand(eax, adr);
1621 void Assembler::fild_d(const Operand& adr) {
1622 EnsureSpace ensure_space(this);
1624 emit_operand(ebp, adr);
1628 void Assembler::fistp_s(const Operand& adr) {
1629 EnsureSpace ensure_space(this);
1631 emit_operand(ebx, adr);
1635 void Assembler::fisttp_s(const Operand& adr) {
1636 ASSERT(IsEnabled(SSE3));
1637 EnsureSpace ensure_space(this);
1639 emit_operand(ecx, adr);
1643 void Assembler::fisttp_d(const Operand& adr) {
1644 ASSERT(IsEnabled(SSE3));
1645 EnsureSpace ensure_space(this);
1647 emit_operand(ecx, adr);
1651 void Assembler::fist_s(const Operand& adr) {
1652 EnsureSpace ensure_space(this);
1654 emit_operand(edx, adr);
1658 void Assembler::fistp_d(const Operand& adr) {
1659 EnsureSpace ensure_space(this);
1661 emit_operand(edi, adr);
1665 void Assembler::fabs() {
1666 EnsureSpace ensure_space(this);
1672 void Assembler::fchs() {
1673 EnsureSpace ensure_space(this);
1679 void Assembler::fcos() {
1680 EnsureSpace ensure_space(this);
1686 void Assembler::fsin() {
1687 EnsureSpace ensure_space(this);
1693 void Assembler::fptan() {
1694 EnsureSpace ensure_space(this);
1700 void Assembler::fyl2x() {
1701 EnsureSpace ensure_space(this);
1707 void Assembler::f2xm1() {
1708 EnsureSpace ensure_space(this);
1714 void Assembler::fscale() {
1715 EnsureSpace ensure_space(this);
1721 void Assembler::fninit() {
1722 EnsureSpace ensure_space(this);
1728 void Assembler::fadd(int i) {
1729 EnsureSpace ensure_space(this);
1730 emit_farith(0xDC, 0xC0, i);
1734 void Assembler::fadd_i(int i) {
1735 EnsureSpace ensure_space(this);
1736 emit_farith(0xD8, 0xC0, i);
1740 void Assembler::fsub(int i) {
1741 EnsureSpace ensure_space(this);
1742 emit_farith(0xDC, 0xE8, i);
1746 void Assembler::fsub_i(int i) {
1747 EnsureSpace ensure_space(this);
1748 emit_farith(0xD8, 0xE0, i);
1752 void Assembler::fisub_s(const Operand& adr) {
1753 EnsureSpace ensure_space(this);
1755 emit_operand(esp, adr);
1759 void Assembler::fmul_i(int i) {
1760 EnsureSpace ensure_space(this);
1761 emit_farith(0xD8, 0xC8, i);
1765 void Assembler::fmul(int i) {
1766 EnsureSpace ensure_space(this);
1767 emit_farith(0xDC, 0xC8, i);
1771 void Assembler::fdiv(int i) {
1772 EnsureSpace ensure_space(this);
1773 emit_farith(0xDC, 0xF8, i);
1777 void Assembler::fdiv_i(int i) {
1778 EnsureSpace ensure_space(this);
1779 emit_farith(0xD8, 0xF0, i);
1783 void Assembler::faddp(int i) {
1784 EnsureSpace ensure_space(this);
1785 emit_farith(0xDE, 0xC0, i);
1789 void Assembler::fsubp(int i) {
1790 EnsureSpace ensure_space(this);
1791 emit_farith(0xDE, 0xE8, i);
1795 void Assembler::fsubrp(int i) {
1796 EnsureSpace ensure_space(this);
1797 emit_farith(0xDE, 0xE0, i);
1801 void Assembler::fmulp(int i) {
1802 EnsureSpace ensure_space(this);
1803 emit_farith(0xDE, 0xC8, i);
1807 void Assembler::fdivp(int i) {
1808 EnsureSpace ensure_space(this);
1809 emit_farith(0xDE, 0xF8, i);
1813 void Assembler::fprem() {
1814 EnsureSpace ensure_space(this);
1820 void Assembler::fprem1() {
1821 EnsureSpace ensure_space(this);
1827 void Assembler::fxch(int i) {
1828 EnsureSpace ensure_space(this);
1829 emit_farith(0xD9, 0xC8, i);
1833 void Assembler::fincstp() {
1834 EnsureSpace ensure_space(this);
1840 void Assembler::ffree(int i) {
1841 EnsureSpace ensure_space(this);
1842 emit_farith(0xDD, 0xC0, i);
1846 void Assembler::ftst() {
1847 EnsureSpace ensure_space(this);
1853 void Assembler::fucomp(int i) {
1854 EnsureSpace ensure_space(this);
1855 emit_farith(0xDD, 0xE8, i);
1859 void Assembler::fucompp() {
1860 EnsureSpace ensure_space(this);
1866 void Assembler::fucomi(int i) {
1867 EnsureSpace ensure_space(this);
1873 void Assembler::fucomip() {
1874 EnsureSpace ensure_space(this);
1880 void Assembler::fcompp() {
1881 EnsureSpace ensure_space(this);
1887 void Assembler::fnstsw_ax() {
1888 EnsureSpace ensure_space(this);
1894 void Assembler::fwait() {
1895 EnsureSpace ensure_space(this);
1900 void Assembler::frndint() {
1901 EnsureSpace ensure_space(this);
1907 void Assembler::fnclex() {
1908 EnsureSpace ensure_space(this);
1914 void Assembler::sahf() {
1915 EnsureSpace ensure_space(this);
1920 void Assembler::setcc(Condition cc, Register reg) {
1921 ASSERT(reg.is_byte_register());
1922 EnsureSpace ensure_space(this);
1925 EMIT(0xC0 | reg.code());
1929 void Assembler::cvttss2si(Register dst, const Operand& src) {
1930 EnsureSpace ensure_space(this);
1934 emit_operand(dst, src);
1938 void Assembler::cvttsd2si(Register dst, const Operand& src) {
1939 EnsureSpace ensure_space(this);
1943 emit_operand(dst, src);
1947 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
1948 EnsureSpace ensure_space(this);
1952 emit_sse_operand(dst, src);
1956 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
1957 EnsureSpace ensure_space(this);
1961 emit_sse_operand(dst, src);
1965 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1966 EnsureSpace ensure_space(this);
1970 emit_sse_operand(dst, src);
1974 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1975 EnsureSpace ensure_space(this);
1979 emit_sse_operand(dst, src);
1983 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1984 EnsureSpace ensure_space(this);
1988 emit_sse_operand(dst, src);
1992 void Assembler::addsd(XMMRegister dst, const Operand& src) {
1993 EnsureSpace ensure_space(this);
1997 emit_sse_operand(dst, src);
2001 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2002 EnsureSpace ensure_space(this);
2006 emit_sse_operand(dst, src);
2010 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2011 EnsureSpace ensure_space(this);
2015 emit_sse_operand(dst, src);
2019 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2020 EnsureSpace ensure_space(this);
2024 emit_sse_operand(dst, src);
2028 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2029 EnsureSpace ensure_space(this);
2033 emit_sse_operand(dst, src);
2037 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2038 EnsureSpace ensure_space(this);
2042 emit_sse_operand(dst, src);
2046 void Assembler::xorpd(XMMRegister dst, const Operand& src) {
2047 EnsureSpace ensure_space(this);
2051 emit_sse_operand(dst, src);
2055 void Assembler::andps(XMMRegister dst, const Operand& src) {
2056 EnsureSpace ensure_space(this);
2059 emit_sse_operand(dst, src);
2063 void Assembler::orps(XMMRegister dst, const Operand& src) {
2064 EnsureSpace ensure_space(this);
2067 emit_sse_operand(dst, src);
2071 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2072 EnsureSpace ensure_space(this);
2075 emit_sse_operand(dst, src);
2079 void Assembler::addps(XMMRegister dst, const Operand& src) {
2080 EnsureSpace ensure_space(this);
2083 emit_sse_operand(dst, src);
2087 void Assembler::subps(XMMRegister dst, const Operand& src) {
2088 EnsureSpace ensure_space(this);
2091 emit_sse_operand(dst, src);
2095 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2096 EnsureSpace ensure_space(this);
2099 emit_sse_operand(dst, src);
2103 void Assembler::divps(XMMRegister dst, const Operand& src) {
2104 EnsureSpace ensure_space(this);
2107 emit_sse_operand(dst, src);
2111 void Assembler::addpd(XMMRegister dst, const Operand& src) {
2112 EnsureSpace ensure_space(this);
2116 emit_sse_operand(dst, src);
2120 void Assembler::subpd(XMMRegister dst, const Operand& src) {
2121 EnsureSpace ensure_space(this);
2125 emit_sse_operand(dst, src);
2129 void Assembler::mulpd(XMMRegister dst, const Operand& src) {
2130 EnsureSpace ensure_space(this);
2134 emit_sse_operand(dst, src);
2138 void Assembler::divpd(XMMRegister dst, const Operand& src) {
2139 EnsureSpace ensure_space(this);
2143 emit_sse_operand(dst, src);
2147 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2148 EnsureSpace ensure_space(this);
2152 emit_sse_operand(dst, src);
2156 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2157 EnsureSpace ensure_space(this);
2161 emit_sse_operand(dst, src);
2165 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2166 EnsureSpace ensure_space(this);
2170 emit_sse_operand(dst, src);
2174 void Assembler::andpd(XMMRegister dst, const Operand& src) {
2175 EnsureSpace ensure_space(this);
2179 emit_sse_operand(dst, src);
2183 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2184 EnsureSpace ensure_space(this);
2188 emit_sse_operand(dst, src);
2192 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2193 EnsureSpace ensure_space(this);
2197 emit_sse_operand(dst, src);
2201 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2202 ASSERT(IsEnabled(SSE4_1));
2203 EnsureSpace ensure_space(this);
2208 emit_sse_operand(dst, src);
2209 // Mask precision exeption.
2210 EMIT(static_cast<byte>(mode) | 0x8);
2214 void Assembler::movmskpd(Register dst, XMMRegister src) {
2215 EnsureSpace ensure_space(this);
2219 emit_sse_operand(dst, src);
2223 void Assembler::movmskps(Register dst, XMMRegister src) {
2224 EnsureSpace ensure_space(this);
2227 emit_sse_operand(dst, src);
2231 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2232 EnsureSpace ensure_space(this);
2236 emit_sse_operand(dst, src);
2240 void Assembler::pcmpgtd(XMMRegister dst, XMMRegister src) {
2241 EnsureSpace ensure_space(this);
2245 emit_sse_operand(dst, src);
2249 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2250 EnsureSpace ensure_space(this);
2254 emit_sse_operand(dst, src);
2259 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2260 EnsureSpace ensure_space(this);
2263 emit_sse_operand(dst, src);
2267 void Assembler::movups(XMMRegister dst, const Operand& src) {
2268 EnsureSpace ensure_space(this);
2271 emit_sse_operand(dst, src);
2275 void Assembler::movups(const Operand& dst, XMMRegister src) {
2276 EnsureSpace ensure_space(this);
2279 emit_sse_operand(src, dst);
2283 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2284 ASSERT(is_uint8(imm8));
2285 EnsureSpace ensure_space(this);
2288 emit_sse_operand(dst, src);
2293 void Assembler::shufpd(XMMRegister dst, XMMRegister src, byte imm8) {
2294 ASSERT(is_uint8(imm8));
2295 EnsureSpace ensure_space(this);
2299 emit_sse_operand(dst, src);
2304 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2305 EnsureSpace ensure_space(this);
2309 emit_sse_operand(src, dst);
2313 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2314 EnsureSpace ensure_space(this);
2318 emit_sse_operand(dst, src);
2322 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2323 EnsureSpace ensure_space(this);
2327 emit_sse_operand(src, dst);
2331 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2332 EnsureSpace ensure_space(this);
2336 emit_sse_operand(dst, src);
2340 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2341 ASSERT(IsEnabled(SSE4_1));
2342 EnsureSpace ensure_space(this);
2347 emit_sse_operand(dst, src);
2351 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2352 EnsureSpace ensure_space(this);
2356 emit_sse_operand(src, dst);
2360 void Assembler::prefetch(const Operand& src, int level) {
2361 ASSERT(is_uint2(level));
2362 EnsureSpace ensure_space(this);
2365 // Emit hint number in Reg position of RegR/M.
2366 XMMRegister code = XMMRegister::from_code(level);
2367 emit_sse_operand(code, src);
2371 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2372 EnsureSpace ensure_space(this);
2373 EMIT(0xF2); // double
2375 EMIT(0x11); // store
2376 emit_sse_operand(src, dst);
2380 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2381 EnsureSpace ensure_space(this);
2382 EMIT(0xF2); // double
2385 emit_sse_operand(dst, src);
2389 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2390 EnsureSpace ensure_space(this);
2391 EMIT(0xF3); // float
2393 EMIT(0x11); // store
2394 emit_sse_operand(src, dst);
2398 void Assembler::movss(XMMRegister dst, const Operand& src) {
2399 EnsureSpace ensure_space(this);
2400 EMIT(0xF3); // float
2403 emit_sse_operand(dst, src);
2407 void Assembler::movd(XMMRegister dst, const Operand& src) {
2408 EnsureSpace ensure_space(this);
2412 emit_sse_operand(dst, src);
2416 void Assembler::movd(const Operand& dst, XMMRegister src) {
2417 EnsureSpace ensure_space(this);
2421 emit_sse_operand(src, dst);
2425 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2426 ASSERT(IsEnabled(SSE4_1));
2427 ASSERT(is_uint8(imm8));
2428 EnsureSpace ensure_space(this);
2433 emit_sse_operand(src, dst);
2438 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2439 EnsureSpace ensure_space(this);
2443 emit_sse_operand(dst, src);
2447 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2448 EnsureSpace ensure_space(this);
2452 emit_sse_operand(dst, src);
2456 void Assembler::por(XMMRegister dst, XMMRegister src) {
2457 EnsureSpace ensure_space(this);
2461 emit_sse_operand(dst, src);
2465 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2466 ASSERT(IsEnabled(SSE4_1));
2467 EnsureSpace ensure_space(this);
2472 emit_sse_operand(dst, src);
2476 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2477 EnsureSpace ensure_space(this);
2481 emit_sse_operand(esi, reg); // esi == 6
2486 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2487 EnsureSpace ensure_space(this);
2491 emit_sse_operand(dst, src);
2495 void Assembler::pslld(XMMRegister reg, int8_t shift) {
2496 EnsureSpace ensure_space(this);
2500 emit_sse_operand(esi, reg); // esi == 6
2505 void Assembler::pslld(XMMRegister dst, XMMRegister src) {
2506 EnsureSpace ensure_space(this);
2510 emit_sse_operand(dst, src);
2514 void Assembler::psrld(XMMRegister reg, int8_t shift) {
2515 EnsureSpace ensure_space(this);
2519 emit_sse_operand(edx, reg); // edx == 2
2524 void Assembler::psrld(XMMRegister dst, XMMRegister src) {
2525 EnsureSpace ensure_space(this);
2529 emit_sse_operand(dst, src);
2533 void Assembler::psrad(XMMRegister reg, int8_t shift) {
2534 EnsureSpace ensure_space(this);
2538 emit_sse_operand(esp, reg); // esp == 4
2543 void Assembler::psrad(XMMRegister dst, XMMRegister src) {
2544 EnsureSpace ensure_space(this);
2548 emit_sse_operand(dst, src);
2552 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2553 EnsureSpace ensure_space(this);
2557 emit_sse_operand(edx, reg); // edx == 2
2562 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2563 EnsureSpace ensure_space(this);
2567 emit_sse_operand(dst, src);
2571 void Assembler::psrldq(XMMRegister dst, int8_t shift) {
2572 EnsureSpace ensure_space(this);
2576 emit_sse_operand(ebx, dst); // ebx == 3
2581 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2582 EnsureSpace ensure_space(this);
2586 emit_sse_operand(dst, src);
2591 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2592 ASSERT(IsEnabled(SSE4_1));
2593 EnsureSpace ensure_space(this);
2598 emit_sse_operand(src, dst);
2603 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2604 ASSERT(IsEnabled(SSE4_1));
2605 EnsureSpace ensure_space(this);
2610 emit_sse_operand(dst, src);
2615 void Assembler::minps(XMMRegister dst, const Operand& src) {
2616 EnsureSpace ensure_space(this);
2619 emit_sse_operand(dst, src);
2623 void Assembler::maxps(XMMRegister dst, const Operand& src) {
2624 EnsureSpace ensure_space(this);
2627 emit_sse_operand(dst, src);
2631 void Assembler::minpd(XMMRegister dst, const Operand& src) {
2632 EnsureSpace ensure_space(this);
2636 emit_sse_operand(dst, src);
2640 void Assembler::maxpd(XMMRegister dst, const Operand& src) {
2641 EnsureSpace ensure_space(this);
2645 emit_sse_operand(dst, src);
2649 void Assembler::rcpps(XMMRegister dst, const Operand& src) {
2650 EnsureSpace ensure_space(this);
2653 emit_sse_operand(dst, src);
2657 void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
2658 EnsureSpace ensure_space(this);
2661 emit_sse_operand(dst, src);
2665 void Assembler::sqrtps(XMMRegister dst, const Operand& src) {
2666 EnsureSpace ensure_space(this);
2669 emit_sse_operand(dst, src);
2673 void Assembler::sqrtpd(XMMRegister dst, const Operand& src) {
2674 EnsureSpace ensure_space(this);
2678 emit_sse_operand(dst, src);
2682 void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
2683 EnsureSpace ensure_space(this);
2686 emit_sse_operand(dst, src);
2690 void Assembler::paddd(XMMRegister dst, const Operand& src) {
2691 EnsureSpace ensure_space(this);
2695 emit_sse_operand(dst, src);
2699 void Assembler::psubd(XMMRegister dst, const Operand& src) {
2700 EnsureSpace ensure_space(this);
2704 emit_sse_operand(dst, src);
2708 void Assembler::pmulld(XMMRegister dst, const Operand& src) {
2709 ASSERT(IsEnabled(SSE4_1));
2710 EnsureSpace ensure_space(this);
2715 emit_sse_operand(dst, src);
2719 void Assembler::pmuludq(XMMRegister dst, const Operand& src) {
2720 EnsureSpace ensure_space(this);
2724 emit_sse_operand(dst, src);
2728 void Assembler::punpackldq(XMMRegister dst, const Operand& src) {
2729 EnsureSpace ensure_space(this);
2733 emit_sse_operand(dst, src);
2737 void Assembler::cvtps2dq(XMMRegister dst, const Operand& src) {
2738 EnsureSpace ensure_space(this);
2742 emit_sse_operand(dst, src);
2746 void Assembler::cmpps(XMMRegister dst, XMMRegister src, int8_t cmp) {
2747 EnsureSpace ensure_space(this);
2750 emit_sse_operand(dst, src);
2755 void Assembler::cmpeqps(XMMRegister dst, XMMRegister src) {
2756 cmpps(dst, src, 0x0);
2760 void Assembler::cmpltps(XMMRegister dst, XMMRegister src) {
2761 cmpps(dst, src, 0x1);
2765 void Assembler::cmpleps(XMMRegister dst, XMMRegister src) {
2766 cmpps(dst, src, 0x2);
2770 void Assembler::cmpneqps(XMMRegister dst, XMMRegister src) {
2771 cmpps(dst, src, 0x4);
2775 void Assembler::cmpnltps(XMMRegister dst, XMMRegister src) {
2776 cmpps(dst, src, 0x5);
2780 void Assembler::cmpnleps(XMMRegister dst, XMMRegister src) {
2781 cmpps(dst, src, 0x6);
2785 void Assembler::insertps(XMMRegister dst, XMMRegister src, byte imm8) {
2786 ASSERT(CpuFeatures::IsSupported(SSE4_1));
2787 ASSERT(is_uint8(imm8));
2788 EnsureSpace ensure_space(this);
2793 emit_sse_operand(dst, src);
2798 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2799 Register ireg = { reg.code() };
2800 emit_operand(ireg, adr);
2804 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2805 EMIT(0xC0 | dst.code() << 3 | src.code());
2809 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2810 EMIT(0xC0 | dst.code() << 3 | src.code());
2814 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2815 EMIT(0xC0 | (dst.code() << 3) | src.code());
2819 void Assembler::Print() {
2820 Disassembler::Decode(isolate(), stdout, buffer_, pc_);
2824 void Assembler::RecordJSReturn() {
2825 positions_recorder()->WriteRecordedPositions();
2826 EnsureSpace ensure_space(this);
2827 RecordRelocInfo(RelocInfo::JS_RETURN);
2831 void Assembler::RecordDebugBreakSlot() {
2832 positions_recorder()->WriteRecordedPositions();
2833 EnsureSpace ensure_space(this);
2834 RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
2838 void Assembler::RecordComment(const char* msg, bool force) {
2839 if (FLAG_code_comments || force) {
2840 EnsureSpace ensure_space(this);
2841 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
2846 void Assembler::GrowBuffer() {
2847 ASSERT(buffer_overflow());
2848 if (!own_buffer_) FATAL("external code buffer is too small");
2850 // Compute new buffer size.
2851 CodeDesc desc; // the new buffer
2852 if (buffer_size_ < 4*KB) {
2853 desc.buffer_size = 4*KB;
2855 desc.buffer_size = 2*buffer_size_;
2857 // Some internal data structures overflow for very large buffers,
2858 // they must ensure that kMaximalBufferSize is not too large.
2859 if ((desc.buffer_size > kMaximalBufferSize) ||
2860 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2861 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2864 // Set up new buffer.
2865 desc.buffer = NewArray<byte>(desc.buffer_size);
2866 desc.instr_size = pc_offset();
2867 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2869 // Clear the buffer in debug mode. Use 'int3' instructions to make
2870 // sure to get into problems if we ever run uninitialized code.
2872 memset(desc.buffer, 0xCC, desc.buffer_size);
2876 int pc_delta = desc.buffer - buffer_;
2877 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2878 MemMove(desc.buffer, buffer_, desc.instr_size);
2879 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2883 if (isolate()->assembler_spare_buffer() == NULL &&
2884 buffer_size_ == kMinimalBufferSize) {
2885 isolate()->set_assembler_spare_buffer(buffer_);
2887 DeleteArray(buffer_);
2889 buffer_ = desc.buffer;
2890 buffer_size_ = desc.buffer_size;
2892 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2893 reloc_info_writer.last_pc() + pc_delta);
2895 // Relocate runtime entries.
2896 for (RelocIterator it(desc); !it.done(); it.next()) {
2897 RelocInfo::Mode rmode = it.rinfo()->rmode();
2898 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
2899 int32_t* p = reinterpret_cast<int32_t*>(it.rinfo()->pc());
2900 if (*p != 0) { // 0 means uninitialized.
2906 ASSERT(!buffer_overflow());
2910 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2911 ASSERT(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2912 ASSERT(is_uint8(imm8));
2913 ASSERT((op1 & 0x01) == 0); // should be 8bit operation
2915 EMIT(op2 | dst.code());
2920 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2921 ASSERT((0 <= sel) && (sel <= 7));
2922 Register ireg = { sel };
2924 EMIT(0x83); // using a sign-extended 8-bit immediate.
2925 emit_operand(ireg, dst);
2927 } else if (dst.is_reg(eax)) {
2928 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2931 EMIT(0x81); // using a literal 32-bit immediate.
2932 emit_operand(ireg, dst);
2938 void Assembler::emit_operand(Register reg, const Operand& adr) {
2939 const unsigned length = adr.len_;
2942 // Emit updated ModRM byte containing the given register.
2943 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2945 // Emit the rest of the encoded operand.
2946 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2949 // Emit relocation information if necessary.
2950 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2951 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2952 RecordRelocInfo(adr.rmode_);
2953 pc_ += sizeof(int32_t);
2958 void Assembler::emit_farith(int b1, int b2, int i) {
2959 ASSERT(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2960 ASSERT(0 <= i && i < 8); // illegal stack offset
2966 void Assembler::db(uint8_t data) {
2967 EnsureSpace ensure_space(this);
2972 void Assembler::dd(uint32_t data) {
2973 EnsureSpace ensure_space(this);
2978 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2979 ASSERT(!RelocInfo::IsNone(rmode));
2980 // Don't record external references unless the heap will be serialized.
2981 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2982 !serializer_enabled() && !emit_debug_code()) {
2985 RelocInfo rinfo(pc_, rmode, data, NULL);
2986 reloc_info_writer.Write(&rinfo);
2990 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2991 // No out-of-line constant pool support.
2992 ASSERT(!FLAG_enable_ool_constant_pool);
2993 return isolate->factory()->empty_constant_pool_array();
2997 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2998 // No out-of-line constant pool support.
2999 ASSERT(!FLAG_enable_ool_constant_pool);
3004 #ifdef GENERATED_CODE_COVERAGE
3005 static FILE* coverage_log = NULL;
3008 static void InitCoverageLog() {
3009 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
3010 if (file_name != NULL) {
3011 coverage_log = fopen(file_name, "aw+");
3016 void LogGeneratedCodeCoverage(const char* file_line) {
3017 const char* return_address = (&file_line)[-1];
3018 char* push_insn = const_cast<char*>(return_address - 12);
3019 push_insn[0] = 0xeb; // Relative branch insn.
3020 push_insn[1] = 13; // Skip over coverage insns.
3021 if (coverage_log != NULL) {
3022 fprintf(coverage_log, "%s\n", file_line);
3023 fflush(coverage_log);
3029 } } // namespace v8::internal
3031 #endif // V8_TARGET_ARCH_IA32