src/v8/src/compiler/instruction-codes.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_
   6 #define V8_COMPILER_INSTRUCTION_CODES_H_
   7
   8 #include <iosfwd>
   9
  10 #if V8_TARGET_ARCH_ARM
  11 #include "src/compiler/arm/instruction-codes-arm.h"
  12 #elif V8_TARGET_ARCH_ARM64
  13 #include "src/compiler/arm64/instruction-codes-arm64.h"
  14 #elif V8_TARGET_ARCH_IA32
  15 #include "src/compiler/ia32/instruction-codes-ia32.h"
  16 #elif V8_TARGET_ARCH_MIPS
  17 #include "src/compiler/mips/instruction-codes-mips.h"
  18 #elif V8_TARGET_ARCH_X64
  19 #include "src/compiler/x64/instruction-codes-x64.h"
  20 #else
  21 #define TARGET_ARCH_OPCODE_LIST(V)
  22 #define TARGET_ADDRESSING_MODE_LIST(V)
  23 #endif
  24 #include "src/utils.h"
  25
  26 namespace v8 {
  27 namespace internal {
  28 namespace compiler {
  29
  30 // Target-specific opcodes that specify which assembly sequence to emit.
  31 // Most opcodes specify a single instruction.
  32 #define ARCH_OPCODE_LIST(V) \
  33   V(ArchCallCodeObject)     \
  34   V(ArchCallJSFunction)     \
  35   V(ArchJmp)                \
  36   V(ArchNop)                \
  37   V(ArchRet)                \
  38   V(ArchStackPointer)       \
  39   V(ArchTruncateDoubleToI)  \
  40   TARGET_ARCH_OPCODE_LIST(V)
  41
  42 enum ArchOpcode {
  43 #define DECLARE_ARCH_OPCODE(Name) k##Name,
  44   ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE)
  45 #undef DECLARE_ARCH_OPCODE
  46 #define COUNT_ARCH_OPCODE(Name) +1
  47   kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE)
  48 #undef COUNT_ARCH_OPCODE
  49 };
  50
  51 std::ostream& operator<<(std::ostream& os, const ArchOpcode& ao);
  52
  53 // Addressing modes represent the "shape" of inputs to an instruction.
  54 // Many instructions support multiple addressing modes. Addressing modes
  55 // are encoded into the InstructionCode of the instruction and tell the
  56 // code generator after register allocation which assembler method to call.
  57 #define ADDRESSING_MODE_LIST(V) \
  58   V(None)                       \
  59   TARGET_ADDRESSING_MODE_LIST(V)
  60
  61 enum AddressingMode {
  62 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name,
  63   ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE)
  64 #undef DECLARE_ADDRESSING_MODE
  65 #define COUNT_ADDRESSING_MODE(Name) +1
  66   kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE)
  67 #undef COUNT_ADDRESSING_MODE
  68 };
  69
  70 std::ostream& operator<<(std::ostream& os, const AddressingMode& am);
  71
  72 // The mode of the flags continuation (see below).
  73 enum FlagsMode { kFlags_none = 0, kFlags_branch = 1, kFlags_set = 2 };
  74
  75 std::ostream& operator<<(std::ostream& os, const FlagsMode& fm);
  76
  77 // The condition of flags continuation (see below).
  78 enum FlagsCondition {
  79   kEqual,
  80   kNotEqual,
  81   kSignedLessThan,
  82   kSignedGreaterThanOrEqual,
  83   kSignedLessThanOrEqual,
  84   kSignedGreaterThan,
  85   kUnsignedLessThan,
  86   kUnsignedGreaterThanOrEqual,
  87   kUnsignedLessThanOrEqual,
  88   kUnsignedGreaterThan,
  89   kUnorderedEqual,
  90   kUnorderedNotEqual,
  91   kUnorderedLessThan,
  92   kUnorderedGreaterThanOrEqual,
  93   kUnorderedLessThanOrEqual,
  94   kUnorderedGreaterThan,
  95   kOverflow,
  96   kNotOverflow
  97 };
  98
  99 std::ostream& operator<<(std::ostream& os, const FlagsCondition& fc);
 100
 101 // The InstructionCode is an opaque, target-specific integer that encodes
 102 // what code to emit for an instruction in the code generator. It is not
 103 // interesting to the register allocator, as the inputs and flags on the
 104 // instructions specify everything of interest.
 105 typedef int32_t InstructionCode;
 106
 107 // Helpers for encoding / decoding InstructionCode into the fields needed
 108 // for code generation. We encode the instruction, addressing mode, and flags
 109 // continuation into a single InstructionCode which is stored as part of
 110 // the instruction.
 111 typedef BitField<ArchOpcode, 0, 7> ArchOpcodeField;
 112 typedef BitField<AddressingMode, 7, 5> AddressingModeField;
 113 typedef BitField<FlagsMode, 12, 2> FlagsModeField;
 114 typedef BitField<FlagsCondition, 14, 5> FlagsConditionField;
 115 typedef BitField<int, 14, 18> MiscField;
 116
 117 }  // namespace compiler
 118 }  // namespace internal
 119 }  // namespace v8
 120
 121 #endif  // V8_COMPILER_INSTRUCTION_CODES_H_