1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_ARM64_SIMULATOR_ARM64_H_
6 #define V8_ARM64_SIMULATOR_ARM64_H_
13 #include "src/allocation.h"
14 #include "src/arm64/assembler-arm64.h"
15 #include "src/arm64/decoder-arm64.h"
16 #include "src/arm64/disasm-arm64.h"
17 #include "src/arm64/instrument-arm64.h"
18 #include "src/assembler.h"
19 #include "src/globals.h"
20 #include "src/utils.h"
22 #define REGISTER_CODE_LIST(R) \
23 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
24 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
25 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
26 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
31 #if !defined(USE_SIMULATOR)
33 // Running without a simulator on a native ARM64 platform.
34 // When running without a simulator we call the entry directly.
35 #define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \
36 (entry(p0, p1, p2, p3, p4))
38 typedef int (*arm64_regexp_matcher)(String* input,
40 const byte* input_start,
41 const byte* input_end,
49 // Call the generated regexp code directly. The code at the entry address
50 // should act as a function matching the type arm64_regexp_matcher.
51 // The ninth argument is a dummy that reserves the space used for
52 // the return address added by the ExitFrame in native calls.
53 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
54 (FUNCTION_CAST<arm64_regexp_matcher>(entry)( \
55 p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8))
57 // Running without a simulator there is nothing to do.
58 class SimulatorStack : public v8::internal::AllStatic {
60 static uintptr_t JsLimitFromCLimit(v8::internal::Isolate* isolate,
66 static uintptr_t RegisterCTryCatch(uintptr_t try_catch_address) {
67 return try_catch_address;
70 static void UnregisterCTryCatch() { }
73 #else // !defined(USE_SIMULATOR)
75 enum ReverseByteMode {
82 // The proper way to initialize a simulated system register (such as NZCV) is as
84 // SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZCV);
85 class SimSystemRegister {
87 // The default constructor represents a register which has no writable bits.
88 // It is not possible to set its value to anything other than 0.
89 SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) { }
91 uint32_t RawValue() const {
95 void SetRawValue(uint32_t new_value) {
96 value_ = (value_ & write_ignore_mask_) | (new_value & ~write_ignore_mask_);
99 uint32_t Bits(int msb, int lsb) const {
100 return unsigned_bitextract_32(msb, lsb, value_);
103 int32_t SignedBits(int msb, int lsb) const {
104 return signed_bitextract_32(msb, lsb, value_);
107 void SetBits(int msb, int lsb, uint32_t bits);
109 // Default system register values.
110 static SimSystemRegister DefaultValueFor(SystemRegister id);
112 #define DEFINE_GETTER(Name, HighBit, LowBit, Func, Type) \
113 Type Name() const { return static_cast<Type>(Func(HighBit, LowBit)); } \
114 void Set##Name(Type bits) { \
115 SetBits(HighBit, LowBit, static_cast<Type>(bits)); \
117 #define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \
118 static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask);
119 SYSTEM_REGISTER_FIELDS_LIST(DEFINE_GETTER, DEFINE_WRITE_IGNORE_MASK)
120 #undef DEFINE_ZERO_BITS
124 // Most system registers only implement a few of the bits in the word. Other
125 // bits are "read-as-zero, write-ignored". The write_ignore_mask argument
126 // describes the bits which are not modifiable.
127 SimSystemRegister(uint32_t value, uint32_t write_ignore_mask)
128 : value_(value), write_ignore_mask_(write_ignore_mask) { }
131 uint32_t write_ignore_mask_;
135 // Represent a register (r0-r31, v0-v31).
136 class SimRegisterBase {
139 void Set(T new_value) {
141 memcpy(&value_, &new_value, sizeof(T));
147 memcpy(&result, &value_, sizeof(T));
156 typedef SimRegisterBase SimRegister; // r0-r31
157 typedef SimRegisterBase SimFPRegister; // v0-v31
160 class Simulator : public DecoderVisitor {
162 explicit Simulator(Decoder<DispatchingDecoderVisitor>* decoder,
163 Isolate* isolate = NULL,
164 FILE* stream = stderr);
170 static void Initialize(Isolate* isolate);
172 static Simulator* current(v8::internal::Isolate* isolate);
176 // Call an arbitrary function taking an arbitrary number of arguments. The
177 // varargs list must be a set of arguments with type CallArgument, and
178 // terminated by CallArgument::End().
179 void CallVoid(byte* entry, CallArgument* args);
181 // Like CallVoid, but expect a return value.
182 int64_t CallInt64(byte* entry, CallArgument* args);
183 double CallDouble(byte* entry, CallArgument* args);
185 // V8 calls into generated JS code with 5 parameters and into
186 // generated RegExp code with 10 parameters. These are convenience functions,
187 // which set up the simulator state and grab the result on return.
188 int64_t CallJS(byte* entry,
189 byte* function_entry,
194 int64_t CallRegExp(byte* entry,
196 int64_t start_offset,
197 const byte* input_start,
198 const byte* input_end,
203 void* return_address,
206 // A wrapper class that stores an argument for one of the above Call
209 // Only arguments up to 64 bits in size are supported.
213 explicit CallArgument(T argument) {
215 DCHECK(sizeof(argument) <= sizeof(bits_));
216 memcpy(&bits_, &argument, sizeof(argument));
220 explicit CallArgument(double argument) {
221 DCHECK(sizeof(argument) == sizeof(bits_));
222 memcpy(&bits_, &argument, sizeof(argument));
226 explicit CallArgument(float argument) {
227 // TODO(all): CallArgument(float) is untested, remove this check once
230 // Make the D register a NaN to try to trap errors if the callee expects a
231 // double. If it expects a float, the callee should ignore the top word.
232 DCHECK(sizeof(kFP64SignallingNaN) == sizeof(bits_));
233 memcpy(&bits_, &kFP64SignallingNaN, sizeof(kFP64SignallingNaN));
234 // Write the float payload to the S register.
235 DCHECK(sizeof(argument) <= sizeof(bits_));
236 memcpy(&bits_, &argument, sizeof(argument));
240 // This indicates the end of the arguments list, so that CallArgument
241 // objects can be passed into varargs functions.
242 static CallArgument End() { return CallArgument(); }
244 int64_t bits() const { return bits_; }
245 bool IsEnd() const { return type_ == NO_ARG; }
246 bool IsX() const { return type_ == X_ARG; }
247 bool IsD() const { return type_ == D_ARG; }
250 enum CallArgumentType { X_ARG, D_ARG, NO_ARG };
252 // All arguments are aligned to at least 64 bits and we don't support
253 // passing bigger arguments, so the payload size can be fixed at 64 bits.
255 CallArgumentType type_;
257 CallArgument() { type_ = NO_ARG; }
261 // Start the debugging command line.
264 bool GetValue(const char* desc, int64_t* value);
266 bool PrintValue(const char* desc);
268 // Push an address onto the JS stack.
269 uintptr_t PushAddress(uintptr_t address);
271 // Pop an address from the JS stack.
272 uintptr_t PopAddress();
274 // Accessor to the internal simulator stack area.
275 uintptr_t StackLimit() const;
279 // Runtime call support.
280 static void* RedirectExternalReference(void* external_function,
281 ExternalReference::Type type);
282 void DoRuntimeCall(Instruction* instr);
284 // Run the simulator.
285 static const Instruction* kEndOfSimAddress;
286 void DecodeInstruction();
288 void RunFrom(Instruction* start);
290 // Simulation helpers.
291 template <typename T>
292 void set_pc(T new_pc) {
293 DCHECK(sizeof(T) == sizeof(pc_));
294 memcpy(&pc_, &new_pc, sizeof(T));
297 Instruction* pc() { return pc_; }
299 void increment_pc() {
301 pc_ = pc_->following();
304 pc_modified_ = false;
307 virtual void Decode(Instruction* instr) {
308 decoder_->Decode(instr);
311 void ExecuteInstruction() {
312 DCHECK(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
320 // Declare all Visitor functions.
321 #define DECLARE(A) void Visit##A(Instruction* instr);
322 VISITOR_LIST(DECLARE)
325 bool IsZeroRegister(unsigned code, Reg31Mode r31mode) const {
326 return ((code == 31) && (r31mode == Reg31IsZeroRegister));
329 // Register accessors.
330 // Return 'size' bits of the value of an integer register, as the specified
331 // type. The value is zero-extended to fill the result.
334 T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
335 DCHECK(code < kNumberOfRegisters);
336 if (IsZeroRegister(code, r31mode)) {
339 return registers_[code].Get<T>();
342 // Common specialized accessors for the reg() template.
343 int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
344 return reg<int32_t>(code, r31mode);
347 int64_t xreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
348 return reg<int64_t>(code, r31mode);
351 // Write 'size' bits of 'value' into an integer register. The value is
352 // zero-extended. This behaviour matches AArch64 register writes.
354 // Like set_reg(), but infer the access size from the template type.
356 void set_reg(unsigned code, T value,
357 Reg31Mode r31mode = Reg31IsZeroRegister) {
358 DCHECK(code < kNumberOfRegisters);
359 if (!IsZeroRegister(code, r31mode))
360 registers_[code].Set(value);
363 // Common specialized accessors for the set_reg() template.
364 void set_wreg(unsigned code, int32_t value,
365 Reg31Mode r31mode = Reg31IsZeroRegister) {
366 set_reg(code, value, r31mode);
369 void set_xreg(unsigned code, int64_t value,
370 Reg31Mode r31mode = Reg31IsZeroRegister) {
371 set_reg(code, value, r31mode);
374 // Commonly-used special cases.
376 void set_lr(T value) {
377 DCHECK(sizeof(T) == kPointerSize);
378 set_reg(kLinkRegCode, value);
382 void set_sp(T value) {
383 DCHECK(sizeof(T) == kPointerSize);
384 set_reg(31, value, Reg31IsStackPointer);
387 int64_t sp() { return xreg(31, Reg31IsStackPointer); }
388 int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); }
390 return xreg(kFramePointerRegCode, Reg31IsStackPointer);
392 Instruction* lr() { return reg<Instruction*>(kLinkRegCode); }
394 Address get_sp() { return reg<Address>(31, Reg31IsStackPointer); }
397 T fpreg(unsigned code) const {
398 DCHECK(code < kNumberOfRegisters);
399 return fpregisters_[code].Get<T>();
402 // Common specialized accessors for the fpreg() template.
403 float sreg(unsigned code) const {
404 return fpreg<float>(code);
407 uint32_t sreg_bits(unsigned code) const {
408 return fpreg<uint32_t>(code);
411 double dreg(unsigned code) const {
412 return fpreg<double>(code);
415 uint64_t dreg_bits(unsigned code) const {
416 return fpreg<uint64_t>(code);
419 double fpreg(unsigned size, unsigned code) const {
421 case kSRegSizeInBits: return sreg(code);
422 case kDRegSizeInBits: return dreg(code);
429 // Write 'value' into a floating-point register. The value is zero-extended.
430 // This behaviour matches AArch64 register writes.
432 void set_fpreg(unsigned code, T value) {
433 DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
434 DCHECK(code < kNumberOfFPRegisters);
435 fpregisters_[code].Set(value);
438 // Common specialized accessors for the set_fpreg() template.
439 void set_sreg(unsigned code, float value) {
440 set_fpreg(code, value);
443 void set_sreg_bits(unsigned code, uint32_t value) {
444 set_fpreg(code, value);
447 void set_dreg(unsigned code, double value) {
448 set_fpreg(code, value);
451 void set_dreg_bits(unsigned code, uint64_t value) {
452 set_fpreg(code, value);
455 SimSystemRegister& nzcv() { return nzcv_; }
456 SimSystemRegister& fpcr() { return fpcr_; }
460 // Simulator breakpoints.
462 Instruction* location;
465 std::vector<Breakpoint> breakpoints_;
466 void SetBreakpoint(Instruction* breakpoint);
467 void ListBreakpoints();
468 void CheckBreakpoints();
470 // Helpers for the 'next' command.
471 // When this is set, the Simulator will insert a breakpoint after the next BL
472 // instruction it meets.
474 // Check if the Simulator should insert a break after the current instruction
475 // for the 'next' command.
476 void CheckBreakNext();
478 // Disassemble instruction at the given address.
479 void PrintInstructionsAt(Instruction* pc, uint64_t count);
481 void PrintSystemRegisters(bool print_all = false);
482 void PrintRegisters(bool print_all_regs = false);
483 void PrintFPRegisters(bool print_all_regs = false);
484 void PrintProcessorState();
485 void PrintWrite(uint8_t* address, uint64_t value, unsigned num_bytes);
486 void LogSystemRegisters() {
487 if (log_parameters_ & LOG_SYS_REGS) PrintSystemRegisters();
489 void LogRegisters() {
490 if (log_parameters_ & LOG_REGS) PrintRegisters();
492 void LogFPRegisters() {
493 if (log_parameters_ & LOG_FP_REGS) PrintFPRegisters();
495 void LogProcessorState() {
496 LogSystemRegisters();
500 void LogWrite(uint8_t* address, uint64_t value, unsigned num_bytes) {
501 if (log_parameters_ & LOG_WRITE) PrintWrite(address, value, num_bytes);
504 int log_parameters() { return log_parameters_; }
505 void set_log_parameters(int new_parameters) {
506 log_parameters_ = new_parameters;
508 if (new_parameters & LOG_DISASM) {
509 PrintF("Run --debug-sim to dynamically turn on disassembler\n");
513 if (new_parameters & LOG_DISASM) {
514 decoder_->InsertVisitorBefore(print_disasm_, this);
516 decoder_->RemoveVisitor(print_disasm_);
520 static inline const char* WRegNameForCode(unsigned code,
521 Reg31Mode mode = Reg31IsZeroRegister);
522 static inline const char* XRegNameForCode(unsigned code,
523 Reg31Mode mode = Reg31IsZeroRegister);
524 static inline const char* SRegNameForCode(unsigned code);
525 static inline const char* DRegNameForCode(unsigned code);
526 static inline const char* VRegNameForCode(unsigned code);
527 static inline int CodeFromName(const char* name);
530 // Simulation helpers ------------------------------------
531 bool ConditionPassed(Condition cond) {
532 SimSystemRegister& flags = nzcv();
551 return flags.C() && !flags.Z();
553 return !(flags.C() && !flags.Z());
555 return flags.N() == flags.V();
557 return flags.N() != flags.V();
559 return !flags.Z() && (flags.N() == flags.V());
561 return !(!flags.Z() && (flags.N() == flags.V()));
562 case nv: // Fall through.
571 bool ConditionFailed(Condition cond) {
572 return !ConditionPassed(cond);
576 void AddSubHelper(Instruction* instr, T op2);
578 T AddWithCarry(bool set_flags,
583 void AddSubWithCarry(Instruction* instr);
585 void LogicalHelper(Instruction* instr, T op2);
587 void ConditionalCompareHelper(Instruction* instr, T op2);
588 void LoadStoreHelper(Instruction* instr,
591 void LoadStorePairHelper(Instruction* instr, AddrMode addrmode);
592 uint8_t* LoadStoreAddress(unsigned addr_reg,
595 void LoadStoreWriteBack(unsigned addr_reg,
598 void CheckMemoryAccess(uint8_t* address, uint8_t* stack);
600 uint64_t MemoryRead(uint8_t* address, unsigned num_bytes);
601 uint8_t MemoryRead8(uint8_t* address);
602 uint16_t MemoryRead16(uint8_t* address);
603 uint32_t MemoryRead32(uint8_t* address);
604 float MemoryReadFP32(uint8_t* address);
605 uint64_t MemoryRead64(uint8_t* address);
606 double MemoryReadFP64(uint8_t* address);
608 void MemoryWrite(uint8_t* address, uint64_t value, unsigned num_bytes);
609 void MemoryWrite32(uint8_t* address, uint32_t value);
610 void MemoryWriteFP32(uint8_t* address, float value);
611 void MemoryWrite64(uint8_t* address, uint64_t value);
612 void MemoryWriteFP64(uint8_t* address, double value);
615 template <typename T>
616 T ShiftOperand(T value,
619 template <typename T>
620 T ExtendValue(T value,
622 unsigned left_shift = 0);
623 template <typename T>
624 void Extract(Instruction* instr);
625 template <typename T>
626 void DataProcessing2Source(Instruction* instr);
627 template <typename T>
628 void BitfieldHelper(Instruction* instr);
630 uint64_t ReverseBits(uint64_t value, unsigned num_bits);
631 uint64_t ReverseBytes(uint64_t value, ReverseByteMode mode);
633 template <typename T>
634 T FPDefaultNaN() const;
636 void FPCompare(double val0, double val1);
637 double FPRoundInt(double value, FPRounding round_mode);
638 double FPToDouble(float value);
639 float FPToFloat(double value, FPRounding round_mode);
640 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
641 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
642 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
643 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
644 int32_t FPToInt32(double value, FPRounding rmode);
645 int64_t FPToInt64(double value, FPRounding rmode);
646 uint32_t FPToUInt32(double value, FPRounding rmode);
647 uint64_t FPToUInt64(double value, FPRounding rmode);
649 template <typename T>
650 T FPAdd(T op1, T op2);
652 template <typename T>
653 T FPDiv(T op1, T op2);
655 template <typename T>
658 template <typename T>
661 template <typename T>
664 template <typename T>
667 template <typename T>
668 T FPMul(T op1, T op2);
670 template <typename T>
671 T FPMulAdd(T a, T op1, T op2);
673 template <typename T>
676 template <typename T>
677 T FPSub(T op1, T op2);
679 // Standard NaN processing.
680 template <typename T>
681 T FPProcessNaN(T op);
683 bool FPProcessNaNs(Instruction* instr);
685 template <typename T>
686 T FPProcessNaNs(T op1, T op2);
688 template <typename T>
689 T FPProcessNaNs3(T op1, T op2, T op3);
691 void CheckStackAlignment();
693 inline void CheckPCSComplianceAndRun();
696 // Corruption values should have their least significant byte cleared to
697 // allow the code of the register being corrupted to be inserted.
698 static const uint64_t kCallerSavedRegisterCorruptionValue =
699 0xca11edc0de000000UL;
700 // This value is a NaN in both 32-bit and 64-bit FP.
701 static const uint64_t kCallerSavedFPRegisterCorruptionValue =
702 0x7ff000007f801000UL;
703 // This value is a mix of 32/64-bits NaN and "verbose" immediate.
704 static const uint64_t kDefaultCPURegisterCorruptionValue =
705 0x7ffbad007f8bad00UL;
707 void CorruptRegisters(CPURegList* list,
708 uint64_t value = kDefaultCPURegisterCorruptionValue);
709 void CorruptAllCallerSavedCPURegisters();
712 // Pseudo Printf instruction
713 void DoPrintf(Instruction* instr);
715 // Processor state ---------------------------------------
719 PrintDisassembler* print_disasm_;
720 void PRINTF_METHOD_CHECKING TraceSim(const char* format, ...);
723 Instrument* instrument_;
725 // General purpose registers. Register 31 is the stack pointer.
726 SimRegister registers_[kNumberOfRegisters];
728 // Floating point registers
729 SimFPRegister fpregisters_[kNumberOfFPRegisters];
732 // bits[31, 27]: Condition flags N, Z, C, and V.
733 // (Negative, Zero, Carry, Overflow)
734 SimSystemRegister nzcv_;
736 // Floating-Point Control Register
737 SimSystemRegister fpcr_;
739 // Only a subset of FPCR features are supported by the simulator. This helper
740 // checks that the FPCR settings are supported.
742 // This is checked when floating-point instructions are executed, not when
743 // FPCR is set. This allows generated code to modify FPCR for external
744 // functions, or to save and restore it when entering and leaving generated
746 void AssertSupportedFPCR() {
747 DCHECK(fpcr().FZ() == 0); // No flush-to-zero support.
748 DCHECK(fpcr().RMode() == FPTieEven); // Ties-to-even rounding only.
750 // The simulator does not support half-precision operations so fpcr().AHP()
751 // is irrelevant, and is not checked here.
754 template <typename T>
755 static int CalcNFlag(T result) {
756 return (result >> (sizeof(T) * 8 - 1)) & 1;
759 static int CalcZFlag(uint64_t result) {
763 static const uint32_t kConditionFlagsMask = 0xf0000000;
767 static const intptr_t stack_protection_size_ = KB;
768 intptr_t stack_size_;
771 Decoder<DispatchingDecoderVisitor>* decoder_;
772 Decoder<DispatchingDecoderVisitor>* disassembler_decoder_;
774 // Indicates if the pc has been modified by the instruction and should not be
775 // automatically incremented.
779 static const char* xreg_names[];
780 static const char* wreg_names[];
781 static const char* sreg_names[];
782 static const char* dreg_names[];
783 static const char* vreg_names[];
786 void set_last_debugger_input(char* input) {
787 DeleteArray(last_debugger_input_);
788 last_debugger_input_ = input;
790 char* last_debugger_input() { return last_debugger_input_; }
791 char* last_debugger_input_;
794 void Init(FILE* stream);
801 // When running with the simulator transition into simulated execution at this
803 #define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \
804 reinterpret_cast<Object*>(Simulator::current(Isolate::Current())->CallJS( \
805 FUNCTION_ADDR(entry), \
808 #define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
809 Simulator::current(Isolate::Current())->CallRegExp( \
811 p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8)
814 // The simulator has its own stack. Thus it has a different stack limit from
815 // the C-based native code.
816 // See also 'class SimulatorStack' in arm/simulator-arm.h.
817 class SimulatorStack : public v8::internal::AllStatic {
819 static uintptr_t JsLimitFromCLimit(v8::internal::Isolate* isolate,
821 return Simulator::current(isolate)->StackLimit();
824 static uintptr_t RegisterCTryCatch(uintptr_t try_catch_address) {
825 Simulator* sim = Simulator::current(Isolate::Current());
826 return sim->PushAddress(try_catch_address);
829 static void UnregisterCTryCatch() {
830 Simulator::current(Isolate::Current())->PopAddress();
834 #endif // !defined(USE_SIMULATOR)
836 } } // namespace v8::internal
838 #endif // V8_ARM64_SIMULATOR_ARM64_H_