1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
7 #if V8_TARGET_ARCH_ARM64
9 #define ARM64_DEFINE_FP_STATICS
11 #include "src/arm64/assembler-arm64-inl.h"
12 #include "src/arm64/instructions-arm64.h"
18 bool Instruction::IsLoad() const {
19 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
23 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
24 return Mask(LoadStorePairLBit) != 0;
26 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreOpMask));
38 case LDR_d: return true;
39 default: return false;
45 bool Instruction::IsStore() const {
46 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
50 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
51 return Mask(LoadStorePairLBit) == 0;
53 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreOpMask));
60 case STR_d: return true;
61 default: return false;
67 static uint64_t RotateRight(uint64_t value,
72 return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) |
77 static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
80 DCHECK((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
82 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
83 uint64_t result = value & ((1UL << width) - 1UL);
84 for (unsigned i = width; i < reg_size; i *= 2) {
85 result |= (result << i);
91 // Logical immediates can't encode zero, so a return value of zero is used to
92 // indicate a failure case. Specifically, where the constraints on imm_s are not
94 uint64_t Instruction::ImmLogical() {
95 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits;
97 int64_t imm_s = ImmSetBits();
98 int64_t imm_r = ImmRotate();
100 // An integer is constructed from the n, imm_s and imm_r bits according to
101 // the following table:
103 // N imms immr size S R
104 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
105 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
106 // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
107 // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
108 // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
109 // 0 11110s xxxxxr 2 UInt(s) UInt(r)
110 // (s bits must not be all set)
112 // A pattern is constructed of size bits, where the least significant S+1
113 // bits are set. The pattern is rotated right by R, and repeated across a
114 // 32 or 64-bit value, depending on destination register width.
121 uint64_t bits = (1UL << (imm_s + 1)) - 1;
122 return RotateRight(bits, imm_r, 64);
124 if ((imm_s >> 1) == 0x1F) {
127 for (int width = 0x20; width >= 0x2; width >>= 1) {
128 if ((imm_s & width) == 0) {
129 int mask = width - 1;
130 if ((imm_s & mask) == mask) {
133 uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1;
134 return RepeatBitsAcrossReg(reg_size,
135 RotateRight(bits, imm_r & mask, width),
145 float Instruction::ImmFP32() {
146 // ImmFP: abcdefgh (8 bits)
147 // Single: aBbb.bbbc.defg.h000.0000.0000.0000.0000 (32 bits)
149 uint32_t bits = ImmFP();
150 uint32_t bit7 = (bits >> 7) & 0x1;
151 uint32_t bit6 = (bits >> 6) & 0x1;
152 uint32_t bit5_to_0 = bits & 0x3f;
153 uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19);
155 return rawbits_to_float(result);
159 double Instruction::ImmFP64() {
160 // ImmFP: abcdefgh (8 bits)
161 // Double: aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000
162 // 0000.0000.0000.0000.0000.0000.0000.0000 (64 bits)
164 uint32_t bits = ImmFP();
165 uint64_t bit7 = (bits >> 7) & 0x1;
166 uint64_t bit6 = (bits >> 6) & 0x1;
167 uint64_t bit5_to_0 = bits & 0x3f;
168 uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48);
170 return rawbits_to_double(result);
174 LSDataSize CalcLSPairDataSize(LoadStorePairOp op) {
179 case LDP_d: return LSDoubleWord;
180 default: return LSWord;
185 int64_t Instruction::ImmPCOffset() {
187 if (IsPCRelAddressing()) {
188 // PC-relative addressing. Only ADR is supported.
190 } else if (BranchType() != UnknownBranchType) {
191 // All PC-relative branches.
192 // Relative branch offsets are instruction-size-aligned.
193 offset = ImmBranch() << kInstructionSizeLog2;
195 // Load literal (offset from PC).
196 DCHECK(IsLdrLiteral());
197 // The offset is always shifted by 2 bits, even for loads to 64-bits
199 offset = ImmLLiteral() << kInstructionSizeLog2;
205 Instruction* Instruction::ImmPCOffsetTarget() {
206 return InstructionAtOffset(ImmPCOffset());
210 bool Instruction::IsValidImmPCOffset(ImmBranchType branch_type,
212 return is_intn(offset, ImmBranchRangeBitwidth(branch_type));
216 bool Instruction::IsTargetInImmPCOffsetRange(Instruction* target) {
217 return IsValidImmPCOffset(BranchType(), DistanceTo(target));
221 void Instruction::SetImmPCOffsetTarget(Instruction* target) {
222 if (IsPCRelAddressing()) {
223 SetPCRelImmTarget(target);
224 } else if (BranchType() != UnknownBranchType) {
225 SetBranchImmTarget(target);
227 SetImmLLiteral(target);
232 void Instruction::SetPCRelImmTarget(Instruction* target) {
233 // ADRP is not supported, so 'this' must point to an ADR instruction.
236 ptrdiff_t target_offset = DistanceTo(target);
238 if (Instruction::IsValidPCRelOffset(target_offset)) {
239 imm = Assembler::ImmPCRelAddress(target_offset);
240 SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
242 PatchingAssembler patcher(this,
243 PatchingAssembler::kAdrFarPatchableNInstrs);
244 patcher.PatchAdrFar(target_offset);
249 void Instruction::SetBranchImmTarget(Instruction* target) {
250 DCHECK(IsAligned(DistanceTo(target), kInstructionSize));
251 Instr branch_imm = 0;
252 uint32_t imm_mask = 0;
253 ptrdiff_t offset = DistanceTo(target) >> kInstructionSizeLog2;
254 switch (BranchType()) {
255 case CondBranchType: {
256 branch_imm = Assembler::ImmCondBranch(offset);
257 imm_mask = ImmCondBranch_mask;
260 case UncondBranchType: {
261 branch_imm = Assembler::ImmUncondBranch(offset);
262 imm_mask = ImmUncondBranch_mask;
265 case CompareBranchType: {
266 branch_imm = Assembler::ImmCmpBranch(offset);
267 imm_mask = ImmCmpBranch_mask;
270 case TestBranchType: {
271 branch_imm = Assembler::ImmTestBranch(offset);
272 imm_mask = ImmTestBranch_mask;
275 default: UNREACHABLE();
277 SetInstructionBits(Mask(~imm_mask) | branch_imm);
281 void Instruction::SetImmLLiteral(Instruction* source) {
282 DCHECK(IsAligned(DistanceTo(source), kInstructionSize));
283 ptrdiff_t offset = DistanceTo(source) >> kLoadLiteralScaleLog2;
284 Instr imm = Assembler::ImmLLiteral(offset);
285 Instr mask = ImmLLiteral_mask;
287 SetInstructionBits(Mask(~mask) | imm);
291 // TODO(jbramley): We can't put this inline in the class because things like
292 // xzr and Register are not defined in that header. Consider adding
293 // instructions-arm64-inl.h to work around this.
294 bool InstructionSequence::IsInlineData() const {
295 // Inline data is encoded as a single movz instruction which writes to xzr
297 return IsMovz() && SixtyFourBits() && (Rd() == xzr.code());
298 // TODO(all): If we extend ::InlineData() to support bigger data, we need
299 // to update this method too.
303 // TODO(jbramley): We can't put this inline in the class because things like
304 // xzr and Register are not defined in that header. Consider adding
305 // instructions-arm64-inl.h to work around this.
306 uint64_t InstructionSequence::InlineData() const {
307 DCHECK(IsInlineData());
308 uint64_t payload = ImmMoveWide();
309 // TODO(all): If we extend ::InlineData() to support bigger data, we need
310 // to update this method too.
315 } } // namespace v8::internal
317 #endif // V8_TARGET_ARCH_ARM64