1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been
34 // modified significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
37 // A light-weight ARM Assembler
38 // Generates user mode instructions for the ARM architecture up to version 5
40 #ifndef V8_ARM_ASSEMBLER_ARM_H_
41 #define V8_ARM_ASSEMBLER_ARM_H_
46 #include "src/arm/constants-arm.h"
47 #include "src/assembler.h"
48 #include "src/serialize.h"
55 // 1) We would prefer to use an enum, but enum values are assignment-
56 // compatible with int, which has caused code-generation bugs.
58 // 2) We would prefer to use a class instead of a struct but we don't like
59 // the register initialization to depend on the particular initialization
60 // order (which appears to be different on OS X, Linux, and Windows for the
61 // installed versions of C++ we tried). Using a struct permits C-style
62 // "initialization". Also, the Register objects cannot be const as this
63 // forces initialization stubs in MSVC, making us dependent on initialization
66 // 3) By not using an enum, we are possibly preventing the compiler from
67 // doing certain constant folds, which may significantly reduce the
68 // code generated for some assembly instructions (because they boil down
69 // to a few constants). If this is a problem, we could change the code
70 // such that we use an enum in optimized mode, and the struct in debug
71 // mode. This way we get the compile-time error checking in debug mode
72 // and best performance in optimized code.
74 // These constants are used in several locations, including static initializers
75 const int kRegister_no_reg_Code = -1;
76 const int kRegister_r0_Code = 0;
77 const int kRegister_r1_Code = 1;
78 const int kRegister_r2_Code = 2;
79 const int kRegister_r3_Code = 3;
80 const int kRegister_r4_Code = 4;
81 const int kRegister_r5_Code = 5;
82 const int kRegister_r6_Code = 6;
83 const int kRegister_r7_Code = 7;
84 const int kRegister_r8_Code = 8;
85 const int kRegister_r9_Code = 9;
86 const int kRegister_r10_Code = 10;
87 const int kRegister_fp_Code = 11;
88 const int kRegister_ip_Code = 12;
89 const int kRegister_sp_Code = 13;
90 const int kRegister_lr_Code = 14;
91 const int kRegister_pc_Code = 15;
95 static const int kNumRegisters = 16;
96 static const int kMaxNumAllocatableRegisters =
97 FLAG_enable_ool_constant_pool ? 8 : 9;
98 static const int kSizeInBytes = 4;
100 inline static int NumAllocatableRegisters();
102 static int ToAllocationIndex(Register reg) {
103 DCHECK(reg.code() < kMaxNumAllocatableRegisters);
107 static Register FromAllocationIndex(int index) {
108 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
109 return from_code(index);
112 static const char* AllocationIndexToString(int index) {
113 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
114 const char* const names[] = {
125 if (FLAG_enable_ool_constant_pool && (index >= 7)) {
126 return names[index + 1];
131 static Register from_code(int code) {
132 Register r = { code };
136 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
137 bool is(Register reg) const { return code_ == reg.code_; }
147 void set_code(int code) {
152 // Unfortunately we can't make this private in a struct.
156 const Register no_reg = { kRegister_no_reg_Code };
158 const Register r0 = { kRegister_r0_Code };
159 const Register r1 = { kRegister_r1_Code };
160 const Register r2 = { kRegister_r2_Code };
161 const Register r3 = { kRegister_r3_Code };
162 const Register r4 = { kRegister_r4_Code };
163 const Register r5 = { kRegister_r5_Code };
164 const Register r6 = { kRegister_r6_Code };
165 // Used as constant pool pointer register if FLAG_enable_ool_constant_pool.
166 const Register r7 = { kRegister_r7_Code };
167 // Used as context register.
168 const Register r8 = { kRegister_r8_Code };
169 // Used as lithium codegen scratch register.
170 const Register r9 = { kRegister_r9_Code };
171 // Used as roots register.
172 const Register r10 = { kRegister_r10_Code };
173 const Register fp = { kRegister_fp_Code };
174 const Register ip = { kRegister_ip_Code };
175 const Register sp = { kRegister_sp_Code };
176 const Register lr = { kRegister_lr_Code };
177 const Register pc = { kRegister_pc_Code };
179 // Single word VFP register.
180 struct SwVfpRegister {
181 static const int kSizeInBytes = 4;
182 bool is_valid() const { return 0 <= code_ && code_ < 32; }
183 bool is(SwVfpRegister reg) const { return code_ == reg.code_; }
192 void split_code(int* vm, int* m) const {
202 // Double word VFP register.
203 struct DwVfpRegister {
204 static const int kMaxNumRegisters = 32;
205 // A few double registers are reserved: one as a scratch register and one to
206 // hold 0.0, that does not fit in the immediate field of vmov instructions.
208 // d15: scratch register.
209 static const int kNumReservedRegisters = 2;
210 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters -
211 kNumReservedRegisters;
212 static const int kSizeInBytes = 8;
214 // Note: the number of registers can be different at snapshot and run-time.
215 // Any code included in the snapshot must be able to run both with 16 or 32
217 inline static int NumRegisters();
218 inline static int NumReservedRegisters();
219 inline static int NumAllocatableRegisters();
221 inline static int ToAllocationIndex(DwVfpRegister reg);
222 static const char* AllocationIndexToString(int index);
223 inline static DwVfpRegister FromAllocationIndex(int index);
225 static DwVfpRegister from_code(int code) {
226 DwVfpRegister r = { code };
230 bool is_valid() const {
231 return 0 <= code_ && code_ < kMaxNumRegisters;
233 bool is(DwVfpRegister reg) const { return code_ == reg.code_; }
242 void split_code(int* vm, int* m) const {
244 *m = (code_ & 0x10) >> 4;
252 typedef DwVfpRegister DoubleRegister;
255 // Double word VFP register d0-15.
256 struct LowDwVfpRegister {
258 static const int kMaxNumLowRegisters = 16;
259 operator DwVfpRegister() const {
260 DwVfpRegister r = { code_ };
263 static LowDwVfpRegister from_code(int code) {
264 LowDwVfpRegister r = { code };
268 bool is_valid() const {
269 return 0 <= code_ && code_ < kMaxNumLowRegisters;
271 bool is(DwVfpRegister reg) const { return code_ == reg.code_; }
272 bool is(LowDwVfpRegister reg) const { return code_ == reg.code_; }
277 SwVfpRegister low() const {
279 reg.code_ = code_ * 2;
281 DCHECK(reg.is_valid());
284 SwVfpRegister high() const {
286 reg.code_ = (code_ * 2) + 1;
288 DCHECK(reg.is_valid());
296 // Quad word NEON register.
297 struct QwNeonRegister {
298 static const int kMaxNumRegisters = 16;
300 static QwNeonRegister from_code(int code) {
301 QwNeonRegister r = { code };
305 bool is_valid() const {
306 return (0 <= code_) && (code_ < kMaxNumRegisters);
308 bool is(QwNeonRegister reg) const { return code_ == reg.code_; }
313 void split_code(int* vm, int* m) const {
315 int encoded_code = code_ << 1;
316 *m = (encoded_code & 0x10) >> 4;
317 *vm = encoded_code & 0x0F;
324 typedef QwNeonRegister QuadRegister;
327 // Support for the VFP registers s0 to s31 (d0 to d15).
328 // Note that "s(N):s(N+1)" is the same as "d(N/2)".
329 const SwVfpRegister s0 = { 0 };
330 const SwVfpRegister s1 = { 1 };
331 const SwVfpRegister s2 = { 2 };
332 const SwVfpRegister s3 = { 3 };
333 const SwVfpRegister s4 = { 4 };
334 const SwVfpRegister s5 = { 5 };
335 const SwVfpRegister s6 = { 6 };
336 const SwVfpRegister s7 = { 7 };
337 const SwVfpRegister s8 = { 8 };
338 const SwVfpRegister s9 = { 9 };
339 const SwVfpRegister s10 = { 10 };
340 const SwVfpRegister s11 = { 11 };
341 const SwVfpRegister s12 = { 12 };
342 const SwVfpRegister s13 = { 13 };
343 const SwVfpRegister s14 = { 14 };
344 const SwVfpRegister s15 = { 15 };
345 const SwVfpRegister s16 = { 16 };
346 const SwVfpRegister s17 = { 17 };
347 const SwVfpRegister s18 = { 18 };
348 const SwVfpRegister s19 = { 19 };
349 const SwVfpRegister s20 = { 20 };
350 const SwVfpRegister s21 = { 21 };
351 const SwVfpRegister s22 = { 22 };
352 const SwVfpRegister s23 = { 23 };
353 const SwVfpRegister s24 = { 24 };
354 const SwVfpRegister s25 = { 25 };
355 const SwVfpRegister s26 = { 26 };
356 const SwVfpRegister s27 = { 27 };
357 const SwVfpRegister s28 = { 28 };
358 const SwVfpRegister s29 = { 29 };
359 const SwVfpRegister s30 = { 30 };
360 const SwVfpRegister s31 = { 31 };
362 const DwVfpRegister no_dreg = { -1 };
363 const LowDwVfpRegister d0 = { 0 };
364 const LowDwVfpRegister d1 = { 1 };
365 const LowDwVfpRegister d2 = { 2 };
366 const LowDwVfpRegister d3 = { 3 };
367 const LowDwVfpRegister d4 = { 4 };
368 const LowDwVfpRegister d5 = { 5 };
369 const LowDwVfpRegister d6 = { 6 };
370 const LowDwVfpRegister d7 = { 7 };
371 const LowDwVfpRegister d8 = { 8 };
372 const LowDwVfpRegister d9 = { 9 };
373 const LowDwVfpRegister d10 = { 10 };
374 const LowDwVfpRegister d11 = { 11 };
375 const LowDwVfpRegister d12 = { 12 };
376 const LowDwVfpRegister d13 = { 13 };
377 const LowDwVfpRegister d14 = { 14 };
378 const LowDwVfpRegister d15 = { 15 };
379 const DwVfpRegister d16 = { 16 };
380 const DwVfpRegister d17 = { 17 };
381 const DwVfpRegister d18 = { 18 };
382 const DwVfpRegister d19 = { 19 };
383 const DwVfpRegister d20 = { 20 };
384 const DwVfpRegister d21 = { 21 };
385 const DwVfpRegister d22 = { 22 };
386 const DwVfpRegister d23 = { 23 };
387 const DwVfpRegister d24 = { 24 };
388 const DwVfpRegister d25 = { 25 };
389 const DwVfpRegister d26 = { 26 };
390 const DwVfpRegister d27 = { 27 };
391 const DwVfpRegister d28 = { 28 };
392 const DwVfpRegister d29 = { 29 };
393 const DwVfpRegister d30 = { 30 };
394 const DwVfpRegister d31 = { 31 };
396 const QwNeonRegister q0 = { 0 };
397 const QwNeonRegister q1 = { 1 };
398 const QwNeonRegister q2 = { 2 };
399 const QwNeonRegister q3 = { 3 };
400 const QwNeonRegister q4 = { 4 };
401 const QwNeonRegister q5 = { 5 };
402 const QwNeonRegister q6 = { 6 };
403 const QwNeonRegister q7 = { 7 };
404 const QwNeonRegister q8 = { 8 };
405 const QwNeonRegister q9 = { 9 };
406 const QwNeonRegister q10 = { 10 };
407 const QwNeonRegister q11 = { 11 };
408 const QwNeonRegister q12 = { 12 };
409 const QwNeonRegister q13 = { 13 };
410 const QwNeonRegister q14 = { 14 };
411 const QwNeonRegister q15 = { 15 };
414 // Aliases for double registers. Defined using #define instead of
415 // "static const DwVfpRegister&" because Clang complains otherwise when a
416 // compilation unit that includes this header doesn't use the variables.
417 #define kFirstCalleeSavedDoubleReg d8
418 #define kLastCalleeSavedDoubleReg d15
419 #define kDoubleRegZero d14
420 #define kScratchDoubleReg d15
423 // Coprocessor register
425 bool is_valid() const { return 0 <= code_ && code_ < 16; }
426 bool is(CRegister creg) const { return code_ == creg.code_; }
436 // Unfortunately we can't make this private in a struct.
441 const CRegister no_creg = { -1 };
443 const CRegister cr0 = { 0 };
444 const CRegister cr1 = { 1 };
445 const CRegister cr2 = { 2 };
446 const CRegister cr3 = { 3 };
447 const CRegister cr4 = { 4 };
448 const CRegister cr5 = { 5 };
449 const CRegister cr6 = { 6 };
450 const CRegister cr7 = { 7 };
451 const CRegister cr8 = { 8 };
452 const CRegister cr9 = { 9 };
453 const CRegister cr10 = { 10 };
454 const CRegister cr11 = { 11 };
455 const CRegister cr12 = { 12 };
456 const CRegister cr13 = { 13 };
457 const CRegister cr14 = { 14 };
458 const CRegister cr15 = { 15 };
461 // Coprocessor number
482 // -----------------------------------------------------------------------------
483 // Machine instruction Operands
485 // Class Operand represents a shifter operand in data processing instructions
486 class Operand BASE_EMBEDDED {
489 INLINE(explicit Operand(int32_t immediate,
490 RelocInfo::Mode rmode = RelocInfo::NONE32));
491 INLINE(static Operand Zero()) {
492 return Operand(static_cast<int32_t>(0));
494 INLINE(explicit Operand(const ExternalReference& f));
495 explicit Operand(Handle<Object> handle);
496 INLINE(explicit Operand(Smi* value));
499 INLINE(explicit Operand(Register rm));
501 // rm <shift_op> shift_imm
502 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
503 INLINE(static Operand SmiUntag(Register rm)) {
504 return Operand(rm, ASR, kSmiTagSize);
506 INLINE(static Operand PointerOffsetFromSmiKey(Register key)) {
507 STATIC_ASSERT(kSmiTag == 0 && kSmiTagSize < kPointerSizeLog2);
508 return Operand(key, LSL, kPointerSizeLog2 - kSmiTagSize);
510 INLINE(static Operand DoubleOffsetFromSmiKey(Register key)) {
511 STATIC_ASSERT(kSmiTag == 0 && kSmiTagSize < kDoubleSizeLog2);
512 return Operand(key, LSL, kDoubleSizeLog2 - kSmiTagSize);
516 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
518 // Return true if this is a register operand.
519 INLINE(bool is_reg() const);
521 // Return the number of actual instructions required to implement the given
522 // instruction for this particular operand. This can be a single instruction,
523 // if no load into the ip register is necessary, or anything between 2 and 4
524 // instructions when we need to load from the constant pool (depending upon
525 // whether the constant pool entry is in the small or extended section). If
526 // the instruction this operand is used for is a MOV or MVN instruction the
527 // actual instruction to use is required for this calculation. For other
528 // instructions instr is ignored.
530 // The value returned is only valid as long as no entries are added to the
531 // constant pool between this call and the actual instruction being emitted.
532 int instructions_required(const Assembler* assembler, Instr instr = 0) const;
533 bool must_output_reloc_info(const Assembler* assembler) const;
535 inline int32_t immediate() const {
536 DCHECK(!rm_.is_valid());
540 Register rm() const { return rm_; }
541 Register rs() const { return rs_; }
542 ShiftOp shift_op() const { return shift_op_; }
548 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
549 int32_t imm32_; // valid if rm_ == no_reg
550 RelocInfo::Mode rmode_;
552 friend class Assembler;
556 // Class MemOperand represents a memory operand in load and store instructions
557 class MemOperand BASE_EMBEDDED {
559 // [rn +/- offset] Offset/NegOffset
560 // [rn +/- offset]! PreIndex/NegPreIndex
561 // [rn], +/- offset PostIndex/NegPostIndex
562 // offset is any signed 32-bit value; offset is first loaded to register ip if
563 // it does not fit the addressing mode (12-bit unsigned and sign bit)
564 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
566 // [rn +/- rm] Offset/NegOffset
567 // [rn +/- rm]! PreIndex/NegPreIndex
568 // [rn], +/- rm PostIndex/NegPostIndex
569 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
571 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
572 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
573 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
574 explicit MemOperand(Register rn, Register rm,
575 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
576 INLINE(static MemOperand PointerAddressFromSmiKey(Register array,
578 AddrMode am = Offset)) {
579 STATIC_ASSERT(kSmiTag == 0 && kSmiTagSize < kPointerSizeLog2);
580 return MemOperand(array, key, LSL, kPointerSizeLog2 - kSmiTagSize, am);
583 void set_offset(int32_t offset) {
584 DCHECK(rm_.is(no_reg));
588 uint32_t offset() const {
589 DCHECK(rm_.is(no_reg));
593 Register rn() const { return rn_; }
594 Register rm() const { return rm_; }
595 AddrMode am() const { return am_; }
597 bool OffsetIsUint12Encodable() const {
598 return offset_ >= 0 ? is_uint12(offset_) : is_uint12(-offset_);
602 Register rn_; // base
603 Register rm_; // register offset
604 int32_t offset_; // valid if rm_ == no_reg
606 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
607 AddrMode am_; // bits P, U, and W
609 friend class Assembler;
613 // Class NeonMemOperand represents a memory operand in load and
614 // store NEON instructions
615 class NeonMemOperand BASE_EMBEDDED {
617 // [rn {:align}] Offset
618 // [rn {:align}]! PostIndex
619 explicit NeonMemOperand(Register rn, AddrMode am = Offset, int align = 0);
621 // [rn {:align}], rm PostIndex
622 explicit NeonMemOperand(Register rn, Register rm, int align = 0);
624 Register rn() const { return rn_; }
625 Register rm() const { return rm_; }
626 int align() const { return align_; }
629 void SetAlignment(int align);
631 Register rn_; // base
632 Register rm_; // register increment
637 // Class NeonListOperand represents a list of NEON registers
638 class NeonListOperand BASE_EMBEDDED {
640 explicit NeonListOperand(DoubleRegister base, int registers_count = 1);
641 DoubleRegister base() const { return base_; }
642 NeonListType type() const { return type_; }
644 DoubleRegister base_;
649 // Class used to build a constant pool.
650 class ConstantPoolBuilder BASE_EMBEDDED {
652 ConstantPoolBuilder();
653 ConstantPoolArray::LayoutSection AddEntry(Assembler* assm,
654 const RelocInfo& rinfo);
655 void Relocate(int pc_delta);
657 Handle<ConstantPoolArray> New(Isolate* isolate);
658 void Populate(Assembler* assm, ConstantPoolArray* constant_pool);
660 inline ConstantPoolArray::LayoutSection current_section() const {
661 return current_section_;
664 inline ConstantPoolArray::NumberOfEntries* number_of_entries(
665 ConstantPoolArray::LayoutSection section) {
666 return &number_of_entries_[section];
669 inline ConstantPoolArray::NumberOfEntries* small_entries() {
670 return number_of_entries(ConstantPoolArray::SMALL_SECTION);
673 inline ConstantPoolArray::NumberOfEntries* extended_entries() {
674 return number_of_entries(ConstantPoolArray::EXTENDED_SECTION);
678 struct ConstantPoolEntry {
679 ConstantPoolEntry(RelocInfo rinfo, ConstantPoolArray::LayoutSection section,
681 : rinfo_(rinfo), section_(section), merged_index_(merged_index) {}
684 ConstantPoolArray::LayoutSection section_;
688 ConstantPoolArray::Type GetConstantPoolType(RelocInfo::Mode rmode);
690 std::vector<ConstantPoolEntry> entries_;
691 ConstantPoolArray::LayoutSection current_section_;
692 ConstantPoolArray::NumberOfEntries number_of_entries_[2];
698 const VmovIndex VmovIndexLo = { 0 };
699 const VmovIndex VmovIndexHi = { 1 };
701 class Assembler : public AssemblerBase {
703 // Create an assembler. Instructions and relocation information are emitted
704 // into a buffer, with the instructions starting from the beginning and the
705 // relocation information starting from the end of the buffer. See CodeDesc
706 // for a detailed comment on the layout (globals.h).
708 // If the provided buffer is NULL, the assembler allocates and grows its own
709 // buffer, and buffer_size determines the initial buffer size. The buffer is
710 // owned by the assembler and deallocated upon destruction of the assembler.
712 // If the provided buffer is not NULL, the assembler uses the provided buffer
713 // for code generation and assumes its size to be buffer_size. If the buffer
714 // is too small, a fatal error occurs. No deallocation of the buffer is done
715 // upon destruction of the assembler.
716 Assembler(Isolate* isolate, void* buffer, int buffer_size);
717 virtual ~Assembler();
719 // GetCode emits any pending (non-emitted) code and fills the descriptor
720 // desc. GetCode() is idempotent; it returns the same result if no other
721 // Assembler functions are invoked in between GetCode() calls.
722 void GetCode(CodeDesc* desc);
724 // Label operations & relative jumps (PPUM Appendix D)
726 // Takes a branch opcode (cc) and a label (L) and generates
727 // either a backward branch or a forward branch and links it
728 // to the label fixup chain. Usage:
730 // Label L; // unbound label
731 // j(cc, &L); // forward branch to unbound label
732 // bind(&L); // bind label to the current pc
733 // j(cc, &L); // backward branch to bound label
734 // bind(&L); // illegal: a label may be bound only once
736 // Note: The same Label can be used for forward and backward branches
737 // but it may be bound only once.
739 void bind(Label* L); // binds an unbound label L to the current code position
741 // Returns the branch offset to the given label from the current code position
742 // Links the label to the current position if it is still unbound
743 // Manages the jump elimination optimization if the second parameter is true.
744 int branch_offset(Label* L, bool jump_elimination_allowed);
746 // Returns true if the given pc address is the start of a constant pool load
747 // instruction sequence.
748 INLINE(static bool is_constant_pool_load(Address pc));
750 // Return the address in the constant pool of the code target address used by
751 // the branch/call instruction at pc, or the object in a mov.
752 INLINE(static Address constant_pool_entry_address(
753 Address pc, ConstantPoolArray* constant_pool));
755 // Read/Modify the code target address in the branch/call instruction at pc.
756 INLINE(static Address target_address_at(Address pc,
757 ConstantPoolArray* constant_pool));
758 INLINE(static void set_target_address_at(Address pc,
759 ConstantPoolArray* constant_pool,
761 ICacheFlushMode icache_flush_mode =
762 FLUSH_ICACHE_IF_NEEDED));
763 INLINE(static Address target_address_at(Address pc, Code* code)) {
764 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
765 return target_address_at(pc, constant_pool);
767 INLINE(static void set_target_address_at(Address pc,
770 ICacheFlushMode icache_flush_mode =
771 FLUSH_ICACHE_IF_NEEDED)) {
772 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
773 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
776 // Return the code target address at a call site from the return address
777 // of that call in the instruction stream.
778 INLINE(static Address target_address_from_return_address(Address pc));
780 // Given the address of the beginning of a call, return the address
781 // in the instruction stream that the call will return from.
782 INLINE(static Address return_address_from_call_start(Address pc));
784 // Return the code target address of the patch debug break slot
785 INLINE(static Address break_address_from_return_address(Address pc));
787 // This sets the branch destination (which is in the constant pool on ARM).
788 // This is for calls and branches within generated code.
789 inline static void deserialization_set_special_target_at(
790 Address constant_pool_entry, Code* code, Address target);
792 // Here we are patching the address in the constant pool, not the actual call
793 // instruction. The address in the constant pool is the same size as a
795 static const int kSpecialTargetSize = kPointerSize;
797 // Size of an instruction.
798 static const int kInstrSize = sizeof(Instr);
800 // Distance between start of patched return sequence and the emitted address
802 // Patched return sequence is:
803 // ldr ip, [pc, #0] @ emited address and start
805 static const int kPatchReturnSequenceAddressOffset = 0 * kInstrSize;
807 // Distance between start of patched debug break slot and the emitted address
809 // Patched debug break slot code is:
810 // ldr ip, [pc, #0] @ emited address and start
812 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
814 static const int kPatchDebugBreakSlotReturnOffset = 2 * kInstrSize;
816 // Difference between address of current opcode and value read from pc
818 static const int kPcLoadDelta = 8;
820 static const int kJSReturnSequenceInstructions = 4;
821 static const int kDebugBreakSlotInstructions = 3;
822 static const int kDebugBreakSlotLength =
823 kDebugBreakSlotInstructions * kInstrSize;
825 // ---------------------------------------------------------------------------
828 // Insert the smallest number of nop instructions
829 // possible to align the pc offset to a multiple
830 // of m. m must be a power of 2 (>= 4).
832 // Aligns code to something that's optimal for a jump target for the platform.
833 void CodeTargetAlign();
835 // Branch instructions
836 void b(int branch_offset, Condition cond = al);
837 void bl(int branch_offset, Condition cond = al);
838 void blx(int branch_offset); // v5 and above
839 void blx(Register target, Condition cond = al); // v5 and above
840 void bx(Register target, Condition cond = al); // v5 and above, plus v4t
842 // Convenience branch instructions using labels
843 void b(Label* L, Condition cond = al) {
844 b(branch_offset(L, cond == al), cond);
846 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); }
847 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); }
848 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); }
849 void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above
851 // Data-processing instructions
853 void and_(Register dst, Register src1, const Operand& src2,
854 SBit s = LeaveCC, Condition cond = al);
856 void eor(Register dst, Register src1, const Operand& src2,
857 SBit s = LeaveCC, Condition cond = al);
859 void sub(Register dst, Register src1, const Operand& src2,
860 SBit s = LeaveCC, Condition cond = al);
861 void sub(Register dst, Register src1, Register src2,
862 SBit s = LeaveCC, Condition cond = al) {
863 sub(dst, src1, Operand(src2), s, cond);
866 void rsb(Register dst, Register src1, const Operand& src2,
867 SBit s = LeaveCC, Condition cond = al);
869 void add(Register dst, Register src1, const Operand& src2,
870 SBit s = LeaveCC, Condition cond = al);
871 void add(Register dst, Register src1, Register src2,
872 SBit s = LeaveCC, Condition cond = al) {
873 add(dst, src1, Operand(src2), s, cond);
876 void adc(Register dst, Register src1, const Operand& src2,
877 SBit s = LeaveCC, Condition cond = al);
879 void sbc(Register dst, Register src1, const Operand& src2,
880 SBit s = LeaveCC, Condition cond = al);
882 void rsc(Register dst, Register src1, const Operand& src2,
883 SBit s = LeaveCC, Condition cond = al);
885 void tst(Register src1, const Operand& src2, Condition cond = al);
886 void tst(Register src1, Register src2, Condition cond = al) {
887 tst(src1, Operand(src2), cond);
890 void teq(Register src1, const Operand& src2, Condition cond = al);
892 void cmp(Register src1, const Operand& src2, Condition cond = al);
893 void cmp(Register src1, Register src2, Condition cond = al) {
894 cmp(src1, Operand(src2), cond);
896 void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);
898 void cmn(Register src1, const Operand& src2, Condition cond = al);
900 void orr(Register dst, Register src1, const Operand& src2,
901 SBit s = LeaveCC, Condition cond = al);
902 void orr(Register dst, Register src1, Register src2,
903 SBit s = LeaveCC, Condition cond = al) {
904 orr(dst, src1, Operand(src2), s, cond);
907 void mov(Register dst, const Operand& src,
908 SBit s = LeaveCC, Condition cond = al);
909 void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
910 mov(dst, Operand(src), s, cond);
913 // Load the position of the label relative to the generated code object
914 // pointer in a register.
915 void mov_label_offset(Register dst, Label* label);
917 // ARMv7 instructions for loading a 32 bit immediate in two instructions.
918 // The constant for movw and movt should be in the range 0-0xffff.
919 void movw(Register reg, uint32_t immediate, Condition cond = al);
920 void movt(Register reg, uint32_t immediate, Condition cond = al);
922 void bic(Register dst, Register src1, const Operand& src2,
923 SBit s = LeaveCC, Condition cond = al);
925 void mvn(Register dst, const Operand& src,
926 SBit s = LeaveCC, Condition cond = al);
928 // Shift instructions
930 void asr(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
931 Condition cond = al) {
933 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
935 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
939 void lsl(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
940 Condition cond = al) {
942 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
944 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
948 void lsr(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
949 Condition cond = al) {
951 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
953 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
957 // Multiply instructions
959 void mla(Register dst, Register src1, Register src2, Register srcA,
960 SBit s = LeaveCC, Condition cond = al);
962 void mls(Register dst, Register src1, Register src2, Register srcA,
963 Condition cond = al);
965 void sdiv(Register dst, Register src1, Register src2,
966 Condition cond = al);
968 void udiv(Register dst, Register src1, Register src2, Condition cond = al);
970 void mul(Register dst, Register src1, Register src2,
971 SBit s = LeaveCC, Condition cond = al);
973 void smlal(Register dstL, Register dstH, Register src1, Register src2,
974 SBit s = LeaveCC, Condition cond = al);
976 void smull(Register dstL, Register dstH, Register src1, Register src2,
977 SBit s = LeaveCC, Condition cond = al);
979 void umlal(Register dstL, Register dstH, Register src1, Register src2,
980 SBit s = LeaveCC, Condition cond = al);
982 void umull(Register dstL, Register dstH, Register src1, Register src2,
983 SBit s = LeaveCC, Condition cond = al);
985 // Miscellaneous arithmetic instructions
987 void clz(Register dst, Register src, Condition cond = al); // v5 and above
989 // Saturating instructions. v6 and above.
991 // Unsigned saturate.
993 // Saturate an optionally shifted signed value to an unsigned range.
995 // usat dst, #satpos, src
996 // usat dst, #satpos, src, lsl #sh
997 // usat dst, #satpos, src, asr #sh
999 // Register dst will contain:
1002 // (1 << satpos) - 1, if s > ((1 << satpos) - 1)
1005 // where s is the contents of src after shifting (if used.)
1006 void usat(Register dst, int satpos, const Operand& src, Condition cond = al);
1008 // Bitfield manipulation instructions. v7 and above.
1010 void ubfx(Register dst, Register src, int lsb, int width,
1011 Condition cond = al);
1013 void sbfx(Register dst, Register src, int lsb, int width,
1014 Condition cond = al);
1016 void bfc(Register dst, int lsb, int width, Condition cond = al);
1018 void bfi(Register dst, Register src, int lsb, int width,
1019 Condition cond = al);
1021 void pkhbt(Register dst, Register src1, const Operand& src2,
1022 Condition cond = al);
1024 void pkhtb(Register dst, Register src1, const Operand& src2,
1025 Condition cond = al);
1027 void uxtb(Register dst, const Operand& src, Condition cond = al);
1029 void uxtab(Register dst, Register src1, const Operand& src2,
1030 Condition cond = al);
1032 void uxtb16(Register dst, const Operand& src, Condition cond = al);
1034 // Status register access instructions
1036 void mrs(Register dst, SRegister s, Condition cond = al);
1037 void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al);
1039 // Load/Store instructions
1040 void ldr(Register dst, const MemOperand& src, Condition cond = al);
1041 void str(Register src, const MemOperand& dst, Condition cond = al);
1042 void ldrb(Register dst, const MemOperand& src, Condition cond = al);
1043 void strb(Register src, const MemOperand& dst, Condition cond = al);
1044 void ldrh(Register dst, const MemOperand& src, Condition cond = al);
1045 void strh(Register src, const MemOperand& dst, Condition cond = al);
1046 void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
1047 void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
1048 void ldrd(Register dst1,
1050 const MemOperand& src, Condition cond = al);
1051 void strd(Register src1,
1053 const MemOperand& dst, Condition cond = al);
1055 // Preload instructions
1056 void pld(const MemOperand& address);
1058 // Load/Store multiple instructions
1059 void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
1060 void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
1062 // Exception-generating instructions and debugging support
1063 void stop(const char* msg,
1064 Condition cond = al,
1065 int32_t code = kDefaultStopCode);
1067 void bkpt(uint32_t imm16); // v5 and above
1068 void svc(uint32_t imm24, Condition cond = al);
1070 // Coprocessor instructions
1072 void cdp(Coprocessor coproc, int opcode_1,
1073 CRegister crd, CRegister crn, CRegister crm,
1074 int opcode_2, Condition cond = al);
1076 void cdp2(Coprocessor coproc, int opcode_1,
1077 CRegister crd, CRegister crn, CRegister crm,
1078 int opcode_2); // v5 and above
1080 void mcr(Coprocessor coproc, int opcode_1,
1081 Register rd, CRegister crn, CRegister crm,
1082 int opcode_2 = 0, Condition cond = al);
1084 void mcr2(Coprocessor coproc, int opcode_1,
1085 Register rd, CRegister crn, CRegister crm,
1086 int opcode_2 = 0); // v5 and above
1088 void mrc(Coprocessor coproc, int opcode_1,
1089 Register rd, CRegister crn, CRegister crm,
1090 int opcode_2 = 0, Condition cond = al);
1092 void mrc2(Coprocessor coproc, int opcode_1,
1093 Register rd, CRegister crn, CRegister crm,
1094 int opcode_2 = 0); // v5 and above
1096 void ldc(Coprocessor coproc, CRegister crd, const MemOperand& src,
1097 LFlag l = Short, Condition cond = al);
1098 void ldc(Coprocessor coproc, CRegister crd, Register base, int option,
1099 LFlag l = Short, Condition cond = al);
1101 void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src,
1102 LFlag l = Short); // v5 and above
1103 void ldc2(Coprocessor coproc, CRegister crd, Register base, int option,
1104 LFlag l = Short); // v5 and above
1107 // All these APIs support S0 to S31 and D0 to D31.
1109 void vldr(const DwVfpRegister dst,
1110 const Register base,
1112 const Condition cond = al);
1113 void vldr(const DwVfpRegister dst,
1114 const MemOperand& src,
1115 const Condition cond = al);
1117 void vldr(const SwVfpRegister dst,
1118 const Register base,
1120 const Condition cond = al);
1121 void vldr(const SwVfpRegister dst,
1122 const MemOperand& src,
1123 const Condition cond = al);
1125 void vstr(const DwVfpRegister src,
1126 const Register base,
1128 const Condition cond = al);
1129 void vstr(const DwVfpRegister src,
1130 const MemOperand& dst,
1131 const Condition cond = al);
1133 void vstr(const SwVfpRegister src,
1134 const Register base,
1136 const Condition cond = al);
1137 void vstr(const SwVfpRegister src,
1138 const MemOperand& dst,
1139 const Condition cond = al);
1141 void vldm(BlockAddrMode am,
1143 DwVfpRegister first,
1145 Condition cond = al);
1147 void vstm(BlockAddrMode am,
1149 DwVfpRegister first,
1151 Condition cond = al);
1153 void vldm(BlockAddrMode am,
1155 SwVfpRegister first,
1157 Condition cond = al);
1159 void vstm(BlockAddrMode am,
1161 SwVfpRegister first,
1163 Condition cond = al);
1165 void vmov(const DwVfpRegister dst,
1167 const Register scratch = no_reg);
1168 void vmov(const SwVfpRegister dst,
1169 const SwVfpRegister src,
1170 const Condition cond = al);
1171 void vmov(const DwVfpRegister dst,
1172 const DwVfpRegister src,
1173 const Condition cond = al);
1174 void vmov(const DwVfpRegister dst,
1175 const VmovIndex index,
1177 const Condition cond = al);
1178 void vmov(const Register dst,
1179 const VmovIndex index,
1180 const DwVfpRegister src,
1181 const Condition cond = al);
1182 void vmov(const DwVfpRegister dst,
1183 const Register src1,
1184 const Register src2,
1185 const Condition cond = al);
1186 void vmov(const Register dst1,
1187 const Register dst2,
1188 const DwVfpRegister src,
1189 const Condition cond = al);
1190 void vmov(const SwVfpRegister dst,
1192 const Condition cond = al);
1193 void vmov(const Register dst,
1194 const SwVfpRegister src,
1195 const Condition cond = al);
1196 void vcvt_f64_s32(const DwVfpRegister dst,
1197 const SwVfpRegister src,
1198 VFPConversionMode mode = kDefaultRoundToZero,
1199 const Condition cond = al);
1200 void vcvt_f32_s32(const SwVfpRegister dst,
1201 const SwVfpRegister src,
1202 VFPConversionMode mode = kDefaultRoundToZero,
1203 const Condition cond = al);
1204 void vcvt_f64_u32(const DwVfpRegister dst,
1205 const SwVfpRegister src,
1206 VFPConversionMode mode = kDefaultRoundToZero,
1207 const Condition cond = al);
1208 void vcvt_s32_f64(const SwVfpRegister dst,
1209 const DwVfpRegister src,
1210 VFPConversionMode mode = kDefaultRoundToZero,
1211 const Condition cond = al);
1212 void vcvt_u32_f64(const SwVfpRegister dst,
1213 const DwVfpRegister src,
1214 VFPConversionMode mode = kDefaultRoundToZero,
1215 const Condition cond = al);
1216 void vcvt_f64_f32(const DwVfpRegister dst,
1217 const SwVfpRegister src,
1218 VFPConversionMode mode = kDefaultRoundToZero,
1219 const Condition cond = al);
1220 void vcvt_f32_f64(const SwVfpRegister dst,
1221 const DwVfpRegister src,
1222 VFPConversionMode mode = kDefaultRoundToZero,
1223 const Condition cond = al);
1224 void vcvt_f64_s32(const DwVfpRegister dst,
1226 const Condition cond = al);
1228 void vneg(const DwVfpRegister dst,
1229 const DwVfpRegister src,
1230 const Condition cond = al);
1231 void vabs(const DwVfpRegister dst,
1232 const DwVfpRegister src,
1233 const Condition cond = al);
1234 void vadd(const DwVfpRegister dst,
1235 const DwVfpRegister src1,
1236 const DwVfpRegister src2,
1237 const Condition cond = al);
1238 void vsub(const DwVfpRegister dst,
1239 const DwVfpRegister src1,
1240 const DwVfpRegister src2,
1241 const Condition cond = al);
1242 void vmul(const DwVfpRegister dst,
1243 const DwVfpRegister src1,
1244 const DwVfpRegister src2,
1245 const Condition cond = al);
1246 void vmla(const DwVfpRegister dst,
1247 const DwVfpRegister src1,
1248 const DwVfpRegister src2,
1249 const Condition cond = al);
1250 void vmls(const DwVfpRegister dst,
1251 const DwVfpRegister src1,
1252 const DwVfpRegister src2,
1253 const Condition cond = al);
1254 void vdiv(const DwVfpRegister dst,
1255 const DwVfpRegister src1,
1256 const DwVfpRegister src2,
1257 const Condition cond = al);
1258 void vcmp(const DwVfpRegister src1,
1259 const DwVfpRegister src2,
1260 const Condition cond = al);
1261 void vcmp(const DwVfpRegister src1,
1263 const Condition cond = al);
1264 void vmrs(const Register dst,
1265 const Condition cond = al);
1266 void vmsr(const Register dst,
1267 const Condition cond = al);
1268 void vsqrt(const DwVfpRegister dst,
1269 const DwVfpRegister src,
1270 const Condition cond = al);
1272 // Support for NEON.
1273 // All these APIs support D0 to D31 and Q0 to Q15.
1275 void vld1(NeonSize size,
1276 const NeonListOperand& dst,
1277 const NeonMemOperand& src);
1278 void vst1(NeonSize size,
1279 const NeonListOperand& src,
1280 const NeonMemOperand& dst);
1281 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src);
1283 // Pseudo instructions
1285 // Different nop operations are used by the code generator to detect certain
1286 // states of the generated code.
1287 enum NopMarkerTypes {
1288 NON_MARKING_NOP = 0,
1291 PROPERTY_ACCESS_INLINED,
1292 PROPERTY_ACCESS_INLINED_CONTEXT,
1293 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
1296 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED
1299 void nop(int type = 0); // 0 is the default non-marking type.
1301 void push(Register src, Condition cond = al) {
1302 str(src, MemOperand(sp, 4, NegPreIndex), cond);
1305 void pop(Register dst, Condition cond = al) {
1306 ldr(dst, MemOperand(sp, 4, PostIndex), cond);
1310 add(sp, sp, Operand(kPointerSize));
1313 // Jump unconditionally to given label.
1314 void jmp(Label* L) { b(L, al); }
1316 // Check the code size generated from label to here.
1317 int SizeOfCodeGeneratedSince(Label* label) {
1318 return pc_offset() - label->pos();
1321 // Check the number of instructions generated from label to here.
1322 int InstructionsGeneratedSince(Label* label) {
1323 return SizeOfCodeGeneratedSince(label) / kInstrSize;
1326 // Check whether an immediate fits an addressing mode 1 instruction.
1327 static bool ImmediateFitsAddrMode1Instruction(int32_t imm32);
1329 // Check whether an immediate fits an addressing mode 2 instruction.
1330 bool ImmediateFitsAddrMode2Instruction(int32_t imm32);
1332 // Class for scoping postponing the constant pool generation.
1333 class BlockConstPoolScope {
1335 explicit BlockConstPoolScope(Assembler* assem) : assem_(assem) {
1336 assem_->StartBlockConstPool();
1338 ~BlockConstPoolScope() {
1339 assem_->EndBlockConstPool();
1345 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope);
1350 // Mark address of the ExitJSFrame code.
1351 void RecordJSReturn();
1353 // Mark address of a debug break slot.
1354 void RecordDebugBreakSlot();
1356 // Record the AST id of the CallIC being compiled, so that it can be placed
1357 // in the relocation information.
1358 void SetRecordedAstId(TypeFeedbackId ast_id) {
1359 DCHECK(recorded_ast_id_.IsNone());
1360 recorded_ast_id_ = ast_id;
1363 TypeFeedbackId RecordedAstId() {
1364 DCHECK(!recorded_ast_id_.IsNone());
1365 return recorded_ast_id_;
1368 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
1370 // Record a comment relocation entry that can be used by a disassembler.
1371 // Use --code-comments to enable.
1372 void RecordComment(const char* msg);
1374 // Record the emission of a constant pool.
1376 // The emission of constant pool depends on the size of the code generated and
1377 // the number of RelocInfo recorded.
1378 // The Debug mechanism needs to map code offsets between two versions of a
1379 // function, compiled with and without debugger support (see for example
1380 // Debug::PrepareForBreakPoints()).
1381 // Compiling functions with debugger support generates additional code
1382 // (DebugCodegen::GenerateSlot()). This may affect the emission of the
1383 // constant pools and cause the version of the code with debugger support to
1384 // have constant pools generated in different places.
1385 // Recording the position and size of emitted constant pools allows to
1386 // correctly compute the offset mappings between the different versions of a
1387 // function in all situations.
1389 // The parameter indicates the size of the constant pool (in bytes), including
1390 // the marker and branch over the data.
1391 void RecordConstPool(int size);
1393 // Writes a single byte or word of data in the code stream. Used
1394 // for inline tables, e.g., jump-tables. The constant pool should be
1395 // emitted before any use of db and dd to ensure that constant pools
1396 // are not emitted as part of the tables generated.
1397 void db(uint8_t data);
1398 void dd(uint32_t data);
1400 // Emits the address of the code stub's first instruction.
1401 void emit_code_stub_address(Code* stub);
1403 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1405 // Read/patch instructions
1406 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
1407 void instr_at_put(int pos, Instr instr) {
1408 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
1410 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
1411 static void instr_at_put(byte* pc, Instr instr) {
1412 *reinterpret_cast<Instr*>(pc) = instr;
1414 static Condition GetCondition(Instr instr);
1415 static bool IsBranch(Instr instr);
1416 static int GetBranchOffset(Instr instr);
1417 static bool IsLdrRegisterImmediate(Instr instr);
1418 static bool IsVldrDRegisterImmediate(Instr instr);
1419 static Instr GetConsantPoolLoadPattern();
1420 static Instr GetConsantPoolLoadMask();
1421 static bool IsLdrPpRegOffset(Instr instr);
1422 static Instr GetLdrPpRegOffsetPattern();
1423 static bool IsLdrPpImmediateOffset(Instr instr);
1424 static bool IsVldrDPpImmediateOffset(Instr instr);
1425 static int GetLdrRegisterImmediateOffset(Instr instr);
1426 static int GetVldrDRegisterImmediateOffset(Instr instr);
1427 static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset);
1428 static Instr SetVldrDRegisterImmediateOffset(Instr instr, int offset);
1429 static bool IsStrRegisterImmediate(Instr instr);
1430 static Instr SetStrRegisterImmediateOffset(Instr instr, int offset);
1431 static bool IsAddRegisterImmediate(Instr instr);
1432 static Instr SetAddRegisterImmediateOffset(Instr instr, int offset);
1433 static Register GetRd(Instr instr);
1434 static Register GetRn(Instr instr);
1435 static Register GetRm(Instr instr);
1436 static bool IsPush(Instr instr);
1437 static bool IsPop(Instr instr);
1438 static bool IsStrRegFpOffset(Instr instr);
1439 static bool IsLdrRegFpOffset(Instr instr);
1440 static bool IsStrRegFpNegOffset(Instr instr);
1441 static bool IsLdrRegFpNegOffset(Instr instr);
1442 static bool IsLdrPcImmediateOffset(Instr instr);
1443 static bool IsVldrDPcImmediateOffset(Instr instr);
1444 static bool IsBlxReg(Instr instr);
1445 static bool IsBlxIp(Instr instr);
1446 static bool IsTstImmediate(Instr instr);
1447 static bool IsCmpRegister(Instr instr);
1448 static bool IsCmpImmediate(Instr instr);
1449 static Register GetCmpImmediateRegister(Instr instr);
1450 static int GetCmpImmediateRawImmediate(Instr instr);
1451 static bool IsNop(Instr instr, int type = NON_MARKING_NOP);
1452 static bool IsMovT(Instr instr);
1453 static Instr GetMovTPattern();
1454 static bool IsMovW(Instr instr);
1455 static Instr GetMovWPattern();
1456 static Instr EncodeMovwImmediate(uint32_t immediate);
1457 static Instr PatchMovwImmediate(Instr instruction, uint32_t immediate);
1459 // Constants in pools are accessed via pc relative addressing, which can
1460 // reach +/-4KB for integer PC-relative loads and +/-1KB for floating-point
1461 // PC-relative loads, thereby defining a maximum distance between the
1462 // instruction and the accessed constant.
1463 static const int kMaxDistToIntPool = 4*KB;
1464 static const int kMaxDistToFPPool = 1*KB;
1465 // All relocations could be integer, it therefore acts as the limit.
1466 static const int kMaxNumPending32RelocInfo = kMaxDistToIntPool/kInstrSize;
1467 static const int kMaxNumPending64RelocInfo = kMaxDistToFPPool/kInstrSize;
1469 // Postpone the generation of the constant pool for the specified number of
1471 void BlockConstPoolFor(int instructions);
1473 // Check if is time to emit a constant pool.
1474 void CheckConstPool(bool force_emit, bool require_jump);
1476 // Allocate a constant pool of the correct size for the generated code.
1477 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1479 // Generate the constant pool for the generated code.
1480 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1482 bool is_constant_pool_available() const { return constant_pool_available_; }
1484 bool use_extended_constant_pool() const {
1485 return constant_pool_builder_.current_section() ==
1486 ConstantPoolArray::EXTENDED_SECTION;
1491 // Relocation for a type-recording IC has the AST id added to it. This
1492 // member variable is a way to pass the information from the call site to
1493 // the relocation info.
1494 TypeFeedbackId recorded_ast_id_;
1496 int buffer_space() const { return reloc_info_writer.pos() - pc_; }
1498 // Decode branch instruction at pos and return branch target pos
1499 int target_at(int pos);
1501 // Patch branch instruction at pos to branch to given branch target pos
1502 void target_at_put(int pos, int target_pos);
1504 // Prevent contant pool emission until EndBlockConstPool is called.
1505 // Call to this function can be nested but must be followed by an equal
1506 // number of call to EndBlockConstpool.
1507 void StartBlockConstPool() {
1508 if (const_pool_blocked_nesting_++ == 0) {
1509 // Prevent constant pool checks happening by setting the next check to
1510 // the biggest possible offset.
1511 next_buffer_check_ = kMaxInt;
1515 // Resume constant pool emission. Need to be called as many time as
1516 // StartBlockConstPool to have an effect.
1517 void EndBlockConstPool() {
1518 if (--const_pool_blocked_nesting_ == 0) {
1520 // Max pool start (if we need a jump and an alignment).
1521 int start = pc_offset() + kInstrSize + 2 * kPointerSize;
1522 // Check the constant pool hasn't been blocked for too long.
1523 DCHECK((num_pending_32_bit_reloc_info_ == 0) ||
1524 (start + num_pending_64_bit_reloc_info_ * kDoubleSize <
1525 (first_const_pool_32_use_ + kMaxDistToIntPool)));
1526 DCHECK((num_pending_64_bit_reloc_info_ == 0) ||
1527 (start < (first_const_pool_64_use_ + kMaxDistToFPPool)));
1530 // * no_const_pool_before_ >= next_buffer_check_ and the emission is
1532 // * no_const_pool_before_ < next_buffer_check_ and the next emit will
1534 next_buffer_check_ = no_const_pool_before_;
1538 bool is_const_pool_blocked() const {
1539 return (const_pool_blocked_nesting_ > 0) ||
1540 (pc_offset() < no_const_pool_before_);
1543 void set_constant_pool_available(bool available) {
1544 constant_pool_available_ = available;
1548 int next_buffer_check_; // pc offset of next buffer check
1551 // The relocation writer's position is at least kGap bytes below the end of
1552 // the generated instructions. This is so that multi-instruction sequences do
1553 // not have to check for overflow. The same is true for writes of large
1554 // relocation info entries.
1555 static const int kGap = 32;
1557 // Constant pool generation
1558 // Pools are emitted in the instruction stream, preferably after unconditional
1559 // jumps or after returns from functions (in dead code locations).
1560 // If a long code sequence does not contain unconditional jumps, it is
1561 // necessary to emit the constant pool before the pool gets too far from the
1562 // location it is accessed from. In this case, we emit a jump over the emitted
1564 // Constants in the pool may be addresses of functions that gets relocated;
1565 // if so, a relocation info entry is associated to the constant pool entry.
1567 // Repeated checking whether the constant pool should be emitted is rather
1568 // expensive. By default we only check again once a number of instructions
1569 // has been generated. That also means that the sizing of the buffers is not
1570 // an exact science, and that we rely on some slop to not overrun buffers.
1571 static const int kCheckPoolIntervalInst = 32;
1572 static const int kCheckPoolInterval = kCheckPoolIntervalInst * kInstrSize;
1575 // Emission of the constant pool may be blocked in some code sequences.
1576 int const_pool_blocked_nesting_; // Block emission if this is not zero.
1577 int no_const_pool_before_; // Block emission before this pc offset.
1579 // Keep track of the first instruction requiring a constant pool entry
1580 // since the previous constant pool was emitted.
1581 int first_const_pool_32_use_;
1582 int first_const_pool_64_use_;
1584 // Relocation info generation
1585 // Each relocation is encoded as a variable size value
1586 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1587 RelocInfoWriter reloc_info_writer;
1589 // Relocation info records are also used during code generation as temporary
1590 // containers for constants and code target addresses until they are emitted
1591 // to the constant pool. These pending relocation info records are temporarily
1592 // stored in a separate buffer until a constant pool is emitted.
1593 // If every instruction in a long sequence is accessing the pool, we need one
1594 // pending relocation entry per instruction.
1596 // The buffers of pending relocation info.
1597 RelocInfo pending_32_bit_reloc_info_[kMaxNumPending32RelocInfo];
1598 RelocInfo pending_64_bit_reloc_info_[kMaxNumPending64RelocInfo];
1599 // Number of pending reloc info entries in the 32 bits buffer.
1600 int num_pending_32_bit_reloc_info_;
1601 // Number of pending reloc info entries in the 64 bits buffer.
1602 int num_pending_64_bit_reloc_info_;
1604 ConstantPoolBuilder constant_pool_builder_;
1606 // The bound position, before this we cannot do instruction elimination.
1607 int last_bound_pos_;
1609 // Indicates whether the constant pool can be accessed, which is only possible
1610 // if the pp register points to the current code object's constant pool.
1611 bool constant_pool_available_;
1614 inline void CheckBuffer();
1616 inline void emit(Instr x);
1618 // 32-bit immediate values
1619 void move_32_bit_immediate(Register rd,
1621 Condition cond = al);
1623 // Instruction generation
1624 void addrmod1(Instr instr, Register rn, Register rd, const Operand& x);
1625 void addrmod2(Instr instr, Register rd, const MemOperand& x);
1626 void addrmod3(Instr instr, Register rd, const MemOperand& x);
1627 void addrmod4(Instr instr, Register rn, RegList rl);
1628 void addrmod5(Instr instr, CRegister crd, const MemOperand& x);
1631 void print(Label* L);
1632 void bind_to(Label* L, int pos);
1633 void next(Label* L);
1635 enum UseConstantPoolMode {
1637 DONT_USE_CONSTANT_POOL
1640 // Record reloc info for current pc_
1641 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1642 void RecordRelocInfo(const RelocInfo& rinfo);
1643 ConstantPoolArray::LayoutSection ConstantPoolAddEntry(const RelocInfo& rinfo);
1645 friend class RelocInfo;
1646 friend class CodePatcher;
1647 friend class BlockConstPoolScope;
1648 friend class FrameAndConstantPoolScope;
1649 friend class ConstantPoolUnavailableScope;
1651 PositionsRecorder positions_recorder_;
1652 friend class PositionsRecorder;
1653 friend class EnsureSpace;
1657 class EnsureSpace BASE_EMBEDDED {
1659 explicit EnsureSpace(Assembler* assembler) {
1660 assembler->CheckBuffer();
1665 } } // namespace v8::internal
1667 #endif // V8_ARM_ASSEMBLER_ARM_H_