2 # Copyright (c) 2012 The Native Client Authors. All rights reserved.
3 # Use of this source code is governed by a BSD-style license that can be
4 # found in the LICENSE file.
8 if env.Bit('bitcode') and not env.Bit('pnacl_generate_pexe'):
10 env.PNaClForceNative()
11 testsuites = ['small_tests', 'sel_ldr_tests', 'nonpexe_tests']
13 infoleak_sources = ['test_infoleak.c']
14 if env.Bit('target_arm') and not env.Bit('pnacl_generate_pexe'):
15 infoleak_sources.append('test_infoleak_arm.S')
16 elif env.Bit('target_mips32') and not env.Bit('pnacl_generate_pexe'):
17 infoleak_sources.append('test_infoleak_mips.S')
19 nexe = env.ComponentProgram('test_infoleak', infoleak_sources,
20 EXTRA_LIBS=['${NONIRT_LIBS}'])
22 node = env.CommandSelLdrTestNacl('test_infoleak.out', nexe)
23 env.AddNodeToTestSuite(node,
26 # Valgrind apparently doesn't implement
27 # stmxcsr/ldmxcsr correctly. stmxcsr seems to do
28 # nothing, and ldmxcsr always reads back the
29 # hardware's power-up default value of 0x1f80.
30 is_broken=env.IsRunningUnderValgrind())
32 if not env.Bit('pnacl_generate_pexe') and not env.Bit('target_mips32'):
33 fpu_cw_sources = ['test_fpu_control_word.c']
34 if env.Bit('target_arm'):
35 fpu_cw_sources.append('test_fpu_control_word_arm.S')
36 nexe = env.ComponentProgram('test_fpu_control_word', fpu_cw_sources,
37 EXTRA_LIBS=['${NONIRT_LIBS}'])
38 node = env.CommandSelLdrTestNacl('test_fpu_control_word.out', nexe)
39 env.AddNodeToTestSuite(node,
41 'run_fpu_control_word_test',
42 # Valgrind apparenty doesn't implement
43 # fnstcw;fldcw correctly.
44 is_broken=env.IsRunningUnderValgrind())