Merge branch 'timers/clockevents-next' of git://git.linaro.org/people/dlezcano/clocke...

* Support for memory mapped arch_timers
* Trivial fixes to the moxart timer code
* Documentation updates

Trivial conflicts in drivers/clocksource/arm_arch_timer.c. Fixed up
the newly added __cpuinit annotations as well.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --cc arch/arm/include/asm/arch_timer.h
Simple merge

diff --cc arch/arm64/include/asm/arch_timer.h
Simple merge

diff --cc drivers/clocksource/arm_arch_timer.c
index ffadd83,b3df46d..fbd9ccd
--- 1/drivers/clocksource/arm_arch_timer.c
--- 2/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@@ -43,14 -70,76 +70,77 @@@ static bool arch_timer_mem_use_virtual
   * Architected system timer support.
   */
  
- static inline irqreturn_t timer_handler(const int access,
+ static __always_inline
+ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 -              struct clock_event_device *clk)
++                        struct clock_event_device *clk)
+ {
+       if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
+               struct arch_timer *timer = to_arch_timer(clk);
+               switch (reg) {
+               case ARCH_TIMER_REG_CTRL:
+                       writel_relaxed(val, timer->base + CNTP_CTL);
+                       break;
+               case ARCH_TIMER_REG_TVAL:
+                       writel_relaxed(val, timer->base + CNTP_TVAL);
+                       break;
+               }
+       } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+               struct arch_timer *timer = to_arch_timer(clk);
+               switch (reg) {
+               case ARCH_TIMER_REG_CTRL:
+                       writel_relaxed(val, timer->base + CNTV_CTL);
+                       break;
+               case ARCH_TIMER_REG_TVAL:
+                       writel_relaxed(val, timer->base + CNTV_TVAL);
+                       break;
+               }
+       } else {
+               arch_timer_reg_write_cp15(access, reg, val);
+       }
+ }
+ 
+ static __always_inline
+ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 -              struct clock_event_device *clk)
++                      struct clock_event_device *clk)
+ {
+       u32 val;
+ 
+       if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
+               struct arch_timer *timer = to_arch_timer(clk);
+               switch (reg) {
+               case ARCH_TIMER_REG_CTRL:
+                       val = readl_relaxed(timer->base + CNTP_CTL);
+                       break;
+               case ARCH_TIMER_REG_TVAL:
+                       val = readl_relaxed(timer->base + CNTP_TVAL);
+                       break;
+               }
+       } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+               struct arch_timer *timer = to_arch_timer(clk);
+               switch (reg) {
+               case ARCH_TIMER_REG_CTRL:
+                       val = readl_relaxed(timer->base + CNTV_CTL);
+                       break;
+               case ARCH_TIMER_REG_TVAL:
+                       val = readl_relaxed(timer->base + CNTV_TVAL);
+                       break;
+               }
+       } else {
+               val = arch_timer_reg_read_cp15(access, reg);
+       }
+ 
+       return val;
+ }
+ 
+ static __always_inline irqreturn_t timer_handler(const int access,
                                        struct clock_event_device *evt)
  {
        unsigned long ctrl;
-       ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
++
+       ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
        if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
                ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-               arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+               arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
                evt->event_handler(evt);
                return IRQ_HANDLED;
        }
@@@ -96,17 -200,30 +201,30 @@@ static void arch_timer_set_mode_virt(en
  static void arch_timer_set_mode_phys(enum clock_event_mode mode,
                                     struct clock_event_device *clk)
  {
-       timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+       timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
+ }
+ 
+ static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
+                                        struct clock_event_device *clk)
+ {
+       timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
  }
  
- static inline void set_next_event(const int access, unsigned long evt)
+ static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
+                                        struct clock_event_device *clk)
+ {
+       timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
+ }
+ 
+ static __always_inline void set_next_event(const int access, unsigned long evt,
 -                                struct clock_event_device *clk)
++                                         struct clock_event_device *clk)
  {
        unsigned long ctrl;
-       ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+       ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
        ctrl |= ARCH_TIMER_CTRL_ENABLE;
        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
-       arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
-       arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+       arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
+       arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
  }
  
  static int arch_timer_set_next_event_virt(unsigned long evt,
@@@ -123,27 -240,62 +241,62 @@@ static int arch_timer_set_next_event_ph
        return 0;
  }
  
- static int arch_timer_setup(struct clock_event_device *clk)
+ static int arch_timer_set_next_event_virt_mem(unsigned long evt,
+                                             struct clock_event_device *clk)
  {
-       clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
-       clk->name = "arch_sys_timer";
-       clk->rating = 450;
-       if (arch_timer_use_virtual) {
-               clk->irq = arch_timer_ppi[VIRT_PPI];
-               clk->set_mode = arch_timer_set_mode_virt;
-               clk->set_next_event = arch_timer_set_next_event_virt;
+       set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
+       return 0;
+ }
+ 
+ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
+                                             struct clock_event_device *clk)
+ {
+       set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
+       return 0;
+ }
+ 
 -static void __cpuinit __arch_timer_setup(unsigned type,
 -                                     struct clock_event_device *clk)
++static void __arch_timer_setup(unsigned type,
++                             struct clock_event_device *clk)
+ {
+       clk->features = CLOCK_EVT_FEAT_ONESHOT;
+ 
+       if (type == ARCH_CP15_TIMER) {
+               clk->features |= CLOCK_EVT_FEAT_C3STOP;
+               clk->name = "arch_sys_timer";
+               clk->rating = 450;
+               clk->cpumask = cpumask_of(smp_processor_id());
+               if (arch_timer_use_virtual) {
+                       clk->irq = arch_timer_ppi[VIRT_PPI];
+                       clk->set_mode = arch_timer_set_mode_virt;
+                       clk->set_next_event = arch_timer_set_next_event_virt;
+               } else {
+                       clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
+                       clk->set_mode = arch_timer_set_mode_phys;
+                       clk->set_next_event = arch_timer_set_next_event_phys;
+               }
        } else {
-               clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
-               clk->set_mode = arch_timer_set_mode_phys;
-               clk->set_next_event = arch_timer_set_next_event_phys;
+               clk->name = "arch_mem_timer";
+               clk->rating = 400;
+               clk->cpumask = cpu_all_mask;
+               if (arch_timer_mem_use_virtual) {
+                       clk->set_mode = arch_timer_set_mode_virt_mem;
+                       clk->set_next_event =
+                               arch_timer_set_next_event_virt_mem;
+               } else {
+                       clk->set_mode = arch_timer_set_mode_phys_mem;
+                       clk->set_next_event =
+                               arch_timer_set_next_event_phys_mem;
+               }
        }
  
-       clk->cpumask = cpumask_of(smp_processor_id());
+       clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
  
-       clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
+       clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
+ }
  
-       clockevents_config_and_register(clk, arch_timer_rate,
-                                       0xf, 0x7fffffff);
 -static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
++static int arch_timer_setup(struct clock_event_device *clk)
+ {
+       __arch_timer_setup(ARCH_CP15_TIMER, clk);
  
        if (arch_timer_use_virtual)
                enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
@@@ -221,7 -403,24 +404,24 @@@ struct timecounter *arch_timer_get_time
        return &timecounter;
  }
  
 -static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
+ static void __init arch_counter_register(unsigned type)
+ {
+       u64 start_count;
+ 
+       /* Register the CP15 based counter if we have one */
+       if (type & ARCH_CP15_TIMER)
+               arch_timer_read_counter = arch_counter_get_cntvct;
+       else
+               arch_timer_read_counter = arch_counter_get_cntvct_mem;
+ 
+       start_count = arch_timer_read_counter();
+       clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+       cyclecounter.mult = clocksource_counter.mult;
+       cyclecounter.shift = clocksource_counter.shift;
+       timecounter_init(&timecounter, &cyclecounter, start_count);
+ }
+ 
 +static void arch_timer_stop(struct clock_event_device *clk)
  {
        pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
                 clk->irq, smp_processor_id());
@@@ -373,3 -615,69 +616,69 @@@ static void __init arch_timer_init(stru
  }
  CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
  CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
 -                              arch_timer_mem_use_virtual ? "virt" : "phys");
+ 
+ static void __init arch_timer_mem_init(struct device_node *np)
+ {
+       struct device_node *frame, *best_frame = NULL;
+       void __iomem *cntctlbase, *base;
+       unsigned int irq;
+       u32 cnttidr;
+ 
+       arch_timers_present |= ARCH_MEM_TIMER;
+       cntctlbase = of_iomap(np, 0);
+       if (!cntctlbase) {
+               pr_err("arch_timer: Can't find CNTCTLBase\n");
+               return;
+       }
+ 
+       cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
+       iounmap(cntctlbase);
+ 
+       /*
+        * Try to find a virtual capable frame. Otherwise fall back to a
+        * physical capable frame.
+        */
+       for_each_available_child_of_node(np, frame) {
+               int n;
+ 
+               if (of_property_read_u32(frame, "frame-number", &n)) {
+                       pr_err("arch_timer: Missing frame-number\n");
+                       of_node_put(best_frame);
+                       of_node_put(frame);
+                       return;
+               }
+ 
+               if (cnttidr & CNTTIDR_VIRT(n)) {
+                       of_node_put(best_frame);
+                       best_frame = frame;
+                       arch_timer_mem_use_virtual = true;
+                       break;
+               }
+               of_node_put(best_frame);
+               best_frame = of_node_get(frame);
+       }
+ 
+       base = arch_counter_base = of_iomap(best_frame, 0);
+       if (!base) {
+               pr_err("arch_timer: Can't map frame's registers\n");
+               of_node_put(best_frame);
+               return;
+       }
+ 
+       if (arch_timer_mem_use_virtual)
+               irq = irq_of_parse_and_map(best_frame, 1);
+       else
+               irq = irq_of_parse_and_map(best_frame, 0);
+       of_node_put(best_frame);
+       if (!irq) {
+               pr_err("arch_timer: Frame missing %s irq",
++                     arch_timer_mem_use_virtual ? "virt" : "phys");
+               return;
+       }
+ 
+       arch_timer_detect_rate(base, np);
+       arch_timer_mem_register(base, irq);
+       arch_timer_common_init();
+ }
+ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
+                      arch_timer_mem_init);