drm/i915: Mask the vblank interrupt on bdw by default
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 7 Nov 2013 14:31:52 +0000 (15:31 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:10:14 +0000 (18:10 +0100)
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_irq.c

index bf71e35..1ce5722 100644 (file)
@@ -2917,15 +2917,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 {
        struct drm_device *dev = dev_priv->dev;
-       uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
-                                  GEN8_PIPE_VBLANK |
-                                  GEN8_PIPE_CDCLK_CRC_DONE |
-                                  GEN8_PIPE_FIFO_UNDERRUN |
-                                  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+       uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
+               GEN8_PIPE_CDCLK_CRC_DONE |
+               GEN8_PIPE_FIFO_UNDERRUN |
+               GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+       uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
        int pipe;
-       dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
-       dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
-       dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
+       dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
+       dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
+       dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
 
        for_each_pipe(pipe) {
                u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));