2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/pm_runtime.h>
20 #include <linux/of_device.h>
21 #include <linux/scatterlist.h>
22 #include <linux/sh_dma.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/workqueue.h>
26 #include <sound/soc.h>
27 #include <sound/pcm_params.h>
28 #include <sound/sh_fsi.h>
30 /* PortA/PortB register */
31 #define REG_DO_FMT 0x0000
32 #define REG_DOFF_CTL 0x0004
33 #define REG_DOFF_ST 0x0008
34 #define REG_DI_FMT 0x000C
35 #define REG_DIFF_CTL 0x0010
36 #define REG_DIFF_ST 0x0014
37 #define REG_CKG1 0x0018
38 #define REG_CKG2 0x001C
39 #define REG_DIDT 0x0020
40 #define REG_DODT 0x0024
41 #define REG_MUTE_ST 0x0028
42 #define REG_OUT_DMAC 0x002C
43 #define REG_OUT_SEL 0x0030
44 #define REG_IN_DMAC 0x0038
47 #define MST_CLK_RST 0x0210
48 #define MST_SOFT_RST 0x0214
49 #define MST_FIFO_SZ 0x0218
51 /* core register (depend on FSI version) */
52 #define A_MST_CTLR 0x0180
53 #define B_MST_CTLR 0x01A0
54 #define CPU_INT_ST 0x01F4
55 #define CPU_IEMSK 0x01F8
56 #define CPU_IMSK 0x01FC
63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
72 #define CR_MONO (0x0 << 4)
73 #define CR_MONO_D (0x1 << 4)
74 #define CR_PCM (0x2 << 4)
75 #define CR_I2S (0x3 << 4)
76 #define CR_TDM (0x4 << 4)
77 #define CR_TDM_D (0x5 << 4)
81 #define VDMD_MASK (0x3 << 4)
82 #define VDMD_FRONT (0x0 << 4) /* Package in front */
83 #define VDMD_BACK (0x1 << 4) /* Package in back */
84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
86 #define DMA_ON (0x1 << 0)
90 #define IRQ_HALF 0x00100000
91 #define FIFO_CLR 0x00000001
94 #define ERR_OVER 0x00000010
95 #define ERR_UNDER 0x00000001
96 #define ST_ERR (ERR_OVER | ERR_UNDER)
99 #define ACKMD_MASK 0x00007000
100 #define BPFMD_MASK 0x00000700
101 #define DIMD (1 << 4)
102 #define DOMD (1 << 0)
105 #define BP (1 << 4) /* Fix the signal of Biphase output */
106 #define SE (1 << 0) /* Fix the master clock */
112 /* IO SHIFT / MACRO */
117 #define AB_IO(param, shift) (param << shift)
120 #define PBSR (1 << 12) /* Port B Software Reset */
121 #define PASR (1 << 8) /* Port A Software Reset */
122 #define IR (1 << 4) /* Interrupt Reset */
123 #define FSISR (1 << 0) /* Software Reset */
126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
127 /* 1: Biphase and serial */
130 #define FIFO_SZ_MASK 0x7
132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
141 * A : sample widtht 16bit setting
142 * B : sample widtht 24bit setting
145 #define SHIFT_16DATA 0
146 #define SHIFT_24DATA 4
148 #define PACKAGE_24BITBUS_BACK 0
149 #define PACKAGE_24BITBUS_FRONT 1
150 #define PACKAGE_16BITBUS_STREAM 2
152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
156 * FSI driver use below type name for variable
158 * xxx_num : number of data
159 * xxx_pos : position of data
160 * xxx_capa : capacity of data
164 * period/frame/sample image
168 * period pos period pos
170 * |<-------------------- period--------------------->|
171 * ==|============================================ ... =|==
173 * ||<----- frame ----->|<------ frame ----->| ... |
174 * |+--------------------+--------------------+- ... |
175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
176 * |+--------------------+--------------------+- ... |
177 * ==|============================================ ... =|==
195 * FSIxCLK [CPG] (ick) -------> |
196 * |-> FSI_DIV (div)-> FSI2
197 * FSIxCK [external] (xck) ---> |
204 struct fsi_stream_handler;
208 * these are initialized by fsi_stream_init()
210 struct snd_pcm_substream *substream;
211 int fifo_sample_capa; /* sample capacity of FSI FIFO */
212 int buff_sample_capa; /* sample capacity of ALSA buffer */
213 int buff_sample_pos; /* sample position of ALSA buffer */
214 int period_samples; /* sample number / 1 period */
215 int period_pos; /* current period position */
216 int sample_width; /* sample width */
226 * thse are initialized by fsi_handler_init()
228 struct fsi_stream_handler *handler;
229 struct fsi_priv *priv;
232 * these are for DMAEngine
234 struct dma_chan *chan;
235 struct work_struct work;
242 /* see [FSI clock] */
247 int (*set_rate)(struct device *dev,
248 struct fsi_priv *fsi);
256 struct fsi_master *master;
258 struct fsi_stream playback;
259 struct fsi_stream capture;
261 struct fsi_clk clock;
274 struct fsi_stream_handler {
275 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
276 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
277 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
278 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
279 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
280 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
283 #define fsi_stream_handler_call(io, func, args...) \
285 !((io)->handler->func) ? 0 : \
286 (io)->handler->func(args))
300 struct fsi_priv fsia;
301 struct fsi_priv fsib;
302 const struct fsi_core *core;
306 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
309 * basic read write function
312 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
314 /* valid data area is 24bit */
317 __raw_writel(data, reg);
320 static u32 __fsi_reg_read(u32 __iomem *reg)
322 return __raw_readl(reg);
325 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
327 u32 val = __fsi_reg_read(reg);
332 __fsi_reg_write(reg, val);
335 #define fsi_reg_write(p, r, d)\
336 __fsi_reg_write((p->base + REG_##r), d)
338 #define fsi_reg_read(p, r)\
339 __fsi_reg_read((p->base + REG_##r))
341 #define fsi_reg_mask_set(p, r, m, d)\
342 __fsi_reg_mask_set((p->base + REG_##r), m, d)
344 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
345 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
346 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
351 spin_lock_irqsave(&master->lock, flags);
352 ret = __fsi_reg_read(master->base + reg);
353 spin_unlock_irqrestore(&master->lock, flags);
358 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
359 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
360 static void _fsi_master_mask_set(struct fsi_master *master,
361 u32 reg, u32 mask, u32 data)
365 spin_lock_irqsave(&master->lock, flags);
366 __fsi_reg_mask_set(master->base + reg, mask, data);
367 spin_unlock_irqrestore(&master->lock, flags);
373 static int fsi_version(struct fsi_master *master)
375 return master->core->ver;
378 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
383 static int fsi_is_clk_master(struct fsi_priv *fsi)
385 return fsi->clk_master;
388 static int fsi_is_port_a(struct fsi_priv *fsi)
390 return fsi->master->base == fsi->base;
393 static int fsi_is_spdif(struct fsi_priv *fsi)
398 static int fsi_is_enable_stream(struct fsi_priv *fsi)
400 return fsi->enable_stream;
403 static int fsi_is_play(struct snd_pcm_substream *substream)
405 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
408 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
410 struct snd_soc_pcm_runtime *rtd = substream->private_data;
415 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
417 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
420 return &master->fsia;
422 return &master->fsib;
425 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
427 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
430 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
432 int is_play = fsi_stream_is_play(fsi, io);
433 int is_porta = fsi_is_port_a(fsi);
437 shift = is_play ? AO_SHIFT : AI_SHIFT;
439 shift = is_play ? BO_SHIFT : BI_SHIFT;
444 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
446 return frames * fsi->chan_num;
449 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
451 return samples / fsi->chan_num;
454 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
455 struct fsi_stream *io)
457 int is_play = fsi_stream_is_play(fsi, io);
462 fsi_reg_read(fsi, DOFF_ST) :
463 fsi_reg_read(fsi, DIFF_ST);
465 frames = 0x1ff & (status >> 8);
467 return fsi_frame2sample(fsi, frames);
470 static void fsi_count_fifo_err(struct fsi_priv *fsi)
472 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
473 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
475 if (ostatus & ERR_OVER)
476 fsi->playback.oerr_num++;
478 if (ostatus & ERR_UNDER)
479 fsi->playback.uerr_num++;
481 if (istatus & ERR_OVER)
482 fsi->capture.oerr_num++;
484 if (istatus & ERR_UNDER)
485 fsi->capture.uerr_num++;
487 fsi_reg_write(fsi, DOFF_ST, 0);
488 fsi_reg_write(fsi, DIFF_ST, 0);
492 * fsi_stream_xx() function
494 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
495 struct fsi_stream *io)
497 return &fsi->playback == io;
500 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
501 struct snd_pcm_substream *substream)
503 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
506 static int fsi_stream_is_working(struct fsi_priv *fsi,
507 struct fsi_stream *io)
509 struct fsi_master *master = fsi_get_master(fsi);
513 spin_lock_irqsave(&master->lock, flags);
514 ret = !!(io->substream && io->substream->runtime);
515 spin_unlock_irqrestore(&master->lock, flags);
520 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
525 static void fsi_stream_init(struct fsi_priv *fsi,
526 struct fsi_stream *io,
527 struct snd_pcm_substream *substream)
529 struct snd_pcm_runtime *runtime = substream->runtime;
530 struct fsi_master *master = fsi_get_master(fsi);
533 spin_lock_irqsave(&master->lock, flags);
534 io->substream = substream;
535 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
536 io->buff_sample_pos = 0;
537 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
539 io->sample_width = samples_to_bytes(runtime, 1);
541 io->oerr_num = -1; /* ignore 1st err */
542 io->uerr_num = -1; /* ignore 1st err */
543 fsi_stream_handler_call(io, init, fsi, io);
544 spin_unlock_irqrestore(&master->lock, flags);
547 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
549 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
550 struct fsi_master *master = fsi_get_master(fsi);
553 spin_lock_irqsave(&master->lock, flags);
555 if (io->oerr_num > 0)
556 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
558 if (io->uerr_num > 0)
559 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
561 fsi_stream_handler_call(io, quit, fsi, io);
562 io->substream = NULL;
563 io->buff_sample_capa = 0;
564 io->buff_sample_pos = 0;
565 io->period_samples = 0;
567 io->sample_width = 0;
571 spin_unlock_irqrestore(&master->lock, flags);
574 static int fsi_stream_transfer(struct fsi_stream *io)
576 struct fsi_priv *fsi = fsi_stream_to_priv(io);
580 return fsi_stream_handler_call(io, transfer, fsi, io);
583 #define fsi_stream_start(fsi, io)\
584 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
586 #define fsi_stream_stop(fsi, io)\
587 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
589 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
591 struct fsi_stream *io;
595 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
598 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
608 static int fsi_stream_remove(struct fsi_priv *fsi)
610 struct fsi_stream *io;
614 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
617 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
628 * format/bus/dma setting
630 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
631 u32 bus, struct device *dev)
633 struct fsi_master *master = fsi_get_master(fsi);
634 int is_play = fsi_stream_is_play(fsi, io);
637 if (fsi_version(master) >= 2) {
641 * FSI2 needs DMA/Bus setting
644 case PACKAGE_24BITBUS_FRONT:
647 dev_dbg(dev, "24bit bus / package in front\n");
649 case PACKAGE_16BITBUS_STREAM:
652 dev_dbg(dev, "16bit bus / stream mode\n");
654 case PACKAGE_24BITBUS_BACK:
658 dev_dbg(dev, "24bit bus / package in back\n");
663 fsi_reg_write(fsi, OUT_DMAC, dma);
665 fsi_reg_write(fsi, IN_DMAC, dma);
669 fsi_reg_write(fsi, DO_FMT, fmt);
671 fsi_reg_write(fsi, DI_FMT, fmt);
678 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
680 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
681 struct fsi_master *master = fsi_get_master(fsi);
683 fsi_core_mask_set(master, imsk, data, data);
684 fsi_core_mask_set(master, iemsk, data, data);
687 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
689 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
690 struct fsi_master *master = fsi_get_master(fsi);
692 fsi_core_mask_set(master, imsk, data, 0);
693 fsi_core_mask_set(master, iemsk, data, 0);
696 static u32 fsi_irq_get_status(struct fsi_master *master)
698 return fsi_core_read(master, int_st);
701 static void fsi_irq_clear_status(struct fsi_priv *fsi)
704 struct fsi_master *master = fsi_get_master(fsi);
706 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
707 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
709 /* clear interrupt factor */
710 fsi_core_mask_set(master, int_st, data, 0);
714 * SPDIF master clock function
716 * These functions are used later FSI2
718 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
720 struct fsi_master *master = fsi_get_master(fsi);
724 val = enable ? mask : 0;
727 fsi_core_mask_set(master, a_mclk, mask, val) :
728 fsi_core_mask_set(master, b_mclk, mask, val);
734 static int fsi_clk_init(struct device *dev,
735 struct fsi_priv *fsi,
739 int (*set_rate)(struct device *dev,
740 struct fsi_priv *fsi))
742 struct fsi_clk *clock = &fsi->clock;
743 int is_porta = fsi_is_port_a(fsi);
750 clock->set_rate = set_rate;
752 clock->own = devm_clk_get(dev, NULL);
753 if (IS_ERR(clock->own))
758 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
759 if (IS_ERR(clock->xck)) {
760 dev_err(dev, "can't get xck clock\n");
763 if (clock->xck == clock->own) {
764 dev_err(dev, "cpu doesn't support xck clock\n");
769 /* FSIACLK/FSIBCLK */
771 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
772 if (IS_ERR(clock->ick)) {
773 dev_err(dev, "can't get ick clock\n");
776 if (clock->ick == clock->own) {
777 dev_err(dev, "cpu doesn't support ick clock\n");
784 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
785 if (IS_ERR(clock->div)) {
786 dev_err(dev, "can't get div clock\n");
789 if (clock->div == clock->own) {
790 dev_err(dev, "cpu doens't support div clock\n");
798 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
799 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
801 fsi->clock.rate = rate;
804 static int fsi_clk_is_valid(struct fsi_priv *fsi)
806 return fsi->clock.set_rate &&
810 static int fsi_clk_enable(struct device *dev,
811 struct fsi_priv *fsi)
813 struct fsi_clk *clock = &fsi->clock;
816 if (!fsi_clk_is_valid(fsi))
819 if (0 == clock->count) {
820 ret = clock->set_rate(dev, fsi);
822 fsi_clk_invalid(fsi);
827 clk_enable(clock->xck);
829 clk_enable(clock->ick);
831 clk_enable(clock->div);
839 static int fsi_clk_disable(struct device *dev,
840 struct fsi_priv *fsi)
842 struct fsi_clk *clock = &fsi->clock;
844 if (!fsi_clk_is_valid(fsi))
847 if (1 == clock->count--) {
849 clk_disable(clock->xck);
851 clk_disable(clock->ick);
853 clk_disable(clock->div);
859 static int fsi_clk_set_ackbpf(struct device *dev,
860 struct fsi_priv *fsi,
861 int ackmd, int bpfmd)
865 /* check ackmd/bpfmd relationship */
867 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
889 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
914 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
918 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
920 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
926 static int fsi_clk_set_rate_external(struct device *dev,
927 struct fsi_priv *fsi)
929 struct clk *xck = fsi->clock.xck;
930 struct clk *ick = fsi->clock.ick;
931 unsigned long rate = fsi->clock.rate;
936 /* check clock rate */
937 xrate = clk_get_rate(xck);
939 dev_err(dev, "unsupported clock rate\n");
943 clk_set_parent(ick, xck);
944 clk_set_rate(ick, xrate);
946 bpfmd = fsi->chan_num * 32;
947 ackmd = xrate / rate;
949 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
951 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
953 dev_err(dev, "%s failed", __func__);
958 static int fsi_clk_set_rate_cpg(struct device *dev,
959 struct fsi_priv *fsi)
961 struct clk *ick = fsi->clock.ick;
962 struct clk *div = fsi->clock.div;
963 unsigned long rate = fsi->clock.rate;
964 unsigned long target = 0; /* 12288000 or 11289600 */
965 unsigned long actual, cout;
966 unsigned long diff, min;
967 unsigned long best_cout, best_act;
972 if (!(12288000 % rate))
974 if (!(11289600 % rate))
977 dev_err(dev, "unsupported rate\n");
981 bpfmd = fsi->chan_num * 32;
982 ackmd = target / rate;
983 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
985 dev_err(dev, "%s failed", __func__);
992 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
994 * But, it needs to find best match of CPG and FSI_DIV
995 * combination, since it is difficult to generate correct
996 * frequency of audio clock from ick clock only.
997 * Because ick is created from its parent clock.
999 * target = rate x [512/256/128/64]fs
1000 * cout = round(target x adjustment)
1001 * actual = cout / adjustment (by FSI-DIV) ~= target
1007 for (adj = 1; adj < 0xffff; adj++) {
1009 cout = target * adj;
1010 if (cout > 100000000) /* max clock = 100MHz */
1013 /* cout/actual audio clock */
1014 cout = clk_round_rate(ick, cout);
1015 actual = cout / adj;
1017 /* find best frequency */
1018 diff = abs(actual - target);
1026 ret = clk_set_rate(ick, best_cout);
1028 dev_err(dev, "ick clock failed\n");
1032 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1034 dev_err(dev, "div clock failed\n");
1038 dev_dbg(dev, "ick/div = %ld/%ld\n",
1039 clk_get_rate(ick), clk_get_rate(div));
1045 * pio data transfer handler
1047 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1051 if (fsi_is_enable_stream(fsi)) {
1055 * fsi_pio_push_init()
1057 u32 *buf = (u32 *)_buf;
1059 for (i = 0; i < samples / 2; i++)
1060 fsi_reg_write(fsi, DODT, buf[i]);
1063 u16 *buf = (u16 *)_buf;
1065 for (i = 0; i < samples; i++)
1066 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1070 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1072 u16 *buf = (u16 *)_buf;
1075 for (i = 0; i < samples; i++)
1076 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1079 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1081 u32 *buf = (u32 *)_buf;
1084 for (i = 0; i < samples; i++)
1085 fsi_reg_write(fsi, DODT, *(buf + i));
1088 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1090 u32 *buf = (u32 *)_buf;
1093 for (i = 0; i < samples; i++)
1094 *(buf + i) = fsi_reg_read(fsi, DIDT);
1097 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1099 struct snd_pcm_runtime *runtime = io->substream->runtime;
1101 return runtime->dma_area +
1102 samples_to_bytes(runtime, io->buff_sample_pos);
1105 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1106 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1107 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1110 struct snd_pcm_runtime *runtime;
1111 struct snd_pcm_substream *substream;
1115 if (!fsi_stream_is_working(fsi, io))
1119 substream = io->substream;
1120 runtime = substream->runtime;
1122 /* FSI FIFO has limit.
1123 * So, this driver can not send periods data at a time
1125 if (io->buff_sample_pos >=
1126 io->period_samples * (io->period_pos + 1)) {
1129 io->period_pos = (io->period_pos + 1) % runtime->periods;
1131 if (0 == io->period_pos)
1132 io->buff_sample_pos = 0;
1135 buf = fsi_pio_get_area(fsi, io);
1137 switch (io->sample_width) {
1139 run16(fsi, buf, samples);
1142 run32(fsi, buf, samples);
1148 /* update buff_sample_pos */
1149 io->buff_sample_pos += samples;
1152 snd_pcm_period_elapsed(substream);
1157 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1159 int sample_residues; /* samples in FSI fifo */
1160 int sample_space; /* ALSA free samples space */
1163 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1164 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1166 samples = min(sample_residues, sample_space);
1168 return fsi_pio_transfer(fsi, io,
1174 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1176 int sample_residues; /* ALSA residue samples */
1177 int sample_space; /* FSI fifo free samples space */
1180 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1181 sample_space = io->fifo_sample_capa -
1182 fsi_get_current_fifo_samples(fsi, io);
1184 samples = min(sample_residues, sample_space);
1186 return fsi_pio_transfer(fsi, io,
1192 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1195 struct fsi_master *master = fsi_get_master(fsi);
1196 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1199 fsi_irq_enable(fsi, io);
1201 fsi_irq_disable(fsi, io);
1203 if (fsi_is_clk_master(fsi))
1204 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1209 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1212 * we can use 16bit stream mode
1213 * when "playback" and "16bit data"
1214 * and platform allows "stream mode"
1218 if (fsi_is_enable_stream(fsi))
1219 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1220 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1222 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1223 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1227 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1230 * always 24bit bus, package back when "capture"
1232 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1233 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1237 static struct fsi_stream_handler fsi_pio_push_handler = {
1238 .init = fsi_pio_push_init,
1239 .transfer = fsi_pio_push,
1240 .start_stop = fsi_pio_start_stop,
1243 static struct fsi_stream_handler fsi_pio_pop_handler = {
1244 .init = fsi_pio_pop_init,
1245 .transfer = fsi_pio_pop,
1246 .start_stop = fsi_pio_start_stop,
1249 static irqreturn_t fsi_interrupt(int irq, void *data)
1251 struct fsi_master *master = data;
1252 u32 int_st = fsi_irq_get_status(master);
1254 /* clear irq status */
1255 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1256 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1258 if (int_st & AB_IO(1, AO_SHIFT))
1259 fsi_stream_transfer(&master->fsia.playback);
1260 if (int_st & AB_IO(1, BO_SHIFT))
1261 fsi_stream_transfer(&master->fsib.playback);
1262 if (int_st & AB_IO(1, AI_SHIFT))
1263 fsi_stream_transfer(&master->fsia.capture);
1264 if (int_st & AB_IO(1, BI_SHIFT))
1265 fsi_stream_transfer(&master->fsib.capture);
1267 fsi_count_fifo_err(&master->fsia);
1268 fsi_count_fifo_err(&master->fsib);
1270 fsi_irq_clear_status(&master->fsia);
1271 fsi_irq_clear_status(&master->fsib);
1277 * dma data transfer handler
1279 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1282 * 24bit data : 24bit bus / package in back
1283 * 16bit data : 16bit bus / stream mode
1285 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1286 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1288 io->loop_cnt = 2; /* push 1st, 2nd period first, then 3rd, 4th... */
1289 io->additional_pos = 0;
1294 static dma_addr_t fsi_dma_get_area(struct fsi_stream *io, int additional)
1296 struct snd_pcm_runtime *runtime = io->substream->runtime;
1297 int period = io->period_pos + additional;
1299 if (period >= runtime->periods)
1302 return runtime->dma_addr +
1303 samples_to_bytes(runtime, period * io->period_samples);
1306 static void fsi_dma_complete(void *data)
1308 struct fsi_stream *io = (struct fsi_stream *)data;
1309 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1310 struct snd_pcm_runtime *runtime = io->substream->runtime;
1312 io->buff_sample_pos += io->period_samples;
1315 if (io->period_pos >= runtime->periods) {
1317 io->buff_sample_pos = 0;
1320 fsi_count_fifo_err(fsi);
1321 fsi_stream_transfer(io);
1323 snd_pcm_period_elapsed(io->substream);
1326 static void fsi_dma_do_work(struct work_struct *work)
1328 struct fsi_stream *io = container_of(work, struct fsi_stream, work);
1329 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1330 struct snd_soc_dai *dai;
1331 struct dma_async_tx_descriptor *desc;
1332 struct snd_pcm_runtime *runtime;
1333 enum dma_data_direction dir;
1334 int is_play = fsi_stream_is_play(fsi, io);
1338 if (!fsi_stream_is_working(fsi, io))
1341 dai = fsi_get_dai(io->substream);
1342 runtime = io->substream->runtime;
1343 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1344 len = samples_to_bytes(runtime, io->period_samples);
1346 for (i = 0; i < io->loop_cnt; i++) {
1347 buf = fsi_dma_get_area(io, io->additional_pos);
1349 desc = dmaengine_prep_slave_single(io->chan, buf, len, dir,
1350 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1352 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
1356 desc->callback = fsi_dma_complete;
1357 desc->callback_param = io;
1359 if (dmaengine_submit(desc) < 0) {
1360 dev_err(dai->dev, "tx_submit() fail\n");
1364 dma_async_issue_pending(io->chan);
1366 io->additional_pos = 1;
1374 * In DMAEngine case, codec and FSI cannot be started simultaneously
1375 * since FSI is using the scheduler work queue.
1376 * Therefore, in capture case, probably FSI FIFO will have got
1377 * overflow error in this point.
1378 * in that case, DMA cannot start transfer until error was cleared.
1381 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1382 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1383 fsi_reg_write(fsi, DIFF_ST, 0);
1388 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1390 schedule_work(&io->work);
1395 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1398 struct fsi_master *master = fsi_get_master(fsi);
1399 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1400 u32 enable = start ? DMA_ON : 0;
1402 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1404 dmaengine_terminate_all(io->chan);
1406 if (fsi_is_clk_master(fsi))
1407 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1412 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1414 dma_cap_mask_t mask;
1415 int is_play = fsi_stream_is_play(fsi, io);
1418 dma_cap_set(DMA_SLAVE, mask);
1420 io->chan = dma_request_slave_channel_compat(mask,
1421 shdma_chan_filter, (void *)io->dma_id,
1422 dev, is_play ? "tx" : "rx");
1424 struct dma_slave_config cfg;
1427 cfg.slave_id = io->dma_id;
1428 cfg.dst_addr = 0; /* use default addr */
1429 cfg.src_addr = 0; /* use default addr */
1430 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1432 ret = dmaengine_slave_config(io->chan, &cfg);
1434 dma_release_channel(io->chan);
1441 /* switch to PIO handler */
1443 fsi->playback.handler = &fsi_pio_push_handler;
1445 fsi->capture.handler = &fsi_pio_pop_handler;
1447 dev_info(dev, "switch handler (dma => pio)\n");
1450 return fsi_stream_probe(fsi, dev);
1453 INIT_WORK(&io->work, fsi_dma_do_work);
1458 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1460 cancel_work_sync(&io->work);
1462 fsi_stream_stop(fsi, io);
1465 dma_release_channel(io->chan);
1471 static struct fsi_stream_handler fsi_dma_push_handler = {
1472 .init = fsi_dma_init,
1473 .probe = fsi_dma_probe,
1474 .transfer = fsi_dma_transfer,
1475 .remove = fsi_dma_remove,
1476 .start_stop = fsi_dma_push_start_stop,
1482 static void fsi_fifo_init(struct fsi_priv *fsi,
1483 struct fsi_stream *io,
1486 struct fsi_master *master = fsi_get_master(fsi);
1487 int is_play = fsi_stream_is_play(fsi, io);
1491 /* get on-chip RAM capacity */
1492 shift = fsi_master_read(master, FIFO_SZ);
1493 shift >>= fsi_get_port_shift(fsi, io);
1494 shift &= FIFO_SZ_MASK;
1495 frame_capa = 256 << shift;
1496 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1499 * The maximum number of sample data varies depending
1500 * on the number of channels selected for the format.
1502 * FIFOs are used in 4-channel units in 3-channel mode
1503 * and in 8-channel units in 5- to 7-channel mode
1504 * meaning that more FIFOs than the required size of DPRAM
1507 * ex) if 256 words of DP-RAM is connected
1508 * 1 channel: 256 (256 x 1 = 256)
1509 * 2 channels: 128 (128 x 2 = 256)
1510 * 3 channels: 64 ( 64 x 3 = 192)
1511 * 4 channels: 64 ( 64 x 4 = 256)
1512 * 5 channels: 32 ( 32 x 5 = 160)
1513 * 6 channels: 32 ( 32 x 6 = 192)
1514 * 7 channels: 32 ( 32 x 7 = 224)
1515 * 8 channels: 32 ( 32 x 8 = 256)
1517 for (i = 1; i < fsi->chan_num; i <<= 1)
1519 dev_dbg(dev, "%d channel %d store\n",
1520 fsi->chan_num, frame_capa);
1522 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1525 * set interrupt generation factor
1529 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1530 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1532 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1533 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1537 static int fsi_hw_startup(struct fsi_priv *fsi,
1538 struct fsi_stream *io,
1544 if (fsi_is_clk_master(fsi))
1547 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1549 /* clock inversion (CKG2) */
1551 if (fsi->bit_clk_inv)
1553 if (fsi->lr_clk_inv)
1555 if (fsi_is_clk_master(fsi))
1557 fsi_reg_write(fsi, CKG2, data);
1560 if (fsi_is_spdif(fsi)) {
1561 fsi_spdif_clk_ctrl(fsi, 1);
1562 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1569 switch (io->sample_width) {
1571 data = BUSOP_GET(16, io->bus_option);
1574 data = BUSOP_GET(24, io->bus_option);
1577 fsi_format_bus_setup(fsi, io, data, dev);
1580 fsi_irq_disable(fsi, io);
1581 fsi_irq_clear_status(fsi);
1584 fsi_fifo_init(fsi, io, dev);
1586 /* start master clock */
1587 if (fsi_is_clk_master(fsi))
1588 return fsi_clk_enable(dev, fsi);
1593 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1596 /* stop master clock */
1597 if (fsi_is_clk_master(fsi))
1598 return fsi_clk_disable(dev, fsi);
1603 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1604 struct snd_soc_dai *dai)
1606 struct fsi_priv *fsi = fsi_get_priv(substream);
1608 fsi_clk_invalid(fsi);
1613 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1614 struct snd_soc_dai *dai)
1616 struct fsi_priv *fsi = fsi_get_priv(substream);
1618 fsi_clk_invalid(fsi);
1621 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1622 struct snd_soc_dai *dai)
1624 struct fsi_priv *fsi = fsi_get_priv(substream);
1625 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1629 case SNDRV_PCM_TRIGGER_START:
1630 fsi_stream_init(fsi, io, substream);
1632 ret = fsi_hw_startup(fsi, io, dai->dev);
1634 ret = fsi_stream_transfer(io);
1636 fsi_stream_start(fsi, io);
1638 case SNDRV_PCM_TRIGGER_STOP:
1640 ret = fsi_hw_shutdown(fsi, dai->dev);
1641 fsi_stream_stop(fsi, io);
1642 fsi_stream_quit(fsi, io);
1649 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1651 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1652 case SND_SOC_DAIFMT_I2S:
1656 case SND_SOC_DAIFMT_LEFT_J:
1667 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1669 struct fsi_master *master = fsi_get_master(fsi);
1671 if (fsi_version(master) < 2)
1674 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1680 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1682 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1685 /* set master/slave audio interface */
1686 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1687 case SND_SOC_DAIFMT_CBM_CFM:
1689 case SND_SOC_DAIFMT_CBS_CFS:
1690 fsi->clk_master = 1; /* codec is slave, cpu is master */
1696 /* set clock inversion */
1697 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1698 case SND_SOC_DAIFMT_NB_IF:
1699 fsi->bit_clk_inv = 0;
1700 fsi->lr_clk_inv = 1;
1702 case SND_SOC_DAIFMT_IB_NF:
1703 fsi->bit_clk_inv = 1;
1704 fsi->lr_clk_inv = 0;
1706 case SND_SOC_DAIFMT_IB_IF:
1707 fsi->bit_clk_inv = 1;
1708 fsi->lr_clk_inv = 1;
1710 case SND_SOC_DAIFMT_NB_NF:
1712 fsi->bit_clk_inv = 0;
1713 fsi->lr_clk_inv = 0;
1717 if (fsi_is_clk_master(fsi)) {
1719 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1720 fsi_clk_set_rate_cpg);
1722 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1723 fsi_clk_set_rate_external);
1727 if (fsi_is_spdif(fsi))
1728 ret = fsi_set_fmt_spdif(fsi);
1730 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1735 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1736 struct snd_pcm_hw_params *params,
1737 struct snd_soc_dai *dai)
1739 struct fsi_priv *fsi = fsi_get_priv(substream);
1741 if (fsi_is_clk_master(fsi))
1742 fsi_clk_valid(fsi, params_rate(params));
1747 static const struct snd_soc_dai_ops fsi_dai_ops = {
1748 .startup = fsi_dai_startup,
1749 .shutdown = fsi_dai_shutdown,
1750 .trigger = fsi_dai_trigger,
1751 .set_fmt = fsi_dai_set_fmt,
1752 .hw_params = fsi_dai_hw_params,
1759 static struct snd_pcm_hardware fsi_pcm_hardware = {
1760 .info = SNDRV_PCM_INFO_INTERLEAVED |
1761 SNDRV_PCM_INFO_MMAP |
1762 SNDRV_PCM_INFO_MMAP_VALID,
1763 .buffer_bytes_max = 64 * 1024,
1764 .period_bytes_min = 32,
1765 .period_bytes_max = 8192,
1771 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1773 struct snd_pcm_runtime *runtime = substream->runtime;
1776 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1778 ret = snd_pcm_hw_constraint_integer(runtime,
1779 SNDRV_PCM_HW_PARAM_PERIODS);
1784 static int fsi_hw_params(struct snd_pcm_substream *substream,
1785 struct snd_pcm_hw_params *hw_params)
1787 return snd_pcm_lib_malloc_pages(substream,
1788 params_buffer_bytes(hw_params));
1791 static int fsi_hw_free(struct snd_pcm_substream *substream)
1793 return snd_pcm_lib_free_pages(substream);
1796 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1798 struct fsi_priv *fsi = fsi_get_priv(substream);
1799 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1801 return fsi_sample2frame(fsi, io->buff_sample_pos);
1804 static struct snd_pcm_ops fsi_pcm_ops = {
1805 .open = fsi_pcm_open,
1806 .ioctl = snd_pcm_lib_ioctl,
1807 .hw_params = fsi_hw_params,
1808 .hw_free = fsi_hw_free,
1809 .pointer = fsi_pointer,
1816 #define PREALLOC_BUFFER (32 * 1024)
1817 #define PREALLOC_BUFFER_MAX (32 * 1024)
1819 static void fsi_pcm_free(struct snd_pcm *pcm)
1821 snd_pcm_lib_preallocate_free_for_all(pcm);
1824 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1826 return snd_pcm_lib_preallocate_pages_for_all(
1829 rtd->card->snd_card->dev,
1830 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1837 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1842 .formats = FSI_FMTS,
1848 .formats = FSI_FMTS,
1852 .ops = &fsi_dai_ops,
1858 .formats = FSI_FMTS,
1864 .formats = FSI_FMTS,
1868 .ops = &fsi_dai_ops,
1872 static struct snd_soc_platform_driver fsi_soc_platform = {
1873 .ops = &fsi_pcm_ops,
1874 .pcm_new = fsi_pcm_new,
1875 .pcm_free = fsi_pcm_free,
1878 static const struct snd_soc_component_driver fsi_soc_component = {
1885 static void fsi_of_parse(char *name,
1886 struct device_node *np,
1887 struct sh_fsi_port_info *info,
1892 unsigned long flags = 0;
1896 } of_parse_property[] = {
1897 { "spdif-connection", SH_FSI_FMT_SPDIF },
1898 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1899 { "use-internal-clock", SH_FSI_CLK_CPG },
1902 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1903 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1904 if (of_get_property(np, prop, NULL))
1905 flags |= of_parse_property[i].val;
1907 info->flags = flags;
1909 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1912 static void fsi_port_info_init(struct fsi_priv *fsi,
1913 struct sh_fsi_port_info *info)
1915 if (info->flags & SH_FSI_FMT_SPDIF)
1918 if (info->flags & SH_FSI_CLK_CPG)
1921 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1922 fsi->enable_stream = 1;
1925 static void fsi_handler_init(struct fsi_priv *fsi,
1926 struct sh_fsi_port_info *info)
1928 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1929 fsi->playback.priv = fsi;
1930 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1931 fsi->capture.priv = fsi;
1934 fsi->playback.dma_id = info->tx_id;
1935 fsi->playback.handler = &fsi_dma_push_handler;
1939 static struct of_device_id fsi_of_match[];
1940 static int fsi_probe(struct platform_device *pdev)
1942 struct fsi_master *master;
1943 struct device_node *np = pdev->dev.of_node;
1944 struct sh_fsi_platform_info info;
1945 const struct fsi_core *core;
1946 struct fsi_priv *fsi;
1947 struct resource *res;
1951 memset(&info, 0, sizeof(info));
1955 const struct of_device_id *of_id;
1957 of_id = of_match_device(fsi_of_match, &pdev->dev);
1960 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1961 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1964 const struct platform_device_id *id_entry = pdev->id_entry;
1966 core = (struct fsi_core *)id_entry->driver_data;
1968 if (pdev->dev.platform_data)
1969 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1973 dev_err(&pdev->dev, "unknown fsi device\n");
1977 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1978 irq = platform_get_irq(pdev, 0);
1979 if (!res || (int)irq <= 0) {
1980 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1984 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1986 dev_err(&pdev->dev, "Could not allocate master\n");
1990 master->base = devm_ioremap_nocache(&pdev->dev,
1991 res->start, resource_size(res));
1992 if (!master->base) {
1993 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1997 /* master setting */
1998 master->core = core;
1999 spin_lock_init(&master->lock);
2002 fsi = &master->fsia;
2003 fsi->base = master->base;
2004 fsi->master = master;
2005 fsi_port_info_init(fsi, &info.port_a);
2006 fsi_handler_init(fsi, &info.port_a);
2007 ret = fsi_stream_probe(fsi, &pdev->dev);
2009 dev_err(&pdev->dev, "FSIA stream probe failed\n");
2014 fsi = &master->fsib;
2015 fsi->base = master->base + 0x40;
2016 fsi->master = master;
2017 fsi_port_info_init(fsi, &info.port_b);
2018 fsi_handler_init(fsi, &info.port_b);
2019 ret = fsi_stream_probe(fsi, &pdev->dev);
2021 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2025 pm_runtime_enable(&pdev->dev);
2026 dev_set_drvdata(&pdev->dev, master);
2028 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2029 dev_name(&pdev->dev), master);
2031 dev_err(&pdev->dev, "irq request err\n");
2035 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
2037 dev_err(&pdev->dev, "cannot snd soc register\n");
2041 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2042 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2044 dev_err(&pdev->dev, "cannot snd component register\n");
2051 snd_soc_unregister_platform(&pdev->dev);
2053 pm_runtime_disable(&pdev->dev);
2054 fsi_stream_remove(&master->fsib);
2056 fsi_stream_remove(&master->fsia);
2061 static int fsi_remove(struct platform_device *pdev)
2063 struct fsi_master *master;
2065 master = dev_get_drvdata(&pdev->dev);
2067 pm_runtime_disable(&pdev->dev);
2069 snd_soc_unregister_component(&pdev->dev);
2070 snd_soc_unregister_platform(&pdev->dev);
2072 fsi_stream_remove(&master->fsia);
2073 fsi_stream_remove(&master->fsib);
2078 static void __fsi_suspend(struct fsi_priv *fsi,
2079 struct fsi_stream *io,
2082 if (!fsi_stream_is_working(fsi, io))
2085 fsi_stream_stop(fsi, io);
2086 fsi_hw_shutdown(fsi, dev);
2089 static void __fsi_resume(struct fsi_priv *fsi,
2090 struct fsi_stream *io,
2093 if (!fsi_stream_is_working(fsi, io))
2096 fsi_hw_startup(fsi, io, dev);
2097 fsi_stream_start(fsi, io);
2100 static int fsi_suspend(struct device *dev)
2102 struct fsi_master *master = dev_get_drvdata(dev);
2103 struct fsi_priv *fsia = &master->fsia;
2104 struct fsi_priv *fsib = &master->fsib;
2106 __fsi_suspend(fsia, &fsia->playback, dev);
2107 __fsi_suspend(fsia, &fsia->capture, dev);
2109 __fsi_suspend(fsib, &fsib->playback, dev);
2110 __fsi_suspend(fsib, &fsib->capture, dev);
2115 static int fsi_resume(struct device *dev)
2117 struct fsi_master *master = dev_get_drvdata(dev);
2118 struct fsi_priv *fsia = &master->fsia;
2119 struct fsi_priv *fsib = &master->fsib;
2121 __fsi_resume(fsia, &fsia->playback, dev);
2122 __fsi_resume(fsia, &fsia->capture, dev);
2124 __fsi_resume(fsib, &fsib->playback, dev);
2125 __fsi_resume(fsib, &fsib->capture, dev);
2130 static struct dev_pm_ops fsi_pm_ops = {
2131 .suspend = fsi_suspend,
2132 .resume = fsi_resume,
2135 static struct fsi_core fsi1_core = {
2144 static struct fsi_core fsi2_core = {
2148 .int_st = CPU_INT_ST,
2151 .a_mclk = A_MST_CTLR,
2152 .b_mclk = B_MST_CTLR,
2155 static struct of_device_id fsi_of_match[] = {
2156 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
2157 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
2160 MODULE_DEVICE_TABLE(of, fsi_of_match);
2162 static struct platform_device_id fsi_id_table[] = {
2163 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
2164 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
2167 MODULE_DEVICE_TABLE(platform, fsi_id_table);
2169 static struct platform_driver fsi_driver = {
2171 .name = "fsi-pcm-audio",
2173 .of_match_table = fsi_of_match,
2176 .remove = fsi_remove,
2177 .id_table = fsi_id_table,
2180 module_platform_driver(fsi_driver);
2182 MODULE_LICENSE("GPL");
2183 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2184 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2185 MODULE_ALIAS("platform:fsi-pcm-audio");