drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22
  23 #include "rcar_du_crtc.h"
  24 #include "rcar_du_drv.h"
  25 #include "rcar_du_kms.h"
  26 #include "rcar_du_plane.h"
  27 #include "rcar_du_regs.h"
  28
  29 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  30 {
  31         struct rcar_du_device *rcdu = rcrtc->group->dev;
  32
  33         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  34 }
  35
  36 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  37 {
  38         struct rcar_du_device *rcdu = rcrtc->group->dev;
  39
  40         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  41 }
  42
  43 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  44 {
  45         struct rcar_du_device *rcdu = rcrtc->group->dev;
  46
  47         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  48                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  49 }
  50
  51 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  52 {
  53         struct rcar_du_device *rcdu = rcrtc->group->dev;
  54
  55         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  56                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  57 }
  58
  59 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  60                                  u32 clr, u32 set)
  61 {
  62         struct rcar_du_device *rcdu = rcrtc->group->dev;
  63         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  64
  65         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  66 }
  67
  68 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  69 {
  70         int ret;
  71
  72         ret = clk_prepare_enable(rcrtc->clock);
  73         if (ret < 0)
  74                 return ret;
  75
  76         ret = rcar_du_group_get(rcrtc->group);
  77         if (ret < 0)
  78                 clk_disable_unprepare(rcrtc->clock);
  79
  80         return ret;
  81 }
  82
  83 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  84 {
  85         rcar_du_group_put(rcrtc->group);
  86         clk_disable_unprepare(rcrtc->clock);
  87 }
  88
  89 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
  90 {
  91         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  92         unsigned long clk;
  93         u32 value;
  94         u32 div;
  95
  96         /* Dot clock */
  97         clk = clk_get_rate(rcrtc->clock);
  98         div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
  99         div = clamp(div, 1U, 64U) - 1;
 100
 101         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 102                             ESCR_DCLKSEL_CLKS | div);
 103         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 104
 105         /* Signal polarities */
 106         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 107               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 108               | DSMR_DIPM_DE;
 109         rcar_du_crtc_write(rcrtc, DSMR, value);
 110
 111         /* Display timings */
 112         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 113         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 114                                         mode->hdisplay - 19);
 115         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 116                                         mode->hsync_start - 1);
 117         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 118
 119         rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
 120         rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
 121                                         mode->vdisplay - 2);
 122         rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
 123                                         mode->vsync_start - 1);
 124         rcar_du_crtc_write(rcrtc, VCR,  mode->vtotal - 1);
 125
 126         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 127         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 128 }
 129
 130 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 131                                enum rcar_du_output output)
 132 {
 133         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 134         struct rcar_du_device *rcdu = rcrtc->group->dev;
 135
 136         /* Store the route from the CRTC output to the DU output. The DU will be
 137          * configured when starting the CRTC.
 138          */
 139         rcrtc->outputs |= BIT(output);
 140
 141         /* Store RGB routing to DPAD0 for R8A7790. */
 142         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) &&
 143             output == RCAR_DU_OUTPUT_DPAD0)
 144                 rcdu->dpad0_source = rcrtc->index;
 145 }
 146
 147 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 148 {
 149         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 150         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 151         unsigned int num_planes = 0;
 152         unsigned int prio = 0;
 153         unsigned int i;
 154         u32 dptsr = 0;
 155         u32 dspr = 0;
 156
 157         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 158                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 159                 unsigned int j;
 160
 161                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 162                         continue;
 163
 164                 /* Insert the plane in the sorted planes array. */
 165                 for (j = num_planes++; j > 0; --j) {
 166                         if (planes[j-1]->zpos <= plane->zpos)
 167                                 break;
 168                         planes[j] = planes[j-1];
 169                 }
 170
 171                 planes[j] = plane;
 172                 prio += plane->format->planes * 4;
 173         }
 174
 175         for (i = 0; i < num_planes; ++i) {
 176                 struct rcar_du_plane *plane = planes[i];
 177                 unsigned int index = plane->hwindex;
 178
 179                 prio -= 4;
 180                 dspr |= (index + 1) << prio;
 181                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 182
 183                 if (plane->format->planes == 2) {
 184                         index = (index + 1) % 8;
 185
 186                         prio -= 4;
 187                         dspr |= (index + 1) << prio;
 188                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 189                 }
 190         }
 191
 192         /* Select display timing and dot clock generator 2 for planes associated
 193          * with superposition controller 2.
 194          */
 195         if (rcrtc->index % 2) {
 196                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 197
 198                 /* The DPTSR register is updated when the display controller is
 199                  * stopped. We thus need to restart the DU. Once again, sorry
 200                  * for the flicker. One way to mitigate the issue would be to
 201                  * pre-associate planes with CRTCs (either with a fixed 4/4
 202                  * split, or through a module parameter). Flicker would then
 203                  * occur only if we need to break the pre-association.
 204                  */
 205                 if (value != dptsr) {
 206                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 207                         if (rcrtc->group->used_crtcs)
 208                                 rcar_du_group_restart(rcrtc->group);
 209                 }
 210         }
 211
 212         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 213                             dspr);
 214 }
 215
 216 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 217 {
 218         struct drm_crtc *crtc = &rcrtc->crtc;
 219         unsigned int i;
 220
 221         if (rcrtc->started)
 222                 return;
 223
 224         if (WARN_ON(rcrtc->plane->format == NULL))
 225                 return;
 226
 227         /* Set display off and background to black */
 228         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 229         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 230
 231         /* Configure display timings and output routing */
 232         rcar_du_crtc_set_display_timing(rcrtc);
 233         rcar_du_group_set_routing(rcrtc->group);
 234
 235         mutex_lock(&rcrtc->group->planes.lock);
 236         rcrtc->plane->enabled = true;
 237         rcar_du_crtc_update_planes(crtc);
 238         mutex_unlock(&rcrtc->group->planes.lock);
 239
 240         /* Setup planes. */
 241         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 242                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 243
 244                 if (plane->crtc != crtc || !plane->enabled)
 245                         continue;
 246
 247                 rcar_du_plane_setup(plane);
 248         }
 249
 250         /* Select master sync mode. This enables display operation in master
 251          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 252          * actively driven).
 253          */
 254         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
 255
 256         rcar_du_group_start_stop(rcrtc->group, true);
 257
 258         rcrtc->started = true;
 259 }
 260
 261 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 262 {
 263         struct drm_crtc *crtc = &rcrtc->crtc;
 264
 265         if (!rcrtc->started)
 266                 return;
 267
 268         mutex_lock(&rcrtc->group->planes.lock);
 269         rcrtc->plane->enabled = false;
 270         rcar_du_crtc_update_planes(crtc);
 271         mutex_unlock(&rcrtc->group->planes.lock);
 272
 273         /* Select switch sync mode. This stops display operation and configures
 274          * the HSYNC and VSYNC signals as inputs.
 275          */
 276         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 277
 278         rcar_du_group_start_stop(rcrtc->group, false);
 279
 280         rcrtc->started = false;
 281 }
 282
 283 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 284 {
 285         rcar_du_crtc_stop(rcrtc);
 286         rcar_du_crtc_put(rcrtc);
 287 }
 288
 289 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 290 {
 291         if (rcrtc->dpms != DRM_MODE_DPMS_ON)
 292                 return;
 293
 294         rcar_du_crtc_get(rcrtc);
 295         rcar_du_crtc_start(rcrtc);
 296 }
 297
 298 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 299 {
 300         struct drm_crtc *crtc = &rcrtc->crtc;
 301
 302         rcar_du_plane_compute_base(rcrtc->plane, crtc->fb);
 303         rcar_du_plane_update_base(rcrtc->plane);
 304 }
 305
 306 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 307 {
 308         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 309
 310         if (rcrtc->dpms == mode)
 311                 return;
 312
 313         if (mode == DRM_MODE_DPMS_ON) {
 314                 rcar_du_crtc_get(rcrtc);
 315                 rcar_du_crtc_start(rcrtc);
 316         } else {
 317                 rcar_du_crtc_stop(rcrtc);
 318                 rcar_du_crtc_put(rcrtc);
 319         }
 320
 321         rcrtc->dpms = mode;
 322 }
 323
 324 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 325                                     const struct drm_display_mode *mode,
 326                                     struct drm_display_mode *adjusted_mode)
 327 {
 328         /* TODO Fixup modes */
 329         return true;
 330 }
 331
 332 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
 333 {
 334         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 335
 336         /* We need to access the hardware during mode set, acquire a reference
 337          * to the CRTC.
 338          */
 339         rcar_du_crtc_get(rcrtc);
 340
 341         /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
 342          * result.
 343          */
 344         rcar_du_crtc_stop(rcrtc);
 345         rcar_du_plane_release(rcrtc->plane);
 346
 347         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 348 }
 349
 350 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
 351                                  struct drm_display_mode *mode,
 352                                  struct drm_display_mode *adjusted_mode,
 353                                  int x, int y,
 354                                  struct drm_framebuffer *old_fb)
 355 {
 356         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 357         struct rcar_du_device *rcdu = rcrtc->group->dev;
 358         const struct rcar_du_format_info *format;
 359         int ret;
 360
 361         format = rcar_du_format_info(crtc->fb->pixel_format);
 362         if (format == NULL) {
 363                 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
 364                         crtc->fb->pixel_format);
 365                 ret = -EINVAL;
 366                 goto error;
 367         }
 368
 369         ret = rcar_du_plane_reserve(rcrtc->plane, format);
 370         if (ret < 0)
 371                 goto error;
 372
 373         rcrtc->plane->format = format;
 374
 375         rcrtc->plane->src_x = x;
 376         rcrtc->plane->src_y = y;
 377         rcrtc->plane->width = mode->hdisplay;
 378         rcrtc->plane->height = mode->vdisplay;
 379
 380         rcar_du_plane_compute_base(rcrtc->plane, crtc->fb);
 381
 382         rcrtc->outputs = 0;
 383
 384         return 0;
 385
 386 error:
 387         /* There's no rollback/abort operation to clean up in case of error. We
 388          * thus need to release the reference to the CRTC acquired in prepare()
 389          * here.
 390          */
 391         rcar_du_crtc_put(rcrtc);
 392         return ret;
 393 }
 394
 395 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
 396 {
 397         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 398
 399         /* We're done, restart the CRTC and set the DPMS mode to on. The
 400          * reference to the DU acquired at prepare() time will thus be released
 401          * by the DPMS handler (possibly called by the disable() handler).
 402          */
 403         rcar_du_crtc_start(rcrtc);
 404         rcrtc->dpms = DRM_MODE_DPMS_ON;
 405 }
 406
 407 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 408                                       struct drm_framebuffer *old_fb)
 409 {
 410         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 411
 412         rcrtc->plane->src_x = x;
 413         rcrtc->plane->src_y = y;
 414
 415         rcar_du_crtc_update_base(rcrtc);
 416
 417         return 0;
 418 }
 419
 420 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 421 {
 422         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 423
 424         rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 425         rcar_du_plane_release(rcrtc->plane);
 426 }
 427
 428 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 429         .dpms = rcar_du_crtc_dpms,
 430         .mode_fixup = rcar_du_crtc_mode_fixup,
 431         .prepare = rcar_du_crtc_mode_prepare,
 432         .commit = rcar_du_crtc_mode_commit,
 433         .mode_set = rcar_du_crtc_mode_set,
 434         .mode_set_base = rcar_du_crtc_mode_set_base,
 435         .disable = rcar_du_crtc_disable,
 436 };
 437
 438 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 439                                    struct drm_file *file)
 440 {
 441         struct drm_pending_vblank_event *event;
 442         struct drm_device *dev = rcrtc->crtc.dev;
 443         unsigned long flags;
 444
 445         /* Destroy the pending vertical blanking event associated with the
 446          * pending page flip, if any, and disable vertical blanking interrupts.
 447          */
 448         spin_lock_irqsave(&dev->event_lock, flags);
 449         event = rcrtc->event;
 450         if (event && event->base.file_priv == file) {
 451                 rcrtc->event = NULL;
 452                 event->base.destroy(&event->base);
 453                 drm_vblank_put(dev, rcrtc->index);
 454         }
 455         spin_unlock_irqrestore(&dev->event_lock, flags);
 456 }
 457
 458 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 459 {
 460         struct drm_pending_vblank_event *event;
 461         struct drm_device *dev = rcrtc->crtc.dev;
 462         unsigned long flags;
 463
 464         spin_lock_irqsave(&dev->event_lock, flags);
 465         event = rcrtc->event;
 466         rcrtc->event = NULL;
 467         spin_unlock_irqrestore(&dev->event_lock, flags);
 468
 469         if (event == NULL)
 470                 return;
 471
 472         spin_lock_irqsave(&dev->event_lock, flags);
 473         drm_send_vblank_event(dev, rcrtc->index, event);
 474         spin_unlock_irqrestore(&dev->event_lock, flags);
 475
 476         drm_vblank_put(dev, rcrtc->index);
 477 }
 478
 479 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 480 {
 481         struct rcar_du_crtc *rcrtc = arg;
 482         irqreturn_t ret = IRQ_NONE;
 483         u32 status;
 484
 485         status = rcar_du_crtc_read(rcrtc, DSSR);
 486         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 487
 488         if (status & DSSR_VBK) {
 489                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 490                 rcar_du_crtc_finish_page_flip(rcrtc);
 491                 ret = IRQ_HANDLED;
 492         }
 493
 494         return ret;
 495 }
 496
 497 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 498                                   struct drm_framebuffer *fb,
 499                                   struct drm_pending_vblank_event *event,
 500                                   uint32_t page_flip_flags)
 501 {
 502         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 503         struct drm_device *dev = rcrtc->crtc.dev;
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&dev->event_lock, flags);
 507         if (rcrtc->event != NULL) {
 508                 spin_unlock_irqrestore(&dev->event_lock, flags);
 509                 return -EBUSY;
 510         }
 511         spin_unlock_irqrestore(&dev->event_lock, flags);
 512
 513         crtc->fb = fb;
 514         rcar_du_crtc_update_base(rcrtc);
 515
 516         if (event) {
 517                 event->pipe = rcrtc->index;
 518                 drm_vblank_get(dev, rcrtc->index);
 519                 spin_lock_irqsave(&dev->event_lock, flags);
 520                 rcrtc->event = event;
 521                 spin_unlock_irqrestore(&dev->event_lock, flags);
 522         }
 523
 524         return 0;
 525 }
 526
 527 static const struct drm_crtc_funcs crtc_funcs = {
 528         .destroy = drm_crtc_cleanup,
 529         .set_config = drm_crtc_helper_set_config,
 530         .page_flip = rcar_du_crtc_page_flip,
 531 };
 532
 533 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 534 {
 535         static const unsigned int mmio_offsets[] = {
 536                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 537         };
 538
 539         struct rcar_du_device *rcdu = rgrp->dev;
 540         struct platform_device *pdev = to_platform_device(rcdu->dev);
 541         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 542         struct drm_crtc *crtc = &rcrtc->crtc;
 543         unsigned int irqflags;
 544         char clk_name[5];
 545         char *name;
 546         int irq;
 547         int ret;
 548
 549         /* Get the CRTC clock. */
 550         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 551                 sprintf(clk_name, "du.%u", index);
 552                 name = clk_name;
 553         } else {
 554                 name = NULL;
 555         }
 556
 557         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 558         if (IS_ERR(rcrtc->clock)) {
 559                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 560                 return PTR_ERR(rcrtc->clock);
 561         }
 562
 563         rcrtc->group = rgrp;
 564         rcrtc->mmio_offset = mmio_offsets[index];
 565         rcrtc->index = index;
 566         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 567         rcrtc->plane = &rgrp->planes.planes[index % 2];
 568
 569         rcrtc->plane->crtc = crtc;
 570
 571         ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
 572         if (ret < 0)
 573                 return ret;
 574
 575         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 576
 577         /* Register the interrupt handler. */
 578         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 579                 irq = platform_get_irq(pdev, index);
 580                 irqflags = 0;
 581         } else {
 582                 irq = platform_get_irq(pdev, 0);
 583                 irqflags = IRQF_SHARED;
 584         }
 585
 586         if (irq < 0) {
 587                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 588                 return irq;
 589         }
 590
 591         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 592                                dev_name(rcdu->dev), rcrtc);
 593         if (ret < 0) {
 594                 dev_err(rcdu->dev,
 595                         "failed to register IRQ for CRTC %u\n", index);
 596                 return ret;
 597         }
 598
 599         return 0;
 600 }
 601
 602 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 603 {
 604         if (enable) {
 605                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 606                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 607         } else {
 608                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 609         }
 610 }