2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
23 #include "rcar_du_crtc.h"
24 #include "rcar_du_drv.h"
25 #include "rcar_du_kms.h"
26 #include "rcar_du_plane.h"
27 #include "rcar_du_regs.h"
29 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
31 struct rcar_du_device *rcdu = rcrtc->group->dev;
33 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
36 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
38 struct rcar_du_device *rcdu = rcrtc->group->dev;
40 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
43 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
45 struct rcar_du_device *rcdu = rcrtc->group->dev;
47 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
48 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
51 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
53 struct rcar_du_device *rcdu = rcrtc->group->dev;
55 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
56 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
59 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
62 struct rcar_du_device *rcdu = rcrtc->group->dev;
63 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
65 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
68 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
72 ret = clk_prepare_enable(rcrtc->clock);
76 ret = rcar_du_group_get(rcrtc->group);
78 clk_disable_unprepare(rcrtc->clock);
83 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
85 rcar_du_group_put(rcrtc->group);
86 clk_disable_unprepare(rcrtc->clock);
89 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
91 const struct drm_display_mode *mode = &rcrtc->crtc.mode;
97 clk = clk_get_rate(rcrtc->clock);
98 div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
99 div = clamp(div, 1U, 64U) - 1;
101 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
102 ESCR_DCLKSEL_CLKS | div);
103 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
105 /* Signal polarities */
106 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
107 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
109 rcar_du_crtc_write(rcrtc, DSMR, value | DSMR_CSPM);
111 /* Display timings */
112 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
113 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
114 mode->hdisplay - 19);
115 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
116 mode->hsync_start - 1);
117 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
119 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
120 rcar_du_crtc_write(rcrtc, VDSR, (mode->vtotal / 2)
121 - (mode->vsync_end / 2) - 2);
122 rcar_du_crtc_write(rcrtc, VDER, (mode->vtotal / 2)
123 - (mode->vsync_end / 2)
124 + (mode->vdisplay / 2) - 2);
125 rcar_du_crtc_write(rcrtc, VSPR, (mode->vtotal / 2)
126 - (mode->vsync_end / 2)
127 + (mode->vsync_start / 2) - 1);
128 rcar_du_crtc_write(rcrtc, VCR, (mode->vtotal / 2) - 1);
130 rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal
131 - mode->vsync_end - 2);
132 rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end
133 + mode->vdisplay - 2);
134 rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end
135 + mode->vsync_start - 1);
136 rcar_du_crtc_write(rcrtc, VCR, mode->vtotal - 1);
139 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
140 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
143 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
144 enum rcar_du_output output)
146 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
147 struct rcar_du_device *rcdu = rcrtc->group->dev;
149 /* Store the route from the CRTC output to the DU output. The DU will be
150 * configured when starting the CRTC.
152 rcrtc->outputs |= BIT(output);
154 /* Store RGB routing to DPAD0 for R8A7790. */
155 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) &&
156 output == RCAR_DU_OUTPUT_DPAD0)
157 rcdu->dpad0_source = rcrtc->index;
160 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
162 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
163 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
164 unsigned int num_planes = 0;
165 unsigned int prio = 0;
170 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
171 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
174 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
177 /* Insert the plane in the sorted planes array. */
178 for (j = num_planes++; j > 0; --j) {
179 if (planes[j-1]->zpos <= plane->zpos)
181 planes[j] = planes[j-1];
185 prio += plane->format->planes * 4;
188 for (i = 0; i < num_planes; ++i) {
189 struct rcar_du_plane *plane = planes[i];
190 unsigned int index = plane->hwindex;
193 dspr |= (index + 1) << prio;
194 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
196 if (plane->format->planes == 2) {
197 index = (index + 1) % 8;
200 dspr |= (index + 1) << prio;
201 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
205 /* Select display timing and dot clock generator 2 for planes associated
206 * with superposition controller 2.
208 if (rcrtc->index % 2) {
209 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
211 /* The DPTSR register is updated when the display controller is
212 * stopped. We thus need to restart the DU. Once again, sorry
213 * for the flicker. One way to mitigate the issue would be to
214 * pre-associate planes with CRTCs (either with a fixed 4/4
215 * split, or through a module parameter). Flicker would then
216 * occur only if we need to break the pre-association.
218 if (value != dptsr) {
219 rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
220 if (rcrtc->group->used_crtcs)
221 rcar_du_group_restart(rcrtc->group);
225 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
229 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
231 struct drm_crtc *crtc = &rcrtc->crtc;
237 if (WARN_ON(rcrtc->plane->format == NULL))
240 /* Set display off and background to black */
241 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
242 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
244 /* Configure display timings and output routing */
245 rcar_du_crtc_set_display_timing(rcrtc);
246 rcar_du_group_set_routing(rcrtc->group);
248 mutex_lock(&rcrtc->group->planes.lock);
249 rcrtc->plane->enabled = true;
250 rcar_du_crtc_update_planes(crtc);
251 mutex_unlock(&rcrtc->group->planes.lock);
254 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
255 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
257 if (plane->crtc != crtc || !plane->enabled)
260 if (rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE)
261 plane->interlace_flag = true;
263 plane->interlace_flag = false;
264 rcar_du_plane_setup(plane);
267 /* Select master sync mode. This enables display operation in master
268 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
271 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
273 if (rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE) {
274 if (rcrtc->index == 1)
275 rcar_du_crtc_clr_set(rcrtc, DSYSR,
276 DSYSR_SCM_INT_VIDEO, DSYSR_SCM_INT_VIDEO);
278 rcrtc->group->interlace_grp = true;
280 if (rcrtc->index == 1)
281 rcar_du_crtc_clr_set(rcrtc, DSYSR,
282 DSYSR_SCM_INT_VIDEO, 0);
284 rcrtc->group->interlace_grp = false;
286 rcar_du_group_start_stop(rcrtc->group, true);
288 rcrtc->started = true;
291 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
293 struct drm_crtc *crtc = &rcrtc->crtc;
298 mutex_lock(&rcrtc->group->planes.lock);
299 rcrtc->plane->enabled = false;
300 rcar_du_crtc_update_planes(crtc);
301 mutex_unlock(&rcrtc->group->planes.lock);
303 /* Select switch sync mode. This stops display operation and configures
304 * the HSYNC and VSYNC signals as inputs.
306 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
308 if (rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE) {
309 if (rcrtc->index == 1)
310 rcar_du_crtc_clr_set(rcrtc,
311 DSYSR, DSYSR_SCM_INT_VIDEO, 0);
313 rcrtc->group->interlace_grp = false;
316 rcar_du_group_start_stop(rcrtc->group, false);
318 rcrtc->started = false;
321 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
323 rcar_du_crtc_stop(rcrtc);
324 rcar_du_crtc_put(rcrtc);
327 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
329 if (rcrtc->dpms != DRM_MODE_DPMS_ON)
332 rcar_du_crtc_get(rcrtc);
333 rcar_du_crtc_start(rcrtc);
336 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
338 struct drm_crtc *crtc = &rcrtc->crtc;
340 rcrtc->plane->pitch = crtc->fb->pitches[0];
342 rcar_du_plane_compute_base(rcrtc->plane, crtc->fb);
343 rcar_du_plane_update_base(rcrtc->plane);
346 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
348 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
350 if (rcrtc->dpms == mode)
353 if (mode == DRM_MODE_DPMS_ON) {
354 rcar_du_crtc_get(rcrtc);
355 rcar_du_crtc_start(rcrtc);
357 rcar_du_crtc_stop(rcrtc);
358 rcar_du_crtc_put(rcrtc);
364 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
365 const struct drm_display_mode *mode,
366 struct drm_display_mode *adjusted_mode)
368 /* TODO Fixup modes */
372 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
374 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
376 /* We need to access the hardware during mode set, acquire a reference
379 rcar_du_crtc_get(rcrtc);
381 /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
384 rcar_du_crtc_stop(rcrtc);
385 rcar_du_plane_release(rcrtc->plane);
387 rcrtc->dpms = DRM_MODE_DPMS_OFF;
390 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
391 struct drm_display_mode *mode,
392 struct drm_display_mode *adjusted_mode,
394 struct drm_framebuffer *old_fb)
396 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
397 struct rcar_du_device *rcdu = rcrtc->group->dev;
398 const struct rcar_du_format_info *format;
401 format = rcar_du_format_info(crtc->fb->pixel_format);
402 if (format == NULL) {
403 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
404 crtc->fb->pixel_format);
409 ret = rcar_du_plane_reserve(rcrtc->plane, format);
413 rcrtc->plane->format = format;
415 rcrtc->plane->src_x = x;
416 rcrtc->plane->src_y = y;
417 rcrtc->plane->width = mode->hdisplay;
418 rcrtc->plane->height = mode->vdisplay;
420 rcar_du_plane_compute_base(rcrtc->plane, crtc->fb);
427 /* There's no rollback/abort operation to clean up in case of error. We
428 * thus need to release the reference to the CRTC acquired in prepare()
431 rcar_du_crtc_put(rcrtc);
435 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
437 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
439 /* We're done, restart the CRTC and set the DPMS mode to on. The
440 * reference to the DU acquired at prepare() time will thus be released
441 * by the DPMS handler (possibly called by the disable() handler).
443 rcar_du_crtc_start(rcrtc);
444 rcrtc->dpms = DRM_MODE_DPMS_ON;
447 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
448 struct drm_framebuffer *old_fb)
450 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
452 rcrtc->plane->src_x = x;
453 rcrtc->plane->src_y = y;
455 rcar_du_crtc_update_base(rcrtc);
460 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
462 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
464 rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
465 rcar_du_plane_release(rcrtc->plane);
468 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
469 .dpms = rcar_du_crtc_dpms,
470 .mode_fixup = rcar_du_crtc_mode_fixup,
471 .prepare = rcar_du_crtc_mode_prepare,
472 .commit = rcar_du_crtc_mode_commit,
473 .mode_set = rcar_du_crtc_mode_set,
474 .mode_set_base = rcar_du_crtc_mode_set_base,
475 .disable = rcar_du_crtc_disable,
478 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
479 struct drm_file *file)
481 struct drm_pending_vblank_event *event;
482 struct drm_device *dev = rcrtc->crtc.dev;
485 /* Destroy the pending vertical blanking event associated with the
486 * pending page flip, if any, and disable vertical blanking interrupts.
488 spin_lock_irqsave(&dev->event_lock, flags);
489 event = rcrtc->event;
490 if (event && event->base.file_priv == file) {
492 event->base.destroy(&event->base);
493 drm_vblank_put(dev, rcrtc->index);
495 spin_unlock_irqrestore(&dev->event_lock, flags);
498 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
500 struct drm_pending_vblank_event *event;
501 struct drm_device *dev = rcrtc->crtc.dev;
504 spin_lock_irqsave(&dev->event_lock, flags);
505 event = rcrtc->event;
507 spin_unlock_irqrestore(&dev->event_lock, flags);
512 spin_lock_irqsave(&dev->event_lock, flags);
513 drm_send_vblank_event(dev, rcrtc->index, event);
514 spin_unlock_irqrestore(&dev->event_lock, flags);
516 drm_vblank_put(dev, rcrtc->index);
519 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
521 struct rcar_du_crtc *rcrtc = arg;
522 irqreturn_t ret = IRQ_NONE;
525 status = rcar_du_crtc_read(rcrtc, DSSR);
526 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
528 if (status & DSSR_FRM) {
529 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
530 rcar_du_crtc_finish_page_flip(rcrtc);
537 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
538 struct drm_framebuffer *fb,
539 struct drm_pending_vblank_event *event,
540 uint32_t page_flip_flags)
542 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
543 struct drm_device *dev = rcrtc->crtc.dev;
546 spin_lock_irqsave(&dev->event_lock, flags);
547 if (rcrtc->event != NULL) {
548 spin_unlock_irqrestore(&dev->event_lock, flags);
551 spin_unlock_irqrestore(&dev->event_lock, flags);
554 rcar_du_crtc_update_base(rcrtc);
557 event->pipe = rcrtc->index;
558 drm_vblank_get(dev, rcrtc->index);
559 spin_lock_irqsave(&dev->event_lock, flags);
560 rcrtc->event = event;
561 spin_unlock_irqrestore(&dev->event_lock, flags);
567 static const struct drm_crtc_funcs crtc_funcs = {
568 .destroy = drm_crtc_cleanup,
569 .set_config = drm_crtc_helper_set_config,
570 .page_flip = rcar_du_crtc_page_flip,
573 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
575 static const unsigned int mmio_offsets[] = {
576 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
579 struct rcar_du_device *rcdu = rgrp->dev;
580 struct platform_device *pdev = to_platform_device(rcdu->dev);
581 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
582 struct drm_crtc *crtc = &rcrtc->crtc;
583 unsigned int irqflags;
589 /* Get the CRTC clock. */
590 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
591 sprintf(clk_name, "du.%u", index);
597 rcrtc->clock = devm_clk_get(rcdu->dev, name);
598 if (IS_ERR(rcrtc->clock)) {
599 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
600 return PTR_ERR(rcrtc->clock);
604 rcrtc->mmio_offset = mmio_offsets[index];
605 rcrtc->index = index;
606 rcrtc->dpms = DRM_MODE_DPMS_OFF;
607 rcrtc->plane = &rgrp->planes.planes[index % 2];
609 rcrtc->plane->crtc = crtc;
611 ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
615 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
617 /* Register the interrupt handler. */
618 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
619 irq = platform_get_irq(pdev, index);
622 irq = platform_get_irq(pdev, 0);
623 irqflags = IRQF_SHARED;
627 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
631 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
632 dev_name(rcdu->dev), rcrtc);
635 "failed to register IRQ for CRTC %u\n", index);
642 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
645 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
646 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
648 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);