drivers/gpu/drm/radeon/r600_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "r600d.h"
  28 #include "r600_dpm.h"
  29 #include "atom.h"
  30
  31 const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  32 {
  33         R600_UTC_DFLT_00,
  34         R600_UTC_DFLT_01,
  35         R600_UTC_DFLT_02,
  36         R600_UTC_DFLT_03,
  37         R600_UTC_DFLT_04,
  38         R600_UTC_DFLT_05,
  39         R600_UTC_DFLT_06,
  40         R600_UTC_DFLT_07,
  41         R600_UTC_DFLT_08,
  42         R600_UTC_DFLT_09,
  43         R600_UTC_DFLT_10,
  44         R600_UTC_DFLT_11,
  45         R600_UTC_DFLT_12,
  46         R600_UTC_DFLT_13,
  47         R600_UTC_DFLT_14,
  48 };
  49
  50 const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
  51 {
  52         R600_DTC_DFLT_00,
  53         R600_DTC_DFLT_01,
  54         R600_DTC_DFLT_02,
  55         R600_DTC_DFLT_03,
  56         R600_DTC_DFLT_04,
  57         R600_DTC_DFLT_05,
  58         R600_DTC_DFLT_06,
  59         R600_DTC_DFLT_07,
  60         R600_DTC_DFLT_08,
  61         R600_DTC_DFLT_09,
  62         R600_DTC_DFLT_10,
  63         R600_DTC_DFLT_11,
  64         R600_DTC_DFLT_12,
  65         R600_DTC_DFLT_13,
  66         R600_DTC_DFLT_14,
  67 };
  68
  69 void r600_dpm_print_class_info(u32 class, u32 class2)
  70 {
  71         printk("\tui class: ");
  72         switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
  73         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
  74         default:
  75                 printk("none\n");
  76                 break;
  77         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
  78                 printk("battery\n");
  79                 break;
  80         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
  81                 printk("balanced\n");
  82                 break;
  83         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
  84                 printk("performance\n");
  85                 break;
  86         }
  87         printk("\tinternal class: ");
  88         if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
  89             (class2 == 0))
  90                 printk("none");
  91         else {
  92                 if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
  93                         printk("boot ");
  94                 if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
  95                         printk("thermal ");
  96                 if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
  97                         printk("limited_pwr ");
  98                 if (class & ATOM_PPLIB_CLASSIFICATION_REST)
  99                         printk("rest ");
 100                 if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
 101                         printk("forced ");
 102                 if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 103                         printk("3d_perf ");
 104                 if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
 105                         printk("ovrdrv ");
 106                 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
 107                         printk("uvd ");
 108                 if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
 109                         printk("3d_low ");
 110                 if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 111                         printk("acpi ");
 112                 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 113                         printk("uvd_hd2 ");
 114                 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 115                         printk("uvd_hd ");
 116                 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 117                         printk("uvd_sd ");
 118                 if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
 119                         printk("limited_pwr2 ");
 120                 if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 121                         printk("ulv ");
 122                 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 123                         printk("uvd_mvc ");
 124         }
 125         printk("\n");
 126 }
 127
 128 void r600_dpm_print_cap_info(u32 caps)
 129 {
 130         printk("\tcaps: ");
 131         if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
 132                 printk("single_disp ");
 133         if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
 134                 printk("video ");
 135         if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
 136                 printk("no_dc ");
 137         printk("\n");
 138 }
 139
 140 void r600_dpm_print_ps_status(struct radeon_device *rdev,
 141                               struct radeon_ps *rps)
 142 {
 143         printk("\tstatus: ");
 144         if (rps == rdev->pm.dpm.current_ps)
 145                 printk("c ");
 146         if (rps == rdev->pm.dpm.requested_ps)
 147                 printk("r ");
 148         if (rps == rdev->pm.dpm.boot_ps)
 149                 printk("b ");
 150         printk("\n");
 151 }
 152
 153 u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
 154 {
 155         struct drm_device *dev = rdev->ddev;
 156         struct drm_crtc *crtc;
 157         struct radeon_crtc *radeon_crtc;
 158         u32 line_time_us, vblank_lines;
 159         u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
 160
 161         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
 162                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 163                         radeon_crtc = to_radeon_crtc(crtc);
 164                         if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
 165                                 line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
 166                                         radeon_crtc->hw_mode.clock;
 167                                 vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
 168                                         radeon_crtc->hw_mode.crtc_vdisplay +
 169                                         (radeon_crtc->v_border * 2);
 170                                 vblank_time_us = vblank_lines * line_time_us;
 171                                 break;
 172                         }
 173                 }
 174         }
 175
 176         return vblank_time_us;
 177 }
 178
 179 u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
 180 {
 181         struct drm_device *dev = rdev->ddev;
 182         struct drm_crtc *crtc;
 183         struct radeon_crtc *radeon_crtc;
 184         u32 vrefresh = 0;
 185
 186         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
 187                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 188                         radeon_crtc = to_radeon_crtc(crtc);
 189                         if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
 190                                 vrefresh = radeon_crtc->hw_mode.vrefresh;
 191                                 break;
 192                         }
 193                 }
 194         }
 195         return vrefresh;
 196 }
 197
 198 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
 199                             u32 *p, u32 *u)
 200 {
 201         u32 b_c = 0;
 202         u32 i_c;
 203         u32 tmp;
 204
 205         i_c = (i * r_c) / 100;
 206         tmp = i_c >> p_b;
 207
 208         while (tmp) {
 209                 b_c++;
 210                 tmp >>= 1;
 211         }
 212
 213         *u = (b_c + 1) / 2;
 214         *p = i_c / (1 << (2 * (*u)));
 215 }
 216
 217 int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
 218 {
 219         u32 k, a, ah, al;
 220         u32 t1;
 221
 222         if ((fl == 0) || (fh == 0) || (fl > fh))
 223                 return -EINVAL;
 224
 225         k = (100 * fh) / fl;
 226         t1 = (t * (k - 100));
 227         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
 228         a = (a + 5) / 10;
 229         ah = ((a * t) + 5000) / 10000;
 230         al = a - ah;
 231
 232         *th = t - ah;
 233         *tl = t + al;
 234
 235         return 0;
 236 }
 237
 238 void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
 239 {
 240         int i;
 241
 242         if (enable) {
 243                 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
 244         } else {
 245                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
 246
 247                 WREG32(CG_RLC_REQ_AND_RSP, 0x2);
 248
 249                 for (i = 0; i < rdev->usec_timeout; i++) {
 250                         if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
 251                                 break;
 252                         udelay(1);
 253                 }
 254
 255                 WREG32(CG_RLC_REQ_AND_RSP, 0x0);
 256
 257                 WREG32(GRBM_PWR_CNTL, 0x1);
 258                 RREG32(GRBM_PWR_CNTL);
 259         }
 260 }
 261
 262 void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
 263 {
 264         if (enable)
 265                 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
 266         else
 267                 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
 268 }
 269
 270 void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
 271 {
 272         if (enable)
 273                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
 274         else
 275                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
 276 }
 277
 278 void r600_enable_acpi_pm(struct radeon_device *rdev)
 279 {
 280         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
 281 }
 282
 283 void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
 284 {
 285         if (enable)
 286                 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
 287         else
 288                 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
 289 }
 290
 291 bool r600_dynamicpm_enabled(struct radeon_device *rdev)
 292 {
 293         if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
 294                 return true;
 295         else
 296                 return false;
 297 }
 298
 299 void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
 300 {
 301         if (enable)
 302                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
 303         else
 304                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
 305 }
 306
 307 void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
 308 {
 309         if (enable)
 310                 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
 311         else
 312                 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
 313 }
 314
 315 void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
 316 {
 317         if (enable)
 318                 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
 319         else
 320                 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
 321 }
 322
 323 void r600_wait_for_spll_change(struct radeon_device *rdev)
 324 {
 325         int i;
 326
 327         for (i = 0; i < rdev->usec_timeout; i++) {
 328                 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
 329                         break;
 330                 udelay(1);
 331         }
 332 }
 333
 334 void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)
 335 {
 336         WREG32(CG_BSP, BSP(p) | BSU(u));
 337 }
 338
 339 void r600_set_at(struct radeon_device *rdev,
 340                  u32 l_to_m, u32 m_to_h,
 341                  u32 h_to_m, u32 m_to_l)
 342 {
 343         WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));
 344         WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));
 345 }
 346
 347 void r600_set_tc(struct radeon_device *rdev,
 348                  u32 index, u32 u_t, u32 d_t)
 349 {
 350         WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));
 351 }
 352
 353 void r600_select_td(struct radeon_device *rdev,
 354                     enum r600_td td)
 355 {
 356         if (td == R600_TD_AUTO)
 357                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
 358         else
 359                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
 360         if (td == R600_TD_UP)
 361                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
 362         if (td == R600_TD_DOWN)
 363                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
 364 }
 365
 366 void r600_set_vrc(struct radeon_device *rdev, u32 vrv)
 367 {
 368         WREG32(CG_FTV, vrv);
 369 }
 370
 371 void r600_set_tpu(struct radeon_device *rdev, u32 u)
 372 {
 373         WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);
 374 }
 375
 376 void r600_set_tpc(struct radeon_device *rdev, u32 c)
 377 {
 378         WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);
 379 }
 380
 381 void r600_set_sstu(struct radeon_device *rdev, u32 u)
 382 {
 383         WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);
 384 }
 385
 386 void r600_set_sst(struct radeon_device *rdev, u32 t)
 387 {
 388         WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);
 389 }
 390
 391 void r600_set_git(struct radeon_device *rdev, u32 t)
 392 {
 393         WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);
 394 }
 395
 396 void r600_set_fctu(struct radeon_device *rdev, u32 u)
 397 {
 398         WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);
 399 }
 400
 401 void r600_set_fct(struct radeon_device *rdev, u32 t)
 402 {
 403         WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);
 404 }
 405
 406 void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)
 407 {
 408         WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);
 409 }
 410
 411 void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)
 412 {
 413         WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);
 414 }
 415
 416 void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)
 417 {
 418         WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);
 419 }
 420
 421 void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)
 422 {
 423         WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);
 424 }
 425
 426 void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)
 427 {
 428         WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);
 429 }
 430
 431 void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)
 432 {
 433         WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);
 434 }
 435
 436 void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)
 437 {
 438         WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);
 439 }
 440
 441 void r600_engine_clock_entry_enable(struct radeon_device *rdev,
 442                                     u32 index, bool enable)
 443 {
 444         if (enable)
 445                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 446                          STEP_0_SPLL_ENTRY_VALID, ~STEP_0_SPLL_ENTRY_VALID);
 447         else
 448                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 449                          0, ~STEP_0_SPLL_ENTRY_VALID);
 450 }
 451
 452 void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
 453                                                    u32 index, bool enable)
 454 {
 455         if (enable)
 456                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 457                          STEP_0_SPLL_STEP_ENABLE, ~STEP_0_SPLL_STEP_ENABLE);
 458         else
 459                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 460                          0, ~STEP_0_SPLL_STEP_ENABLE);
 461 }
 462
 463 void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
 464                                                  u32 index, bool enable)
 465 {
 466         if (enable)
 467                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 468                          STEP_0_POST_DIV_EN, ~STEP_0_POST_DIV_EN);
 469         else
 470                 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
 471                          0, ~STEP_0_POST_DIV_EN);
 472 }
 473
 474 void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
 475                                               u32 index, u32 divider)
 476 {
 477         WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
 478                  STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
 479 }
 480
 481 void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
 482                                                    u32 index, u32 divider)
 483 {
 484         WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
 485                  STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
 486 }
 487
 488 void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
 489                                                   u32 index, u32 divider)
 490 {
 491         WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
 492                  STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
 493 }
 494
 495 void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
 496                                            u32 index, u32 step_time)
 497 {
 498         WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
 499                  STEP_0_SPLL_STEP_TIME(step_time), ~STEP_0_SPLL_STEP_TIME_MASK);
 500 }
 501
 502 void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)
 503 {
 504         WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);
 505 }
 506
 507 void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)
 508 {
 509         WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);
 510 }
 511
 512 void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)
 513 {
 514         WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);
 515 }
 516
 517 void r600_voltage_control_enable_pins(struct radeon_device *rdev,
 518                                       u64 mask)
 519 {
 520         WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);
 521         WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));
 522 }
 523
 524
 525 void r600_voltage_control_program_voltages(struct radeon_device *rdev,
 526                                            enum r600_power_level index, u64 pins)
 527 {
 528         u32 tmp, mask;
 529         u32 ix = 3 - (3 & index);
 530
 531         WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
 532
 533         mask = 7 << (3 * ix);
 534         tmp = RREG32(VID_UPPER_GPIO_CNTL);
 535         tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
 536         WREG32(VID_UPPER_GPIO_CNTL, tmp);
 537 }
 538
 539 void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
 540                                                     u64 mask)
 541 {
 542         u32 gpio;
 543
 544         gpio = RREG32(GPIOPAD_MASK);
 545         gpio &= ~mask;
 546         WREG32(GPIOPAD_MASK, gpio);
 547
 548         gpio = RREG32(GPIOPAD_EN);
 549         gpio &= ~mask;
 550         WREG32(GPIOPAD_EN, gpio);
 551
 552         gpio = RREG32(GPIOPAD_A);
 553         gpio &= ~mask;
 554         WREG32(GPIOPAD_A, gpio);
 555 }
 556
 557 void r600_power_level_enable(struct radeon_device *rdev,
 558                              enum r600_power_level index, bool enable)
 559 {
 560         u32 ix = 3 - (3 & index);
 561
 562         if (enable)
 563                 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
 564                          ~CTXSW_FREQ_STATE_ENABLE);
 565         else
 566                 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
 567                          ~CTXSW_FREQ_STATE_ENABLE);
 568 }
 569
 570 void r600_power_level_set_voltage_index(struct radeon_device *rdev,
 571                                         enum r600_power_level index, u32 voltage_index)
 572 {
 573         u32 ix = 3 - (3 & index);
 574
 575         WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
 576                  CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK);
 577 }
 578
 579 void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
 580                                           enum r600_power_level index, u32 mem_clock_index)
 581 {
 582         u32 ix = 3 - (3 & index);
 583
 584         WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
 585                  CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK);
 586 }
 587
 588 void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
 589                                           enum r600_power_level index, u32 eng_clock_index)
 590 {
 591         u32 ix = 3 - (3 & index);
 592
 593         WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
 594                  CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK);
 595 }
 596
 597 void r600_power_level_set_watermark_id(struct radeon_device *rdev,
 598                                        enum r600_power_level index,
 599                                        enum r600_display_watermark watermark_id)
 600 {
 601         u32 ix = 3 - (3 & index);
 602         u32 tmp = 0;
 603
 604         if (watermark_id == R600_DISPLAY_WATERMARK_HIGH)
 605                 tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
 606         WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
 607 }
 608
 609 void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
 610                                     enum r600_power_level index, bool compatible)
 611 {
 612         u32 ix = 3 - (3 & index);
 613         u32 tmp = 0;
 614
 615         if (compatible)
 616                 tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
 617         WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
 618 }
 619
 620 enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev)
 621 {
 622         u32 tmp;
 623
 624         tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
 625         tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
 626         return tmp;
 627 }
 628
 629 enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev)
 630 {
 631         u32 tmp;
 632
 633         tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
 634         tmp >>= TARGET_PROFILE_INDEX_SHIFT;
 635         return tmp;
 636 }
 637
 638 void r600_power_level_set_enter_index(struct radeon_device *rdev,
 639                                       enum r600_power_level index)
 640 {
 641         WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),
 642                  ~DYN_PWR_ENTER_INDEX_MASK);
 643 }
 644
 645 void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
 646                                        enum r600_power_level index)
 647 {
 648         int i;
 649
 650         for (i = 0; i < rdev->usec_timeout; i++) {
 651                 if (r600_power_level_get_target_index(rdev) != index)
 652                         break;
 653                 udelay(1);
 654         }
 655
 656         for (i = 0; i < rdev->usec_timeout; i++) {
 657                 if (r600_power_level_get_current_index(rdev) != index)
 658                         break;
 659                 udelay(1);
 660         }
 661 }
 662
 663 void r600_wait_for_power_level(struct radeon_device *rdev,
 664                                enum r600_power_level index)
 665 {
 666         int i;
 667
 668         for (i = 0; i < rdev->usec_timeout; i++) {
 669                 if (r600_power_level_get_target_index(rdev) == index)
 670                         break;
 671                 udelay(1);
 672         }
 673
 674         for (i = 0; i < rdev->usec_timeout; i++) {
 675                 if (r600_power_level_get_current_index(rdev) == index)
 676                         break;
 677                 udelay(1);
 678         }
 679 }
 680
 681 void r600_start_dpm(struct radeon_device *rdev)
 682 {
 683         r600_enable_sclk_control(rdev, false);
 684         r600_enable_mclk_control(rdev, false);
 685
 686         r600_dynamicpm_enable(rdev, true);
 687
 688         radeon_wait_for_vblank(rdev, 0);
 689         radeon_wait_for_vblank(rdev, 1);
 690
 691         r600_enable_spll_bypass(rdev, true);
 692         r600_wait_for_spll_change(rdev);
 693         r600_enable_spll_bypass(rdev, false);
 694         r600_wait_for_spll_change(rdev);
 695
 696         r600_enable_spll_bypass(rdev, true);
 697         r600_wait_for_spll_change(rdev);
 698         r600_enable_spll_bypass(rdev, false);
 699         r600_wait_for_spll_change(rdev);
 700
 701         r600_enable_sclk_control(rdev, true);
 702         r600_enable_mclk_control(rdev, true);
 703 }
 704
 705 void r600_stop_dpm(struct radeon_device *rdev)
 706 {
 707         r600_dynamicpm_enable(rdev, false);
 708 }
 709
 710 int r600_dpm_pre_set_power_state(struct radeon_device *rdev)
 711 {
 712         return 0;
 713 }
 714
 715 void r600_dpm_post_set_power_state(struct radeon_device *rdev)
 716 {
 717
 718 }
 719
 720 bool r600_is_uvd_state(u32 class, u32 class2)
 721 {
 722         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
 723                 return true;
 724         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 725                 return true;
 726         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 727                 return true;
 728         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 729                 return true;
 730         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 731                 return true;
 732         return false;
 733 }
 734
 735 static int r600_set_thermal_temperature_range(struct radeon_device *rdev,
 736                                               int min_temp, int max_temp)
 737 {
 738         int low_temp = 0 * 1000;
 739         int high_temp = 255 * 1000;
 740
 741         if (low_temp < min_temp)
 742                 low_temp = min_temp;
 743         if (high_temp > max_temp)
 744                 high_temp = max_temp;
 745         if (high_temp < low_temp) {
 746                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 747                 return -EINVAL;
 748         }
 749
 750         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
 751         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
 752         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
 753
 754         rdev->pm.dpm.thermal.min_temp = low_temp;
 755         rdev->pm.dpm.thermal.max_temp = high_temp;
 756
 757         return 0;
 758 }
 759
 760 bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
 761 {
 762         switch (sensor) {
 763         case THERMAL_TYPE_RV6XX:
 764         case THERMAL_TYPE_RV770:
 765         case THERMAL_TYPE_EVERGREEN:
 766         case THERMAL_TYPE_SUMO:
 767         case THERMAL_TYPE_NI:
 768         case THERMAL_TYPE_SI:
 769         case THERMAL_TYPE_CI:
 770         case THERMAL_TYPE_KV:
 771                 return true;
 772         case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
 773         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
 774                 return false; /* need special handling */
 775         case THERMAL_TYPE_NONE:
 776         case THERMAL_TYPE_EXTERNAL:
 777         case THERMAL_TYPE_EXTERNAL_GPIO:
 778         default:
 779                 return false;
 780         }
 781 }
 782
 783 int r600_dpm_late_enable(struct radeon_device *rdev)
 784 {
 785         int ret;
 786
 787         if (rdev->irq.installed &&
 788             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
 789                 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
 790                 if (ret)
 791                         return ret;
 792                 rdev->irq.dpm_thermal = true;
 793                 radeon_irq_set(rdev);
 794         }
 795
 796         return 0;
 797 }
 798
 799 union power_info {
 800         struct _ATOM_POWERPLAY_INFO info;
 801         struct _ATOM_POWERPLAY_INFO_V2 info_2;
 802         struct _ATOM_POWERPLAY_INFO_V3 info_3;
 803         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 804         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
 805         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
 806         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
 807         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
 808 };
 809
 810 union fan_info {
 811         struct _ATOM_PPLIB_FANTABLE fan;
 812         struct _ATOM_PPLIB_FANTABLE2 fan2;
 813 };
 814
 815 static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table,
 816                                             ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
 817 {
 818         u32 size = atom_table->ucNumEntries *
 819                 sizeof(struct radeon_clock_voltage_dependency_entry);
 820         int i;
 821         ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry;
 822
 823         radeon_table->entries = kzalloc(size, GFP_KERNEL);
 824         if (!radeon_table->entries)
 825                 return -ENOMEM;
 826
 827         entry = &atom_table->entries[0];
 828         for (i = 0; i < atom_table->ucNumEntries; i++) {
 829                 radeon_table->entries[i].clk = le16_to_cpu(entry->usClockLow) |
 830                         (entry->ucClockHigh << 16);
 831                 radeon_table->entries[i].v = le16_to_cpu(entry->usVoltage);
 832                 entry = (ATOM_PPLIB_Clock_Voltage_Dependency_Record *)
 833                         ((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));
 834         }
 835         radeon_table->count = atom_table->ucNumEntries;
 836
 837         return 0;
 838 }
 839
 840 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
 841 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
 842 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
 843 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
 844 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
 845 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
 846 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
 847
 848 int r600_parse_extended_power_table(struct radeon_device *rdev)
 849 {
 850         struct radeon_mode_info *mode_info = &rdev->mode_info;
 851         union power_info *power_info;
 852         union fan_info *fan_info;
 853         ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
 854         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 855         u16 data_offset;
 856         u8 frev, crev;
 857         int ret, i;
 858
 859         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
 860                                    &frev, &crev, &data_offset))
 861                 return -EINVAL;
 862         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 863
 864         /* fan table */
 865         if (le16_to_cpu(power_info->pplib.usTableSize) >=
 866             sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
 867                 if (power_info->pplib3.usFanTableOffset) {
 868                         fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset +
 869                                                       le16_to_cpu(power_info->pplib3.usFanTableOffset));
 870                         rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
 871                         rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
 872                         rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
 873                         rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
 874                         rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
 875                         rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
 876                         rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
 877                         if (fan_info->fan.ucFanTableFormat >= 2)
 878                                 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
 879                         else
 880                                 rdev->pm.dpm.fan.t_max = 10900;
 881                         rdev->pm.dpm.fan.cycle_delay = 100000;
 882                         rdev->pm.dpm.fan.ucode_fan_control = true;
 883                 }
 884         }
 885
 886         /* clock dependancy tables, shedding tables */
 887         if (le16_to_cpu(power_info->pplib.usTableSize) >=
 888             sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
 889                 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
 890                         dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
 891                                 (mode_info->atom_context->bios + data_offset +
 892                                  le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
 893                         ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
 894                                                                dep_table);
 895                         if (ret)
 896                                 return ret;
 897                 }
 898                 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
 899                         dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
 900                                 (mode_info->atom_context->bios + data_offset +
 901                                  le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
 902                         ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
 903                                                                dep_table);
 904                         if (ret) {
 905                                 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
 906                                 return ret;
 907                         }
 908                 }
 909                 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
 910                         dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
 911                                 (mode_info->atom_context->bios + data_offset +
 912                                  le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
 913                         ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
 914                                                                dep_table);
 915                         if (ret) {
 916                                 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
 917                                 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
 918                                 return ret;
 919                         }
 920                 }
 921                 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) {
 922                         dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
 923                                 (mode_info->atom_context->bios + data_offset +
 924                                  le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset));
 925                         ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
 926                                                                dep_table);
 927                         if (ret) {
 928                                 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
 929                                 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
 930                                 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
 931                                 return ret;
 932                         }
 933                 }
 934                 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
 935                         ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
 936                                 (ATOM_PPLIB_Clock_Voltage_Limit_Table *)
 937                                 (mode_info->atom_context->bios + data_offset +
 938                                  le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset));
 939                         if (clk_v->ucNumEntries) {
 940                                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
 941                                         le16_to_cpu(clk_v->entries[0].usSclkLow) |
 942                                         (clk_v->entries[0].ucSclkHigh << 16);
 943                                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
 944                                         le16_to_cpu(clk_v->entries[0].usMclkLow) |
 945                                         (clk_v->entries[0].ucMclkHigh << 16);
 946                                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
 947                                         le16_to_cpu(clk_v->entries[0].usVddc);
 948                                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
 949                                         le16_to_cpu(clk_v->entries[0].usVddci);
 950                         }
 951                 }
 952                 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
 953                         ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
 954                                 (ATOM_PPLIB_PhaseSheddingLimits_Table *)
 955                                 (mode_info->atom_context->bios + data_offset +
 956                                  le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
 957                         ATOM_PPLIB_PhaseSheddingLimits_Record *entry;
 958
 959                         rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
 960                                 kzalloc(psl->ucNumEntries *
 961                                         sizeof(struct radeon_phase_shedding_limits_entry),
 962                                         GFP_KERNEL);
 963                         if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
 964                                 r600_free_extended_power_table(rdev);
 965                                 return -ENOMEM;
 966                         }
 967
 968                         entry = &psl->entries[0];
 969                         for (i = 0; i < psl->ucNumEntries; i++) {
 970                                 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
 971                                         le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16);
 972                                 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
 973                                         le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16);
 974                                 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
 975                                         le16_to_cpu(entry->usVoltage);
 976                                 entry = (ATOM_PPLIB_PhaseSheddingLimits_Record *)
 977                                         ((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));
 978                         }
 979                         rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
 980                                 psl->ucNumEntries;
 981                 }
 982         }
 983
 984         /* cac data */
 985         if (le16_to_cpu(power_info->pplib.usTableSize) >=
 986             sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
 987                 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
 988                 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
 989                 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
 990                 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
 991                 if (rdev->pm.dpm.tdp_od_limit)
 992                         rdev->pm.dpm.power_control = true;
 993                 else
 994                         rdev->pm.dpm.power_control = false;
 995                 rdev->pm.dpm.tdp_adjustment = 0;
 996                 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
 997                 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
 998                 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
 999                 if (power_info->pplib5.usCACLeakageTableOffset) {
1000                         ATOM_PPLIB_CAC_Leakage_Table *cac_table =
1001                                 (ATOM_PPLIB_CAC_Leakage_Table *)
1002                                 (mode_info->atom_context->bios + data_offset +
1003                                  le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset));
1004                         ATOM_PPLIB_CAC_Leakage_Record *entry;
1005                         u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);
1006                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
1007                         if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1008                                 r600_free_extended_power_table(rdev);
1009                                 return -ENOMEM;
1010                         }
1011                         entry = &cac_table->entries[0];
1012                         for (i = 0; i < cac_table->ucNumEntries; i++) {
1013                                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1014                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
1015                                                 le16_to_cpu(entry->usVddc1);
1016                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
1017                                                 le16_to_cpu(entry->usVddc2);
1018                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
1019                                                 le16_to_cpu(entry->usVddc3);
1020                                 } else {
1021                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
1022                                                 le16_to_cpu(entry->usVddc);
1023                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
1024                                                 le32_to_cpu(entry->ulLeakageValue);
1025                                 }
1026                                 entry = (ATOM_PPLIB_CAC_Leakage_Record *)
1027                                         ((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));
1028                         }
1029                         rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
1030                 }
1031         }
1032
1033         /* ext tables */
1034         if (le16_to_cpu(power_info->pplib.usTableSize) >=
1035             sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
1036                 ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *)
1037                         (mode_info->atom_context->bios + data_offset +
1038                          le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
1039                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) &&
1040                         ext_hdr->usVCETableOffset) {
1041                         VCEClockInfoArray *array = (VCEClockInfoArray *)
1042                                 (mode_info->atom_context->bios + data_offset +
1043                                  le16_to_cpu(ext_hdr->usVCETableOffset) + 1);
1044                         ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =
1045                                 (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
1046                                 (mode_info->atom_context->bios + data_offset +
1047                                  le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
1048                                  1 + array->ucNumEntries * sizeof(VCEClockInfo));
1049                         ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *entry;
1050                         u32 size = limits->numEntries *
1051                                 sizeof(struct radeon_vce_clock_voltage_dependency_entry);
1052                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
1053                                 kzalloc(size, GFP_KERNEL);
1054                         if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
1055                                 r600_free_extended_power_table(rdev);
1056                                 return -ENOMEM;
1057                         }
1058                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
1059                                 limits->numEntries;
1060                         entry = &limits->entries[0];
1061                         for (i = 0; i < limits->numEntries; i++) {
1062                                 VCEClockInfo *vce_clk = (VCEClockInfo *)
1063                                         ((u8 *)&array->entries[0] +
1064                                          (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));
1065                                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
1066                                         le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
1067                                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
1068                                         le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
1069                                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
1070                                         le16_to_cpu(entry->usVoltage);
1071                                 entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *)
1072                                         ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
1073                         }
1074                 }
1075                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) &&
1076                         ext_hdr->usUVDTableOffset) {
1077                         UVDClockInfoArray *array = (UVDClockInfoArray *)
1078                                 (mode_info->atom_context->bios + data_offset +
1079                                  le16_to_cpu(ext_hdr->usUVDTableOffset) + 1);
1080                         ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =
1081                                 (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
1082                                 (mode_info->atom_context->bios + data_offset +
1083                                  le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 +
1084                                  1 + (array->ucNumEntries * sizeof (UVDClockInfo)));
1085                         ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *entry;
1086                         u32 size = limits->numEntries *
1087                                 sizeof(struct radeon_uvd_clock_voltage_dependency_entry);
1088                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
1089                                 kzalloc(size, GFP_KERNEL);
1090                         if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
1091                                 r600_free_extended_power_table(rdev);
1092                                 return -ENOMEM;
1093                         }
1094                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
1095                                 limits->numEntries;
1096                         entry = &limits->entries[0];
1097                         for (i = 0; i < limits->numEntries; i++) {
1098                                 UVDClockInfo *uvd_clk = (UVDClockInfo *)
1099                                         ((u8 *)&array->entries[0] +
1100                                          (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo)));
1101                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
1102                                         le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16);
1103                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
1104                                         le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16);
1105                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
1106                                         le16_to_cpu(entry->usVoltage);
1107                                 entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)
1108                                         ((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));
1109                         }
1110                 }
1111                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) &&
1112                         ext_hdr->usSAMUTableOffset) {
1113                         ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits =
1114                                 (ATOM_PPLIB_SAMClk_Voltage_Limit_Table *)
1115                                 (mode_info->atom_context->bios + data_offset +
1116                                  le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1);
1117                         ATOM_PPLIB_SAMClk_Voltage_Limit_Record *entry;
1118                         u32 size = limits->numEntries *
1119                                 sizeof(struct radeon_clock_voltage_dependency_entry);
1120                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
1121                                 kzalloc(size, GFP_KERNEL);
1122                         if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {
1123                                 r600_free_extended_power_table(rdev);
1124                                 return -ENOMEM;
1125                         }
1126                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
1127                                 limits->numEntries;
1128                         entry = &limits->entries[0];
1129                         for (i = 0; i < limits->numEntries; i++) {
1130                                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
1131                                         le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16);
1132                                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
1133                                         le16_to_cpu(entry->usVoltage);
1134                                 entry = (ATOM_PPLIB_SAMClk_Voltage_Limit_Record *)
1135                                         ((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));
1136                         }
1137                 }
1138                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
1139                     ext_hdr->usPPMTableOffset) {
1140                         ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
1141                                 (mode_info->atom_context->bios + data_offset +
1142                                  le16_to_cpu(ext_hdr->usPPMTableOffset));
1143                         rdev->pm.dpm.dyn_state.ppm_table =
1144                                 kzalloc(sizeof(struct radeon_ppm_table), GFP_KERNEL);
1145                         if (!rdev->pm.dpm.dyn_state.ppm_table) {
1146                                 r600_free_extended_power_table(rdev);
1147                                 return -ENOMEM;
1148                         }
1149                         rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
1150                         rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
1151                                 le16_to_cpu(ppm->usCpuCoreNumber);
1152                         rdev->pm.dpm.dyn_state.ppm_table->platform_tdp =
1153                                 le32_to_cpu(ppm->ulPlatformTDP);
1154                         rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
1155                                 le32_to_cpu(ppm->ulSmallACPlatformTDP);
1156                         rdev->pm.dpm.dyn_state.ppm_table->platform_tdc =
1157                                 le32_to_cpu(ppm->ulPlatformTDC);
1158                         rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
1159                                 le32_to_cpu(ppm->ulSmallACPlatformTDC);
1160                         rdev->pm.dpm.dyn_state.ppm_table->apu_tdp =
1161                                 le32_to_cpu(ppm->ulApuTDP);
1162                         rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
1163                                 le32_to_cpu(ppm->ulDGpuTDP);
1164                         rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
1165                                 le32_to_cpu(ppm->ulDGpuUlvPower);
1166                         rdev->pm.dpm.dyn_state.ppm_table->tj_max =
1167                                 le32_to_cpu(ppm->ulTjmax);
1168                 }
1169                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) &&
1170                         ext_hdr->usACPTableOffset) {
1171                         ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits =
1172                                 (ATOM_PPLIB_ACPClk_Voltage_Limit_Table *)
1173                                 (mode_info->atom_context->bios + data_offset +
1174                                  le16_to_cpu(ext_hdr->usACPTableOffset) + 1);
1175                         ATOM_PPLIB_ACPClk_Voltage_Limit_Record *entry;
1176                         u32 size = limits->numEntries *
1177                                 sizeof(struct radeon_clock_voltage_dependency_entry);
1178                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
1179                                 kzalloc(size, GFP_KERNEL);
1180                         if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {
1181                                 r600_free_extended_power_table(rdev);
1182                                 return -ENOMEM;
1183                         }
1184                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
1185                                 limits->numEntries;
1186                         entry = &limits->entries[0];
1187                         for (i = 0; i < limits->numEntries; i++) {
1188                                 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
1189                                         le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16);
1190                                 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
1191                                         le16_to_cpu(entry->usVoltage);
1192                                 entry = (ATOM_PPLIB_ACPClk_Voltage_Limit_Record *)
1193                                         ((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));
1194                         }
1195                 }
1196                 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) &&
1197                         ext_hdr->usPowerTuneTableOffset) {
1198                         u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +
1199                                          le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1200                         ATOM_PowerTune_Table *pt;
1201                         rdev->pm.dpm.dyn_state.cac_tdp_table =
1202                                 kzalloc(sizeof(struct radeon_cac_tdp_table), GFP_KERNEL);
1203                         if (!rdev->pm.dpm.dyn_state.cac_tdp_table) {
1204                                 r600_free_extended_power_table(rdev);
1205                                 return -ENOMEM;
1206                         }
1207                         if (rev > 0) {
1208                                 ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)
1209                                         (mode_info->atom_context->bios + data_offset +
1210                                          le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1211                                 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
1212                                         ppt->usMaximumPowerDeliveryLimit;
1213                                 pt = &ppt->power_tune_table;
1214                         } else {
1215                                 ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
1216                                         (mode_info->atom_context->bios + data_offset +
1217                                          le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1218                                 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
1219                                 pt = &ppt->power_tune_table;
1220                         }
1221                         rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
1222                         rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
1223                                 le16_to_cpu(pt->usConfigurableTDP);
1224                         rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
1225                         rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
1226                                 le16_to_cpu(pt->usBatteryPowerLimit);
1227                         rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
1228                                 le16_to_cpu(pt->usSmallPowerLimit);
1229                         rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
1230                                 le16_to_cpu(pt->usLowCACLeakage);
1231                         rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
1232                                 le16_to_cpu(pt->usHighCACLeakage);
1233                 }
1234         }
1235
1236         return 0;
1237 }
1238
1239 void r600_free_extended_power_table(struct radeon_device *rdev)
1240 {
1241         struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state;
1242
1243         kfree(dyn_state->vddc_dependency_on_sclk.entries);
1244         kfree(dyn_state->vddci_dependency_on_mclk.entries);
1245         kfree(dyn_state->vddc_dependency_on_mclk.entries);
1246         kfree(dyn_state->mvdd_dependency_on_mclk.entries);
1247         kfree(dyn_state->cac_leakage_table.entries);
1248         kfree(dyn_state->phase_shedding_limits_table.entries);
1249         kfree(dyn_state->ppm_table);
1250         kfree(dyn_state->cac_tdp_table);
1251         kfree(dyn_state->vce_clock_voltage_dependency_table.entries);
1252         kfree(dyn_state->uvd_clock_voltage_dependency_table.entries);
1253         kfree(dyn_state->samu_clock_voltage_dependency_table.entries);
1254         kfree(dyn_state->acp_clock_voltage_dependency_table.entries);
1255 }
1256
1257 enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
1258                                                u32 sys_mask,
1259                                                enum radeon_pcie_gen asic_gen,
1260                                                enum radeon_pcie_gen default_gen)
1261 {
1262         switch (asic_gen) {
1263         case RADEON_PCIE_GEN1:
1264                 return RADEON_PCIE_GEN1;
1265         case RADEON_PCIE_GEN2:
1266                 return RADEON_PCIE_GEN2;
1267         case RADEON_PCIE_GEN3:
1268                 return RADEON_PCIE_GEN3;
1269         default:
1270                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
1271                         return RADEON_PCIE_GEN3;
1272                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
1273                         return RADEON_PCIE_GEN2;
1274                 else
1275                         return RADEON_PCIE_GEN1;
1276         }
1277         return RADEON_PCIE_GEN1;
1278 }
1279
1280 u16 r600_get_pcie_lane_support(struct radeon_device *rdev,
1281                                u16 asic_lanes,
1282                                u16 default_lanes)
1283 {
1284         switch (asic_lanes) {
1285         case 0:
1286         default:
1287                 return default_lanes;
1288         case 1:
1289                 return 1;
1290         case 2:
1291                 return 2;
1292         case 4:
1293                 return 4;
1294         case 8:
1295                 return 8;
1296         case 12:
1297                 return 12;
1298         case 16:
1299                 return 16;
1300         }
1301 }
1302
1303 u8 r600_encode_pci_lane_width(u32 lanes)
1304 {
1305         u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 };
1306
1307         if (lanes > 16)
1308                 return 0;
1309
1310         return encoded_lanes[lanes];
1311 }