2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 static __must_check int
47 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
50 bool map_and_fenceable,
52 static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file);
57 static void i915_gem_write_fence(struct drm_device *dev, int reg,
58 struct drm_i915_gem_object *obj);
59 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
60 struct drm_i915_fence_reg *fence,
63 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
66 struct shrink_control *sc);
67 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
68 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
69 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
335 /* Per-page copy function for the shmem pread fastpath.
336 * Flushes invalid cachelines before reading the target if
337 * needs_clflush is set. */
339 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
340 char __user *user_data,
341 bool page_do_bit17_swizzling, bool needs_clflush)
346 if (unlikely(page_do_bit17_swizzling))
349 vaddr = kmap_atomic(page);
351 drm_clflush_virt_range(vaddr + shmem_page_offset,
353 ret = __copy_to_user_inatomic(user_data,
354 vaddr + shmem_page_offset,
356 kunmap_atomic(vaddr);
358 return ret ? -EFAULT : 0;
362 shmem_clflush_swizzled_range(char *addr, unsigned long length,
365 if (unlikely(swizzled)) {
366 unsigned long start = (unsigned long) addr;
367 unsigned long end = (unsigned long) addr + length;
369 /* For swizzling simply ensure that we always flush both
370 * channels. Lame, but simple and it works. Swizzled
371 * pwrite/pread is far from a hotpath - current userspace
372 * doesn't use it at all. */
373 start = round_down(start, 128);
374 end = round_up(end, 128);
376 drm_clflush_virt_range((void *)start, end - start);
378 drm_clflush_virt_range(addr, length);
383 /* Only difference to the fast-path function is that this can handle bit17
384 * and uses non-atomic copy and kmap functions. */
386 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
387 char __user *user_data,
388 bool page_do_bit17_swizzling, bool needs_clflush)
395 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
397 page_do_bit17_swizzling);
399 if (page_do_bit17_swizzling)
400 ret = __copy_to_user_swizzled(user_data,
401 vaddr, shmem_page_offset,
404 ret = __copy_to_user(user_data,
405 vaddr + shmem_page_offset,
409 return ret ? - EFAULT : 0;
413 i915_gem_shmem_pread(struct drm_device *dev,
414 struct drm_i915_gem_object *obj,
415 struct drm_i915_gem_pread *args,
416 struct drm_file *file)
418 char __user *user_data;
421 int shmem_page_offset, page_length, ret = 0;
422 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
424 int needs_clflush = 0;
425 struct sg_page_iter sg_iter;
427 user_data = to_user_ptr(args->data_ptr);
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
438 ret = i915_gem_object_wait_rendering(obj, true);
443 ret = i915_gem_object_get_pages(obj);
447 i915_gem_object_pin_pages(obj);
449 offset = args->offset;
451 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
452 offset >> PAGE_SHIFT) {
453 struct page *page = sg_page_iter_page(&sg_iter);
458 /* Operation in this page
460 * shmem_page_offset = offset within page in shmem file
461 * page_length = bytes to copy for this page
463 shmem_page_offset = offset_in_page(offset);
464 page_length = remain;
465 if ((shmem_page_offset + page_length) > PAGE_SIZE)
466 page_length = PAGE_SIZE - shmem_page_offset;
468 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
469 (page_to_phys(page) & (1 << 17)) != 0;
471 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
472 user_data, page_do_bit17_swizzling,
477 mutex_unlock(&dev->struct_mutex);
479 if (likely(!i915_prefault_disable) && !prefaulted) {
480 ret = fault_in_multipages_writeable(user_data, remain);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
490 user_data, page_do_bit17_swizzling,
493 mutex_lock(&dev->struct_mutex);
496 mark_page_accessed(page);
501 remain -= page_length;
502 user_data += page_length;
503 offset += page_length;
507 i915_gem_object_unpin_pages(obj);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
528 if (!access_ok(VERIFY_WRITE,
529 to_user_ptr(args->data_ptr),
533 ret = i915_mutex_lock_interruptible(dev);
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj->base.filp) {
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
563 drm_gem_object_unreference(&obj->base);
565 mutex_unlock(&dev->struct_mutex);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
579 void __iomem *vaddr_atomic;
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
588 io_mapping_unmap_atomic(vaddr_atomic);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
616 ret = i915_gem_object_put_fence(obj);
620 user_data = to_user_ptr(args->data_ptr);
623 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv->gtt.mappable, page_base,
643 page_offset, user_data, page_length)) {
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
654 i915_gem_object_unpin(obj);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
673 if (unlikely(page_do_bit17_swizzling))
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 kunmap_atomic(vaddr);
688 return ret ? -EFAULT : 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
713 ret = __copy_from_user(vaddr + shmem_page_offset,
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
719 page_do_bit17_swizzling);
722 return ret ? -EFAULT : 0;
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
733 char __user *user_data;
734 int shmem_page_offset, page_length, ret = 0;
735 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
736 int hit_slowpath = 0;
737 int needs_clflush_after = 0;
738 int needs_clflush_before = 0;
739 struct sg_page_iter sg_iter;
741 user_data = to_user_ptr(args->data_ptr);
744 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
747 /* If we're not in the cpu write domain, set ourself into the gtt
748 * write domain and manually flush cachelines (if required). This
749 * optimizes for the case when the gpu will use the data
750 * right away and we therefore have to clflush anyway. */
751 needs_clflush_after = cpu_write_needs_clflush(obj);
752 ret = i915_gem_object_wait_rendering(obj, false);
756 /* Same trick applies to invalidate partially written cachelines read
758 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
759 needs_clflush_before =
760 !cpu_cache_is_coherent(dev, obj->cache_level);
762 ret = i915_gem_object_get_pages(obj);
766 i915_gem_object_pin_pages(obj);
768 offset = args->offset;
771 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
772 offset >> PAGE_SHIFT) {
773 struct page *page = sg_page_iter_page(&sg_iter);
774 int partial_cacheline_write;
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset = offset_in_page(offset);
786 page_length = remain;
787 if ((shmem_page_offset + page_length) > PAGE_SIZE)
788 page_length = PAGE_SIZE - shmem_page_offset;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write = needs_clflush_before &&
794 ((shmem_page_offset | page_length)
795 & (boot_cpu_data.x86_clflush_size - 1));
797 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
798 (page_to_phys(page) & (1 << 17)) != 0;
800 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
801 user_data, page_do_bit17_swizzling,
802 partial_cacheline_write,
803 needs_clflush_after);
808 mutex_unlock(&dev->struct_mutex);
809 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
814 mutex_lock(&dev->struct_mutex);
817 set_page_dirty(page);
818 mark_page_accessed(page);
823 remain -= page_length;
824 user_data += page_length;
825 offset += page_length;
829 i915_gem_object_unpin_pages(obj);
833 * Fixup: Flush cpu caches in case we didn't flush the dirty
834 * cachelines in-line while writing and the object moved
835 * out of the cpu write domain while we've dropped the lock.
837 if (!needs_clflush_after &&
838 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
839 if (i915_gem_clflush_object(obj, obj->pin_display))
840 i915_gem_chipset_flush(dev);
844 if (needs_clflush_after)
845 i915_gem_chipset_flush(dev);
851 * Writes data to the object referenced by handle.
853 * On error, the contents of the buffer that were to be modified are undefined.
856 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file)
859 struct drm_i915_gem_pwrite *args = data;
860 struct drm_i915_gem_object *obj;
866 if (!access_ok(VERIFY_READ,
867 to_user_ptr(args->data_ptr),
871 if (likely(!i915_prefault_disable)) {
872 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
878 ret = i915_mutex_lock_interruptible(dev);
882 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
883 if (&obj->base == NULL) {
888 /* Bounds check destination. */
889 if (args->offset > obj->base.size ||
890 args->size > obj->base.size - args->offset) {
895 /* prime objects have no backing filp to GEM pread/pwrite
898 if (!obj->base.filp) {
903 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
906 /* We can only do the GTT pwrite on untiled buffers, as otherwise
907 * it would end up going through the fenced access, and we'll get
908 * different detiling behavior between reading and writing.
909 * pread/pwrite currently are reading and writing from the CPU
910 * perspective, requiring manual detiling by the client.
913 ret = i915_gem_phys_pwrite(dev, obj, args, file);
917 if (obj->tiling_mode == I915_TILING_NONE &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
919 cpu_write_needs_clflush(obj)) {
920 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
921 /* Note that the gtt paths might fail with non-page-backed user
922 * pointers (e.g. gtt mappings when moving data between
923 * textures). Fallback to the shmem path in that case. */
926 if (ret == -EFAULT || ret == -ENOSPC)
927 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
930 drm_gem_object_unreference(&obj->base);
932 mutex_unlock(&dev->struct_mutex);
937 i915_gem_check_wedge(struct i915_gpu_error *error,
940 if (i915_reset_in_progress(error)) {
941 /* Non-interruptible callers can't handle -EAGAIN, hence return
942 * -EIO unconditionally for these. */
946 /* Recovery complete, but the reset failed ... */
947 if (i915_terminally_wedged(error))
957 * Compare seqno against outstanding lazy request. Emit a request if they are
961 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
965 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
968 if (seqno == ring->outstanding_lazy_seqno)
969 ret = i915_add_request(ring, NULL);
974 static void fake_irq(unsigned long data)
976 wake_up_process((struct task_struct *)data);
979 static bool missed_irq(struct drm_i915_private *dev_priv,
980 struct intel_ring_buffer *ring)
982 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
985 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
987 if (file_priv == NULL)
990 return !atomic_xchg(&file_priv->rps_wait_boost, true);
994 * __wait_seqno - wait until execution of seqno has finished
995 * @ring: the ring expected to report seqno
997 * @reset_counter: reset sequence associated with the given seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Note: It is of utmost importance that the passed in seqno and reset_counter
1002 * values have been read by the caller in an smp safe manner. Where read-side
1003 * locks are involved, it is sufficient to read the reset_counter before
1004 * unlocking the lock that protects the seqno. For lockless tricks, the
1005 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1008 * Returns 0 if the seqno was found within the alloted time. Else returns the
1009 * errno with remaining time filled in timeout argument.
1011 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1012 unsigned reset_counter,
1014 struct timespec *timeout,
1015 struct drm_i915_file_private *file_priv)
1017 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1018 const bool irq_test_in_progress =
1019 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1020 struct timespec before, now;
1022 unsigned long timeout_expire;
1025 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1027 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1030 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1032 if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
1033 gen6_rps_boost(dev_priv);
1035 mod_delayed_work(dev_priv->wq,
1036 &file_priv->mm.idle_work,
1037 msecs_to_jiffies(100));
1040 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1043 /* Record current time in case interrupted by signal, or wedged */
1044 trace_i915_gem_request_wait_begin(ring, seqno);
1045 getrawmonotonic(&before);
1047 struct timer_list timer;
1049 prepare_to_wait(&ring->irq_queue, &wait,
1050 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1052 /* We need to check whether any gpu reset happened in between
1053 * the caller grabbing the seqno and now ... */
1054 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1055 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1056 * is truely gone. */
1057 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1063 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1068 if (interruptible && signal_pending(current)) {
1073 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1078 timer.function = NULL;
1079 if (timeout || missed_irq(dev_priv, ring)) {
1080 unsigned long expire;
1082 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1083 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1084 mod_timer(&timer, expire);
1089 if (timer.function) {
1090 del_singleshot_timer_sync(&timer);
1091 destroy_timer_on_stack(&timer);
1094 getrawmonotonic(&now);
1095 trace_i915_gem_request_wait_end(ring, seqno);
1097 if (!irq_test_in_progress)
1098 ring->irq_put(ring);
1100 finish_wait(&ring->irq_queue, &wait);
1103 struct timespec sleep_time = timespec_sub(now, before);
1104 *timeout = timespec_sub(*timeout, sleep_time);
1105 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1106 set_normalized_timespec(timeout, 0, 0);
1113 * Waits for a sequence number to be signaled, and cleans up the
1114 * request and object lists appropriately for that event.
1117 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1119 struct drm_device *dev = ring->dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 bool interruptible = dev_priv->mm.interruptible;
1124 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1127 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1131 ret = i915_gem_check_olr(ring, seqno);
1135 return __wait_seqno(ring, seqno,
1136 atomic_read(&dev_priv->gpu_error.reset_counter),
1137 interruptible, NULL, NULL);
1141 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1142 struct intel_ring_buffer *ring)
1144 i915_gem_retire_requests_ring(ring);
1146 /* Manually manage the write flush as we may have not yet
1147 * retired the buffer.
1149 * Note that the last_write_seqno is always the earlier of
1150 * the two (read/write) seqno, so if we haved successfully waited,
1151 * we know we have passed the last write.
1153 obj->last_write_seqno = 0;
1154 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1160 * Ensures that all rendering to the object has completed and the object is
1161 * safe to unbind from the GTT or access from the CPU.
1163 static __must_check int
1164 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1167 struct intel_ring_buffer *ring = obj->ring;
1171 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1175 ret = i915_wait_seqno(ring, seqno);
1179 return i915_gem_object_wait_rendering__tail(obj, ring);
1182 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1183 * as the object state may change during this call.
1185 static __must_check int
1186 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1187 struct drm_file *file,
1190 struct drm_device *dev = obj->base.dev;
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 struct intel_ring_buffer *ring = obj->ring;
1193 unsigned reset_counter;
1197 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1198 BUG_ON(!dev_priv->mm.interruptible);
1200 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1204 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1208 ret = i915_gem_check_olr(ring, seqno);
1212 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1213 mutex_unlock(&dev->struct_mutex);
1214 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv);
1215 mutex_lock(&dev->struct_mutex);
1219 return i915_gem_object_wait_rendering__tail(obj, ring);
1223 * Called when user space prepares to use an object with the CPU, either
1224 * through the mmap ioctl's mapping or a GTT mapping.
1227 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *file)
1230 struct drm_i915_gem_set_domain *args = data;
1231 struct drm_i915_gem_object *obj;
1232 uint32_t read_domains = args->read_domains;
1233 uint32_t write_domain = args->write_domain;
1236 /* Only handle setting domains to types used by the CPU. */
1237 if (write_domain & I915_GEM_GPU_DOMAINS)
1240 if (read_domains & I915_GEM_GPU_DOMAINS)
1243 /* Having something in the write domain implies it's in the read
1244 * domain, and only that read domain. Enforce that in the request.
1246 if (write_domain != 0 && read_domains != write_domain)
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Try to flush the object off the GPU without holding the lock.
1260 * We will repeat the flush holding the lock in the normal manner
1261 * to catch cases where we are gazumped.
1263 ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain);
1267 if (read_domains & I915_GEM_DOMAIN_GTT) {
1268 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1270 /* Silently promote "you're not bound, there was nothing to do"
1271 * to success, since the client was just asking us to
1272 * make sure everything was done.
1277 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1281 drm_gem_object_unreference(&obj->base);
1283 mutex_unlock(&dev->struct_mutex);
1288 * Called when user space has done writes to this buffer
1291 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1292 struct drm_file *file)
1294 struct drm_i915_gem_sw_finish *args = data;
1295 struct drm_i915_gem_object *obj;
1298 ret = i915_mutex_lock_interruptible(dev);
1302 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1303 if (&obj->base == NULL) {
1308 /* Pinned buffers may be scanout, so flush the cache */
1309 if (obj->pin_display)
1310 i915_gem_object_flush_cpu_write_domain(obj, true);
1312 drm_gem_object_unreference(&obj->base);
1314 mutex_unlock(&dev->struct_mutex);
1319 * Maps the contents of an object, returning the address it is mapped
1322 * While the mapping holds a reference on the contents of the object, it doesn't
1323 * imply a ref on the object itself.
1326 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *file)
1329 struct drm_i915_gem_mmap *args = data;
1330 struct drm_gem_object *obj;
1333 obj = drm_gem_object_lookup(dev, file, args->handle);
1337 /* prime objects have no backing filp to GEM mmap
1341 drm_gem_object_unreference_unlocked(obj);
1345 addr = vm_mmap(obj->filp, 0, args->size,
1346 PROT_READ | PROT_WRITE, MAP_SHARED,
1348 drm_gem_object_unreference_unlocked(obj);
1349 if (IS_ERR((void *)addr))
1352 args->addr_ptr = (uint64_t) addr;
1358 * i915_gem_fault - fault a page into the GTT
1359 * vma: VMA in question
1362 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1363 * from userspace. The fault handler takes care of binding the object to
1364 * the GTT (if needed), allocating and programming a fence register (again,
1365 * only if needed based on whether the old reg is still valid or the object
1366 * is tiled) and inserting a new PTE into the faulting process.
1368 * Note that the faulting process may involve evicting existing objects
1369 * from the GTT and/or fence registers to make room. So performance may
1370 * suffer if the GTT working set is large or there are few fence registers
1373 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1375 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1376 struct drm_device *dev = obj->base.dev;
1377 drm_i915_private_t *dev_priv = dev->dev_private;
1378 pgoff_t page_offset;
1381 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1383 intel_runtime_pm_get(dev_priv);
1385 /* We don't use vmf->pgoff since that has the fake offset */
1386 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1389 ret = i915_mutex_lock_interruptible(dev);
1393 trace_i915_gem_object_fault(obj, page_offset, true, write);
1395 /* Access to snoopable pages through the GTT is incoherent. */
1396 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1401 /* Now bind it into the GTT if needed */
1402 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1406 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1410 ret = i915_gem_object_get_fence(obj);
1414 obj->fault_mappable = true;
1416 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1420 /* Finally, remap it using the new GTT offset */
1421 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1423 i915_gem_object_unpin(obj);
1425 mutex_unlock(&dev->struct_mutex);
1430 * We eat errors when the gpu is terminally wedged to avoid
1431 * userspace unduly crashing (gl has no provisions for mmaps to
1432 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1433 * and so needs to be reported.
1435 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1436 ret = VM_FAULT_SIGBUS;
1441 * EAGAIN means the gpu is hung and we'll wait for the error
1442 * handler to reset everything when re-faulting in
1443 * i915_mutex_lock_interruptible.
1450 * EBUSY is ok: this just means that another thread
1451 * already did the job.
1453 ret = VM_FAULT_NOPAGE;
1459 ret = VM_FAULT_SIGBUS;
1462 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1463 ret = VM_FAULT_SIGBUS;
1467 intel_runtime_pm_put(dev_priv);
1471 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1473 struct i915_vma *vma;
1476 * Only the global gtt is relevant for gtt memory mappings, so restrict
1477 * list traversal to objects bound into the global address space. Note
1478 * that the active list should be empty, but better safe than sorry.
1480 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1481 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1482 i915_gem_release_mmap(vma->obj);
1483 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1484 i915_gem_release_mmap(vma->obj);
1488 * i915_gem_release_mmap - remove physical page mappings
1489 * @obj: obj in question
1491 * Preserve the reservation of the mmapping with the DRM core code, but
1492 * relinquish ownership of the pages back to the system.
1494 * It is vital that we remove the page mapping if we have mapped a tiled
1495 * object through the GTT and then lose the fence register due to
1496 * resource pressure. Similarly if the object has been moved out of the
1497 * aperture, than pages mapped into userspace must be revoked. Removing the
1498 * mapping will then trigger a page fault on the next user access, allowing
1499 * fixup by i915_gem_fault().
1502 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1504 if (!obj->fault_mappable)
1507 drm_vma_node_unmap(&obj->base.vma_node,
1508 obj->base.dev->anon_inode->i_mapping);
1509 obj->fault_mappable = false;
1513 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1517 if (INTEL_INFO(dev)->gen >= 4 ||
1518 tiling_mode == I915_TILING_NONE)
1521 /* Previous chips need a power-of-two fence region when tiling */
1522 if (INTEL_INFO(dev)->gen == 3)
1523 gtt_size = 1024*1024;
1525 gtt_size = 512*1024;
1527 while (gtt_size < size)
1534 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1535 * @obj: object to check
1537 * Return the required GTT alignment for an object, taking into account
1538 * potential fence register mapping.
1541 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1542 int tiling_mode, bool fenced)
1545 * Minimum alignment is 4k (GTT page size), but might be greater
1546 * if a fence register is needed for the object.
1548 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1549 tiling_mode == I915_TILING_NONE)
1553 * Previous chips need to be aligned to the size of the smallest
1554 * fence register that can contain the object.
1556 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1559 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1561 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1564 if (drm_vma_node_has_offset(&obj->base.vma_node))
1567 dev_priv->mm.shrinker_no_lock_stealing = true;
1569 ret = drm_gem_create_mmap_offset(&obj->base);
1573 /* Badly fragmented mmap space? The only way we can recover
1574 * space is by destroying unwanted objects. We can't randomly release
1575 * mmap_offsets as userspace expects them to be persistent for the
1576 * lifetime of the objects. The closest we can is to release the
1577 * offsets on purgeable objects by truncating it and marking it purged,
1578 * which prevents userspace from ever using that object again.
1580 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1581 ret = drm_gem_create_mmap_offset(&obj->base);
1585 i915_gem_shrink_all(dev_priv);
1586 ret = drm_gem_create_mmap_offset(&obj->base);
1588 dev_priv->mm.shrinker_no_lock_stealing = false;
1593 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1595 drm_gem_free_mmap_offset(&obj->base);
1599 i915_gem_mmap_gtt(struct drm_file *file,
1600 struct drm_device *dev,
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_i915_gem_object *obj;
1608 ret = i915_mutex_lock_interruptible(dev);
1612 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1613 if (&obj->base == NULL) {
1618 if (obj->base.size > dev_priv->gtt.mappable_end) {
1623 if (obj->madv != I915_MADV_WILLNEED) {
1624 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1629 ret = i915_gem_object_create_mmap_offset(obj);
1633 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1636 drm_gem_object_unreference(&obj->base);
1638 mutex_unlock(&dev->struct_mutex);
1643 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1645 * @data: GTT mapping ioctl data
1646 * @file: GEM object info
1648 * Simply returns the fake offset to userspace so it can mmap it.
1649 * The mmap call will end up in drm_gem_mmap(), which will set things
1650 * up so we can get faults in the handler above.
1652 * The fault handler will take care of binding the object into the GTT
1653 * (since it may have been evicted to make room for something), allocating
1654 * a fence register, and mapping the appropriate aperture address into
1658 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1659 struct drm_file *file)
1661 struct drm_i915_gem_mmap_gtt *args = data;
1663 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1666 /* Immediately discard the backing storage */
1668 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1670 struct inode *inode;
1672 i915_gem_object_free_mmap_offset(obj);
1674 if (obj->base.filp == NULL)
1677 /* Our goal here is to return as much of the memory as
1678 * is possible back to the system as we are called from OOM.
1679 * To do this we must instruct the shmfs to drop all of its
1680 * backing pages, *now*.
1682 inode = file_inode(obj->base.filp);
1683 shmem_truncate_range(inode, 0, (loff_t)-1);
1685 obj->madv = __I915_MADV_PURGED;
1689 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1691 return obj->madv == I915_MADV_DONTNEED;
1695 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1697 struct sg_page_iter sg_iter;
1700 BUG_ON(obj->madv == __I915_MADV_PURGED);
1702 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1704 /* In the event of a disaster, abandon all caches and
1705 * hope for the best.
1707 WARN_ON(ret != -EIO);
1708 i915_gem_clflush_object(obj, true);
1709 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1712 if (i915_gem_object_needs_bit17_swizzle(obj))
1713 i915_gem_object_save_bit_17_swizzle(obj);
1715 if (obj->madv == I915_MADV_DONTNEED)
1718 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1719 struct page *page = sg_page_iter_page(&sg_iter);
1722 set_page_dirty(page);
1724 if (obj->madv == I915_MADV_WILLNEED)
1725 mark_page_accessed(page);
1727 page_cache_release(page);
1731 sg_free_table(obj->pages);
1736 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1738 const struct drm_i915_gem_object_ops *ops = obj->ops;
1740 if (obj->pages == NULL)
1743 if (obj->pages_pin_count)
1746 BUG_ON(i915_gem_obj_bound_any(obj));
1748 /* ->put_pages might need to allocate memory for the bit17 swizzle
1749 * array, hence protect them from being reaped by removing them from gtt
1751 list_del(&obj->global_list);
1753 ops->put_pages(obj);
1756 if (i915_gem_object_is_purgeable(obj))
1757 i915_gem_object_truncate(obj);
1762 static unsigned long
1763 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1764 bool purgeable_only)
1766 struct list_head still_bound_list;
1767 struct drm_i915_gem_object *obj, *next;
1768 unsigned long count = 0;
1770 list_for_each_entry_safe(obj, next,
1771 &dev_priv->mm.unbound_list,
1773 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1774 i915_gem_object_put_pages(obj) == 0) {
1775 count += obj->base.size >> PAGE_SHIFT;
1776 if (count >= target)
1782 * As we may completely rewrite the bound list whilst unbinding
1783 * (due to retiring requests) we have to strictly process only
1784 * one element of the list at the time, and recheck the list
1785 * on every iteration.
1787 INIT_LIST_HEAD(&still_bound_list);
1788 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1789 struct i915_vma *vma, *v;
1791 obj = list_first_entry(&dev_priv->mm.bound_list,
1792 typeof(*obj), global_list);
1793 list_move_tail(&obj->global_list, &still_bound_list);
1795 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1799 * Hold a reference whilst we unbind this object, as we may
1800 * end up waiting for and retiring requests. This might
1801 * release the final reference (held by the active list)
1802 * and result in the object being freed from under us.
1803 * in this object being freed.
1805 * Note 1: Shrinking the bound list is special since only active
1806 * (and hence bound objects) can contain such limbo objects, so
1807 * we don't need special tricks for shrinking the unbound list.
1808 * The only other place where we have to be careful with active
1809 * objects suddenly disappearing due to retiring requests is the
1812 * Note 2: Even though the bound list doesn't hold a reference
1813 * to the object we can safely grab one here: The final object
1814 * unreferencing and the bound_list are both protected by the
1815 * dev->struct_mutex and so we won't ever be able to observe an
1816 * object on the bound_list with a reference count equals 0.
1818 drm_gem_object_reference(&obj->base);
1820 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1821 if (i915_vma_unbind(vma))
1824 if (i915_gem_object_put_pages(obj) == 0)
1825 count += obj->base.size >> PAGE_SHIFT;
1827 drm_gem_object_unreference(&obj->base);
1829 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1834 static unsigned long
1835 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1837 return __i915_gem_shrink(dev_priv, target, true);
1840 static unsigned long
1841 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1843 struct drm_i915_gem_object *obj, *next;
1846 i915_gem_evict_everything(dev_priv->dev);
1848 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1850 if (i915_gem_object_put_pages(obj) == 0)
1851 freed += obj->base.size >> PAGE_SHIFT;
1857 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1859 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1861 struct address_space *mapping;
1862 struct sg_table *st;
1863 struct scatterlist *sg;
1864 struct sg_page_iter sg_iter;
1866 unsigned long last_pfn = 0; /* suppress gcc warning */
1869 /* Assert that the object is not currently in any GPU domain. As it
1870 * wasn't in the GTT, there shouldn't be any way it could have been in
1873 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1874 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1876 st = kmalloc(sizeof(*st), GFP_KERNEL);
1880 page_count = obj->base.size / PAGE_SIZE;
1881 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1886 /* Get the list of pages out of our struct file. They'll be pinned
1887 * at this point until we release them.
1889 * Fail silently without starting the shrinker
1891 mapping = file_inode(obj->base.filp)->i_mapping;
1892 gfp = mapping_gfp_mask(mapping);
1893 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1894 gfp &= ~(__GFP_IO | __GFP_WAIT);
1897 for (i = 0; i < page_count; i++) {
1898 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1900 i915_gem_purge(dev_priv, page_count);
1901 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1904 /* We've tried hard to allocate the memory by reaping
1905 * our own buffer, now let the real VM do its job and
1906 * go down in flames if truly OOM.
1908 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1909 gfp |= __GFP_IO | __GFP_WAIT;
1911 i915_gem_shrink_all(dev_priv);
1912 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1916 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1917 gfp &= ~(__GFP_IO | __GFP_WAIT);
1919 #ifdef CONFIG_SWIOTLB
1920 if (swiotlb_nr_tbl()) {
1922 sg_set_page(sg, page, PAGE_SIZE, 0);
1927 if (!i || page_to_pfn(page) != last_pfn + 1) {
1931 sg_set_page(sg, page, PAGE_SIZE, 0);
1933 sg->length += PAGE_SIZE;
1935 last_pfn = page_to_pfn(page);
1937 /* Check that the i965g/gm workaround works. */
1938 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1940 #ifdef CONFIG_SWIOTLB
1941 if (!swiotlb_nr_tbl())
1946 if (i915_gem_object_needs_bit17_swizzle(obj))
1947 i915_gem_object_do_bit_17_swizzle(obj);
1953 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1954 page_cache_release(sg_page_iter_page(&sg_iter));
1957 return PTR_ERR(page);
1960 /* Ensure that the associated pages are gathered from the backing storage
1961 * and pinned into our object. i915_gem_object_get_pages() may be called
1962 * multiple times before they are released by a single call to
1963 * i915_gem_object_put_pages() - once the pages are no longer referenced
1964 * either as a result of memory pressure (reaping pages under the shrinker)
1965 * or as the object is itself released.
1968 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1970 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1971 const struct drm_i915_gem_object_ops *ops = obj->ops;
1977 if (obj->madv != I915_MADV_WILLNEED) {
1978 DRM_ERROR("Attempting to obtain a purgeable object\n");
1982 BUG_ON(obj->pages_pin_count);
1984 ret = ops->get_pages(obj);
1988 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1993 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1994 struct intel_ring_buffer *ring)
1996 struct drm_device *dev = obj->base.dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 u32 seqno = intel_ring_get_seqno(ring);
2000 BUG_ON(ring == NULL);
2001 if (obj->ring != ring && obj->last_write_seqno) {
2002 /* Keep the seqno relative to the current ring */
2003 obj->last_write_seqno = seqno;
2007 /* Add a reference if we're newly entering the active list. */
2009 drm_gem_object_reference(&obj->base);
2013 list_move_tail(&obj->ring_list, &ring->active_list);
2015 obj->last_read_seqno = seqno;
2017 if (obj->fenced_gpu_access) {
2018 obj->last_fenced_seqno = seqno;
2020 /* Bump MRU to take account of the delayed flush */
2021 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2022 struct drm_i915_fence_reg *reg;
2024 reg = &dev_priv->fence_regs[obj->fence_reg];
2025 list_move_tail(®->lru_list,
2026 &dev_priv->mm.fence_list);
2031 void i915_vma_move_to_active(struct i915_vma *vma,
2032 struct intel_ring_buffer *ring)
2034 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2035 return i915_gem_object_move_to_active(vma->obj, ring);
2039 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2041 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2042 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2043 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2045 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2046 BUG_ON(!obj->active);
2048 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2050 list_del_init(&obj->ring_list);
2053 obj->last_read_seqno = 0;
2054 obj->last_write_seqno = 0;
2055 obj->base.write_domain = 0;
2057 obj->last_fenced_seqno = 0;
2058 obj->fenced_gpu_access = false;
2061 drm_gem_object_unreference(&obj->base);
2063 WARN_ON(i915_verify_lists(dev));
2067 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_ring_buffer *ring;
2073 /* Carefully retire all requests without writing to the rings */
2074 for_each_ring(ring, dev_priv, i) {
2075 ret = intel_ring_idle(ring);
2079 i915_gem_retire_requests(dev);
2081 /* Finally reset hw state */
2082 for_each_ring(ring, dev_priv, i) {
2083 intel_ring_init_seqno(ring, seqno);
2085 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2086 ring->sync_seqno[j] = 0;
2092 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2100 /* HWS page needs to be set less than what we
2101 * will inject to ring
2103 ret = i915_gem_init_seqno(dev, seqno - 1);
2107 /* Carefully set the last_seqno value so that wrap
2108 * detection still works
2110 dev_priv->next_seqno = seqno;
2111 dev_priv->last_seqno = seqno - 1;
2112 if (dev_priv->last_seqno == 0)
2113 dev_priv->last_seqno--;
2119 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2123 /* reserve 0 for non-seqno */
2124 if (dev_priv->next_seqno == 0) {
2125 int ret = i915_gem_init_seqno(dev, 0);
2129 dev_priv->next_seqno = 1;
2132 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2136 int __i915_add_request(struct intel_ring_buffer *ring,
2137 struct drm_file *file,
2138 struct drm_i915_gem_object *obj,
2141 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2142 struct drm_i915_gem_request *request;
2143 u32 request_ring_position, request_start;
2147 request_start = intel_ring_get_tail(ring);
2149 * Emit any outstanding flushes - execbuf can fail to emit the flush
2150 * after having emitted the batchbuffer command. Hence we need to fix
2151 * things up similar to emitting the lazy request. The difference here
2152 * is that the flush _must_ happen before the next request, no matter
2155 ret = intel_ring_flush_all_caches(ring);
2159 request = ring->preallocated_lazy_request;
2160 if (WARN_ON(request == NULL))
2163 /* Record the position of the start of the request so that
2164 * should we detect the updated seqno part-way through the
2165 * GPU processing the request, we never over-estimate the
2166 * position of the head.
2168 request_ring_position = intel_ring_get_tail(ring);
2170 ret = ring->add_request(ring);
2174 request->seqno = intel_ring_get_seqno(ring);
2175 request->ring = ring;
2176 request->head = request_start;
2177 request->tail = request_ring_position;
2179 /* Whilst this request exists, batch_obj will be on the
2180 * active_list, and so will hold the active reference. Only when this
2181 * request is retired will the the batch_obj be moved onto the
2182 * inactive_list and lose its active reference. Hence we do not need
2183 * to explicitly hold another reference here.
2185 request->batch_obj = obj;
2187 /* Hold a reference to the current context so that we can inspect
2188 * it later in case a hangcheck error event fires.
2190 request->ctx = ring->last_context;
2192 i915_gem_context_reference(request->ctx);
2194 request->emitted_jiffies = jiffies;
2195 was_empty = list_empty(&ring->request_list);
2196 list_add_tail(&request->list, &ring->request_list);
2197 request->file_priv = NULL;
2200 struct drm_i915_file_private *file_priv = file->driver_priv;
2202 spin_lock(&file_priv->mm.lock);
2203 request->file_priv = file_priv;
2204 list_add_tail(&request->client_list,
2205 &file_priv->mm.request_list);
2206 spin_unlock(&file_priv->mm.lock);
2209 trace_i915_gem_request_add(ring, request->seqno);
2210 ring->outstanding_lazy_seqno = 0;
2211 ring->preallocated_lazy_request = NULL;
2213 if (!dev_priv->ums.mm_suspended) {
2214 i915_queue_hangcheck(ring->dev);
2217 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2218 queue_delayed_work(dev_priv->wq,
2219 &dev_priv->mm.retire_work,
2220 round_jiffies_up_relative(HZ));
2221 intel_mark_busy(dev_priv->dev);
2226 *out_seqno = request->seqno;
2231 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2233 struct drm_i915_file_private *file_priv = request->file_priv;
2238 spin_lock(&file_priv->mm.lock);
2239 list_del(&request->client_list);
2240 request->file_priv = NULL;
2241 spin_unlock(&file_priv->mm.lock);
2244 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2245 struct i915_address_space *vm)
2247 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2248 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2254 static bool i915_head_inside_request(const u32 acthd_unmasked,
2255 const u32 request_start,
2256 const u32 request_end)
2258 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2260 if (request_start < request_end) {
2261 if (acthd >= request_start && acthd < request_end)
2263 } else if (request_start > request_end) {
2264 if (acthd >= request_start || acthd < request_end)
2271 static struct i915_address_space *
2272 request_to_vm(struct drm_i915_gem_request *request)
2274 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2275 struct i915_address_space *vm;
2277 vm = &dev_priv->gtt.base;
2282 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2283 const u32 acthd, bool *inside)
2285 /* There is a possibility that unmasked head address
2286 * pointing inside the ring, matches the batch_obj address range.
2287 * However this is extremely unlikely.
2289 if (request->batch_obj) {
2290 if (i915_head_inside_object(acthd, request->batch_obj,
2291 request_to_vm(request))) {
2297 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2305 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2307 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2312 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2313 DRM_ERROR("context hanging too fast, declaring banned!\n");
2320 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2321 struct drm_i915_gem_request *request,
2324 struct i915_ctx_hang_stats *hs = NULL;
2325 bool inside, guilty;
2326 unsigned long offset = 0;
2328 /* Innocent until proven guilty */
2331 if (request->batch_obj)
2332 offset = i915_gem_obj_offset(request->batch_obj,
2333 request_to_vm(request));
2335 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2336 i915_request_guilty(request, acthd, &inside)) {
2337 DRM_DEBUG("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2339 inside ? "inside" : "flushing",
2341 request->ctx ? request->ctx->id : 0,
2347 /* If contexts are disabled or this is the default context, use
2348 * file_priv->reset_state
2350 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2351 hs = &request->ctx->hang_stats;
2352 else if (request->file_priv)
2353 hs = &request->file_priv->hang_stats;
2357 hs->banned = i915_context_is_banned(hs);
2359 hs->guilty_ts = get_seconds();
2361 hs->batch_pending++;
2366 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2368 list_del(&request->list);
2369 i915_gem_request_remove_from_client(request);
2372 i915_gem_context_unreference(request->ctx);
2377 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2378 struct intel_ring_buffer *ring)
2380 u32 completed_seqno = ring->get_seqno(ring, false);
2381 u32 acthd = intel_ring_get_active_head(ring);
2382 struct drm_i915_gem_request *request;
2384 list_for_each_entry(request, &ring->request_list, list) {
2385 if (i915_seqno_passed(completed_seqno, request->seqno))
2388 i915_set_reset_status(ring, request, acthd);
2392 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2393 struct intel_ring_buffer *ring)
2395 while (!list_empty(&ring->active_list)) {
2396 struct drm_i915_gem_object *obj;
2398 obj = list_first_entry(&ring->active_list,
2399 struct drm_i915_gem_object,
2402 i915_gem_object_move_to_inactive(obj);
2406 * We must free the requests after all the corresponding objects have
2407 * been moved off active lists. Which is the same order as the normal
2408 * retire_requests function does. This is important if object hold
2409 * implicit references on things like e.g. ppgtt address spaces through
2412 while (!list_empty(&ring->request_list)) {
2413 struct drm_i915_gem_request *request;
2415 request = list_first_entry(&ring->request_list,
2416 struct drm_i915_gem_request,
2419 i915_gem_free_request(request);
2423 void i915_gem_restore_fences(struct drm_device *dev)
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2428 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2429 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2432 * Commit delayed tiling changes if we have an object still
2433 * attached to the fence, otherwise just clear the fence.
2436 i915_gem_object_update_fence(reg->obj, reg,
2437 reg->obj->tiling_mode);
2439 i915_gem_write_fence(dev, i, NULL);
2444 void i915_gem_reset(struct drm_device *dev)
2446 struct drm_i915_private *dev_priv = dev->dev_private;
2447 struct intel_ring_buffer *ring;
2451 * Before we free the objects from the requests, we need to inspect
2452 * them for finding the guilty party. As the requests only borrow
2453 * their reference to the objects, the inspection must be done first.
2455 for_each_ring(ring, dev_priv, i)
2456 i915_gem_reset_ring_status(dev_priv, ring);
2458 for_each_ring(ring, dev_priv, i)
2459 i915_gem_reset_ring_cleanup(dev_priv, ring);
2461 i915_gem_cleanup_ringbuffer(dev);
2463 i915_gem_restore_fences(dev);
2467 * This function clears the request list as sequence numbers are passed.
2470 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2474 if (list_empty(&ring->request_list))
2477 WARN_ON(i915_verify_lists(ring->dev));
2479 seqno = ring->get_seqno(ring, true);
2481 while (!list_empty(&ring->request_list)) {
2482 struct drm_i915_gem_request *request;
2484 request = list_first_entry(&ring->request_list,
2485 struct drm_i915_gem_request,
2488 if (!i915_seqno_passed(seqno, request->seqno))
2491 trace_i915_gem_request_retire(ring, request->seqno);
2492 /* We know the GPU must have read the request to have
2493 * sent us the seqno + interrupt, so use the position
2494 * of tail of the request to update the last known position
2497 ring->last_retired_head = request->tail;
2499 i915_gem_free_request(request);
2502 /* Move any buffers on the active list that are no longer referenced
2503 * by the ringbuffer to the flushing/inactive lists as appropriate.
2505 while (!list_empty(&ring->active_list)) {
2506 struct drm_i915_gem_object *obj;
2508 obj = list_first_entry(&ring->active_list,
2509 struct drm_i915_gem_object,
2512 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2515 i915_gem_object_move_to_inactive(obj);
2518 if (unlikely(ring->trace_irq_seqno &&
2519 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2520 ring->irq_put(ring);
2521 ring->trace_irq_seqno = 0;
2524 WARN_ON(i915_verify_lists(ring->dev));
2528 i915_gem_retire_requests(struct drm_device *dev)
2530 drm_i915_private_t *dev_priv = dev->dev_private;
2531 struct intel_ring_buffer *ring;
2535 for_each_ring(ring, dev_priv, i) {
2536 i915_gem_retire_requests_ring(ring);
2537 idle &= list_empty(&ring->request_list);
2541 mod_delayed_work(dev_priv->wq,
2542 &dev_priv->mm.idle_work,
2543 msecs_to_jiffies(100));
2549 i915_gem_retire_work_handler(struct work_struct *work)
2551 struct drm_i915_private *dev_priv =
2552 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2553 struct drm_device *dev = dev_priv->dev;
2556 /* Come back later if the device is busy... */
2558 if (mutex_trylock(&dev->struct_mutex)) {
2559 idle = i915_gem_retire_requests(dev);
2560 mutex_unlock(&dev->struct_mutex);
2563 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2564 round_jiffies_up_relative(HZ));
2568 i915_gem_idle_work_handler(struct work_struct *work)
2570 struct drm_i915_private *dev_priv =
2571 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2573 intel_mark_idle(dev_priv->dev);
2577 * Ensures that an object will eventually get non-busy by flushing any required
2578 * write domains, emitting any outstanding lazy request and retiring and
2579 * completed requests.
2582 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2587 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2591 i915_gem_retire_requests_ring(obj->ring);
2598 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2599 * @DRM_IOCTL_ARGS: standard ioctl arguments
2601 * Returns 0 if successful, else an error is returned with the remaining time in
2602 * the timeout parameter.
2603 * -ETIME: object is still busy after timeout
2604 * -ERESTARTSYS: signal interrupted the wait
2605 * -ENONENT: object doesn't exist
2606 * Also possible, but rare:
2607 * -EAGAIN: GPU wedged
2609 * -ENODEV: Internal IRQ fail
2610 * -E?: The add request failed
2612 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2613 * non-zero timeout parameter the wait ioctl will wait for the given number of
2614 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2615 * without holding struct_mutex the object may become re-busied before this
2616 * function completes. A similar but shorter * race condition exists in the busy
2620 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2622 drm_i915_private_t *dev_priv = dev->dev_private;
2623 struct drm_i915_gem_wait *args = data;
2624 struct drm_i915_gem_object *obj;
2625 struct intel_ring_buffer *ring = NULL;
2626 struct timespec timeout_stack, *timeout = NULL;
2627 unsigned reset_counter;
2631 if (args->timeout_ns >= 0) {
2632 timeout_stack = ns_to_timespec(args->timeout_ns);
2633 timeout = &timeout_stack;
2636 ret = i915_mutex_lock_interruptible(dev);
2640 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2641 if (&obj->base == NULL) {
2642 mutex_unlock(&dev->struct_mutex);
2646 /* Need to make sure the object gets inactive eventually. */
2647 ret = i915_gem_object_flush_active(obj);
2652 seqno = obj->last_read_seqno;
2659 /* Do this after OLR check to make sure we make forward progress polling
2660 * on this IOCTL with a 0 timeout (like busy ioctl)
2662 if (!args->timeout_ns) {
2667 drm_gem_object_unreference(&obj->base);
2668 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2669 mutex_unlock(&dev->struct_mutex);
2671 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2673 args->timeout_ns = timespec_to_ns(timeout);
2677 drm_gem_object_unreference(&obj->base);
2678 mutex_unlock(&dev->struct_mutex);
2683 * i915_gem_object_sync - sync an object to a ring.
2685 * @obj: object which may be in use on another ring.
2686 * @to: ring we wish to use the object on. May be NULL.
2688 * This code is meant to abstract object synchronization with the GPU.
2689 * Calling with NULL implies synchronizing the object with the CPU
2690 * rather than a particular GPU ring.
2692 * Returns 0 if successful, else propagates up the lower layer error.
2695 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2696 struct intel_ring_buffer *to)
2698 struct intel_ring_buffer *from = obj->ring;
2702 if (from == NULL || to == from)
2705 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2706 return i915_gem_object_wait_rendering(obj, false);
2708 idx = intel_ring_sync_index(from, to);
2710 seqno = obj->last_read_seqno;
2711 if (seqno <= from->sync_seqno[idx])
2714 ret = i915_gem_check_olr(obj->ring, seqno);
2718 trace_i915_gem_ring_sync_to(from, to, seqno);
2719 ret = to->sync_to(to, from, seqno);
2721 /* We use last_read_seqno because sync_to()
2722 * might have just caused seqno wrap under
2725 from->sync_seqno[idx] = obj->last_read_seqno;
2730 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2732 u32 old_write_domain, old_read_domains;
2734 /* Force a pagefault for domain tracking on next user access */
2735 i915_gem_release_mmap(obj);
2737 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2740 /* Wait for any direct GTT access to complete */
2743 old_read_domains = obj->base.read_domains;
2744 old_write_domain = obj->base.write_domain;
2746 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2747 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2749 trace_i915_gem_object_change_domain(obj,
2754 int i915_vma_unbind(struct i915_vma *vma)
2756 struct drm_i915_gem_object *obj = vma->obj;
2757 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2760 /* For now we only ever use 1 vma per object */
2761 WARN_ON(!list_is_singular(&obj->vma_list));
2763 if (list_empty(&vma->vma_link))
2766 if (!drm_mm_node_allocated(&vma->node)) {
2767 i915_gem_vma_destroy(vma);
2775 BUG_ON(obj->pages == NULL);
2777 ret = i915_gem_object_finish_gpu(obj);
2780 /* Continue on if we fail due to EIO, the GPU is hung so we
2781 * should be safe and we need to cleanup or else we might
2782 * cause memory corruption through use-after-free.
2785 i915_gem_object_finish_gtt(obj);
2787 /* release the fence reg _after_ flushing */
2788 ret = i915_gem_object_put_fence(obj);
2792 trace_i915_vma_unbind(vma);
2794 if (obj->has_global_gtt_mapping)
2795 i915_gem_gtt_unbind_object(obj);
2796 if (obj->has_aliasing_ppgtt_mapping) {
2797 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2798 obj->has_aliasing_ppgtt_mapping = 0;
2800 i915_gem_gtt_finish_object(obj);
2802 list_del(&vma->mm_list);
2803 /* Avoid an unnecessary call to unbind on rebind. */
2804 if (i915_is_ggtt(vma->vm))
2805 obj->map_and_fenceable = true;
2807 drm_mm_remove_node(&vma->node);
2808 i915_gem_vma_destroy(vma);
2810 /* Since the unbound list is global, only move to that list if
2811 * no more VMAs exist. */
2812 if (list_empty(&obj->vma_list))
2813 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2815 /* And finally now the object is completely decoupled from this vma,
2816 * we can drop its hold on the backing storage and allow it to be
2817 * reaped by the shrinker.
2819 i915_gem_object_unpin_pages(obj);
2825 * Unbinds an object from the global GTT aperture.
2828 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2830 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2831 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2833 if (!i915_gem_obj_ggtt_bound(obj))
2839 BUG_ON(obj->pages == NULL);
2841 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2844 int i915_gpu_idle(struct drm_device *dev)
2846 drm_i915_private_t *dev_priv = dev->dev_private;
2847 struct intel_ring_buffer *ring;
2850 /* Flush everything onto the inactive list. */
2851 for_each_ring(ring, dev_priv, i) {
2852 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2856 ret = intel_ring_idle(ring);
2864 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2865 struct drm_i915_gem_object *obj)
2867 drm_i915_private_t *dev_priv = dev->dev_private;
2869 int fence_pitch_shift;
2871 if (INTEL_INFO(dev)->gen >= 6) {
2872 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2873 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2875 fence_reg = FENCE_REG_965_0;
2876 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2879 fence_reg += reg * 8;
2881 /* To w/a incoherency with non-atomic 64-bit register updates,
2882 * we split the 64-bit update into two 32-bit writes. In order
2883 * for a partial fence not to be evaluated between writes, we
2884 * precede the update with write to turn off the fence register,
2885 * and only enable the fence as the last step.
2887 * For extra levels of paranoia, we make sure each step lands
2888 * before applying the next step.
2890 I915_WRITE(fence_reg, 0);
2891 POSTING_READ(fence_reg);
2894 u32 size = i915_gem_obj_ggtt_size(obj);
2897 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2899 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2900 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2901 if (obj->tiling_mode == I915_TILING_Y)
2902 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2903 val |= I965_FENCE_REG_VALID;
2905 I915_WRITE(fence_reg + 4, val >> 32);
2906 POSTING_READ(fence_reg + 4);
2908 I915_WRITE(fence_reg + 0, val);
2909 POSTING_READ(fence_reg);
2911 I915_WRITE(fence_reg + 4, 0);
2912 POSTING_READ(fence_reg + 4);
2916 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2917 struct drm_i915_gem_object *obj)
2919 drm_i915_private_t *dev_priv = dev->dev_private;
2923 u32 size = i915_gem_obj_ggtt_size(obj);
2927 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2928 (size & -size) != size ||
2929 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2930 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2931 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2933 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2938 /* Note: pitch better be a power of two tile widths */
2939 pitch_val = obj->stride / tile_width;
2940 pitch_val = ffs(pitch_val) - 1;
2942 val = i915_gem_obj_ggtt_offset(obj);
2943 if (obj->tiling_mode == I915_TILING_Y)
2944 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2945 val |= I915_FENCE_SIZE_BITS(size);
2946 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2947 val |= I830_FENCE_REG_VALID;
2952 reg = FENCE_REG_830_0 + reg * 4;
2954 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2956 I915_WRITE(reg, val);
2960 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2961 struct drm_i915_gem_object *obj)
2963 drm_i915_private_t *dev_priv = dev->dev_private;
2967 u32 size = i915_gem_obj_ggtt_size(obj);
2970 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2971 (size & -size) != size ||
2972 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2973 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2974 i915_gem_obj_ggtt_offset(obj), size);
2976 pitch_val = obj->stride / 128;
2977 pitch_val = ffs(pitch_val) - 1;
2979 val = i915_gem_obj_ggtt_offset(obj);
2980 if (obj->tiling_mode == I915_TILING_Y)
2981 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2982 val |= I830_FENCE_SIZE_BITS(size);
2983 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2984 val |= I830_FENCE_REG_VALID;
2988 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2989 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2992 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2994 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2997 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2998 struct drm_i915_gem_object *obj)
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3002 /* Ensure that all CPU reads are completed before installing a fence
3003 * and all writes before removing the fence.
3005 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3008 WARN(obj && (!obj->stride || !obj->tiling_mode),
3009 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3010 obj->stride, obj->tiling_mode);
3012 switch (INTEL_INFO(dev)->gen) {
3017 case 4: i965_write_fence_reg(dev, reg, obj); break;
3018 case 3: i915_write_fence_reg(dev, reg, obj); break;
3019 case 2: i830_write_fence_reg(dev, reg, obj); break;
3023 /* And similarly be paranoid that no direct access to this region
3024 * is reordered to before the fence is installed.
3026 if (i915_gem_object_needs_mb(obj))
3030 static inline int fence_number(struct drm_i915_private *dev_priv,
3031 struct drm_i915_fence_reg *fence)
3033 return fence - dev_priv->fence_regs;
3036 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3037 struct drm_i915_fence_reg *fence,
3040 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3041 int reg = fence_number(dev_priv, fence);
3043 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3046 obj->fence_reg = reg;
3048 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3050 obj->fence_reg = I915_FENCE_REG_NONE;
3052 list_del_init(&fence->lru_list);
3054 obj->fence_dirty = false;
3058 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3060 if (obj->last_fenced_seqno) {
3061 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3065 obj->last_fenced_seqno = 0;
3068 obj->fenced_gpu_access = false;
3073 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3075 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3076 struct drm_i915_fence_reg *fence;
3079 ret = i915_gem_object_wait_fence(obj);
3083 if (obj->fence_reg == I915_FENCE_REG_NONE)
3086 fence = &dev_priv->fence_regs[obj->fence_reg];
3088 i915_gem_object_fence_lost(obj);
3089 i915_gem_object_update_fence(obj, fence, false);
3094 static struct drm_i915_fence_reg *
3095 i915_find_fence_reg(struct drm_device *dev)
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct drm_i915_fence_reg *reg, *avail;
3101 /* First try to find a free reg */
3103 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3104 reg = &dev_priv->fence_regs[i];
3108 if (!reg->pin_count)
3115 /* None available, try to steal one or wait for a user to finish */
3116 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3124 /* Wait for completion of pending flips which consume fences */
3125 if (intel_has_pending_fb_unpin(dev))
3126 return ERR_PTR(-EAGAIN);
3128 return ERR_PTR(-EDEADLK);
3132 * i915_gem_object_get_fence - set up fencing for an object
3133 * @obj: object to map through a fence reg
3135 * When mapping objects through the GTT, userspace wants to be able to write
3136 * to them without having to worry about swizzling if the object is tiled.
3137 * This function walks the fence regs looking for a free one for @obj,
3138 * stealing one if it can't find any.
3140 * It then sets up the reg based on the object's properties: address, pitch
3141 * and tiling format.
3143 * For an untiled surface, this removes any existing fence.
3146 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3148 struct drm_device *dev = obj->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 bool enable = obj->tiling_mode != I915_TILING_NONE;
3151 struct drm_i915_fence_reg *reg;
3154 /* Have we updated the tiling parameters upon the object and so
3155 * will need to serialise the write to the associated fence register?
3157 if (obj->fence_dirty) {
3158 ret = i915_gem_object_wait_fence(obj);
3163 /* Just update our place in the LRU if our fence is getting reused. */
3164 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3165 reg = &dev_priv->fence_regs[obj->fence_reg];
3166 if (!obj->fence_dirty) {
3167 list_move_tail(®->lru_list,
3168 &dev_priv->mm.fence_list);
3171 } else if (enable) {
3172 reg = i915_find_fence_reg(dev);
3174 return PTR_ERR(reg);
3177 struct drm_i915_gem_object *old = reg->obj;
3179 ret = i915_gem_object_wait_fence(old);
3183 i915_gem_object_fence_lost(old);
3188 i915_gem_object_update_fence(obj, reg, enable);
3193 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3194 struct drm_mm_node *gtt_space,
3195 unsigned long cache_level)
3197 struct drm_mm_node *other;
3199 /* On non-LLC machines we have to be careful when putting differing
3200 * types of snoopable memory together to avoid the prefetcher
3201 * crossing memory domains and dying.
3206 if (!drm_mm_node_allocated(gtt_space))
3209 if (list_empty(>t_space->node_list))
3212 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3213 if (other->allocated && !other->hole_follows && other->color != cache_level)
3216 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3217 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3223 static void i915_gem_verify_gtt(struct drm_device *dev)
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 struct drm_i915_gem_object *obj;
3230 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3231 if (obj->gtt_space == NULL) {
3232 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3237 if (obj->cache_level != obj->gtt_space->color) {
3238 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3239 i915_gem_obj_ggtt_offset(obj),
3240 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3242 obj->gtt_space->color);
3247 if (!i915_gem_valid_gtt_space(dev,
3249 obj->cache_level)) {
3250 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3251 i915_gem_obj_ggtt_offset(obj),
3252 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3264 * Finds free space in the GTT aperture and binds the object there.
3267 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3268 struct i915_address_space *vm,
3270 bool map_and_fenceable,
3273 struct drm_device *dev = obj->base.dev;
3274 drm_i915_private_t *dev_priv = dev->dev_private;
3275 u32 size, fence_size, fence_alignment, unfenced_alignment;
3277 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3278 struct i915_vma *vma;
3281 fence_size = i915_gem_get_gtt_size(dev,
3284 fence_alignment = i915_gem_get_gtt_alignment(dev,
3286 obj->tiling_mode, true);
3287 unfenced_alignment =
3288 i915_gem_get_gtt_alignment(dev,
3290 obj->tiling_mode, false);
3293 alignment = map_and_fenceable ? fence_alignment :
3295 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3296 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3300 size = map_and_fenceable ? fence_size : obj->base.size;
3302 /* If the object is bigger than the entire aperture, reject it early
3303 * before evicting everything in a vain attempt to find space.
3305 if (obj->base.size > gtt_max) {
3306 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3308 map_and_fenceable ? "mappable" : "total",
3313 ret = i915_gem_object_get_pages(obj);
3317 i915_gem_object_pin_pages(obj);
3319 BUG_ON(!i915_is_ggtt(vm));
3321 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3327 /* For now we only ever use 1 vma per object */
3328 WARN_ON(!list_is_singular(&obj->vma_list));
3331 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3333 obj->cache_level, 0, gtt_max,
3334 DRM_MM_SEARCH_DEFAULT);
3336 ret = i915_gem_evict_something(dev, vm, size, alignment,
3345 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3346 obj->cache_level))) {
3348 goto err_remove_node;
3351 ret = i915_gem_gtt_prepare_object(obj);
3353 goto err_remove_node;
3355 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3356 list_add_tail(&vma->mm_list, &vm->inactive_list);
3358 if (i915_is_ggtt(vm)) {
3359 bool mappable, fenceable;
3361 fenceable = (vma->node.size == fence_size &&
3362 (vma->node.start & (fence_alignment - 1)) == 0);
3364 mappable = (vma->node.start + obj->base.size <=
3365 dev_priv->gtt.mappable_end);
3367 obj->map_and_fenceable = mappable && fenceable;
3370 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3372 trace_i915_vma_bind(vma, map_and_fenceable);
3373 i915_gem_verify_gtt(dev);
3377 drm_mm_remove_node(&vma->node);
3379 i915_gem_vma_destroy(vma);
3381 i915_gem_object_unpin_pages(obj);
3386 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3389 /* If we don't have a page list set up, then we're not pinned
3390 * to GPU, and we can ignore the cache flush because it'll happen
3391 * again at bind time.
3393 if (obj->pages == NULL)
3397 * Stolen memory is always coherent with the GPU as it is explicitly
3398 * marked as wc by the system, or the system is cache-coherent.
3403 /* If the GPU is snooping the contents of the CPU cache,
3404 * we do not need to manually clear the CPU cache lines. However,
3405 * the caches are only snooped when the render cache is
3406 * flushed/invalidated. As we always have to emit invalidations
3407 * and flushes when moving into and out of the RENDER domain, correct
3408 * snooping behaviour occurs naturally as the result of our domain
3411 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3414 trace_i915_gem_object_clflush(obj);
3415 drm_clflush_sg(obj->pages);
3420 /** Flushes the GTT write domain for the object if it's dirty. */
3422 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3424 uint32_t old_write_domain;
3426 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3429 /* No actual flushing is required for the GTT write domain. Writes
3430 * to it immediately go to main memory as far as we know, so there's
3431 * no chipset flush. It also doesn't land in render cache.
3433 * However, we do have to enforce the order so that all writes through
3434 * the GTT land before any writes to the device, such as updates to
3439 old_write_domain = obj->base.write_domain;
3440 obj->base.write_domain = 0;
3442 trace_i915_gem_object_change_domain(obj,
3443 obj->base.read_domains,
3447 /** Flushes the CPU write domain for the object if it's dirty. */
3449 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3452 uint32_t old_write_domain;
3454 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3457 if (i915_gem_clflush_object(obj, force))
3458 i915_gem_chipset_flush(obj->base.dev);
3460 old_write_domain = obj->base.write_domain;
3461 obj->base.write_domain = 0;
3463 trace_i915_gem_object_change_domain(obj,
3464 obj->base.read_domains,
3469 * Moves a single object to the GTT read, and possibly write domain.
3471 * This function returns when the move is complete, including waiting on
3475 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3477 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3478 uint32_t old_write_domain, old_read_domains;
3481 /* Not valid to be called on unbound objects. */
3482 if (!i915_gem_obj_bound_any(obj))
3485 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3488 ret = i915_gem_object_wait_rendering(obj, !write);
3492 i915_gem_object_flush_cpu_write_domain(obj, false);
3494 /* Serialise direct access to this object with the barriers for
3495 * coherent writes from the GPU, by effectively invalidating the
3496 * GTT domain upon first access.
3498 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3501 old_write_domain = obj->base.write_domain;
3502 old_read_domains = obj->base.read_domains;
3504 /* It should now be out of any other write domains, and we can update
3505 * the domain values for our changes.
3507 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3508 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3510 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3511 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3515 trace_i915_gem_object_change_domain(obj,
3519 /* And bump the LRU for this access */
3520 if (i915_gem_object_is_inactive(obj)) {
3521 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3523 list_move_tail(&vma->mm_list,
3524 &dev_priv->gtt.base.inactive_list);
3531 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3532 enum i915_cache_level cache_level)
3534 struct drm_device *dev = obj->base.dev;
3535 drm_i915_private_t *dev_priv = dev->dev_private;
3536 struct i915_vma *vma, *next;
3539 if (obj->cache_level == cache_level)
3542 if (obj->pin_count) {
3543 DRM_DEBUG("can not change the cache level of pinned objects\n");
3547 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3548 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3549 ret = i915_vma_unbind(vma);
3557 if (i915_gem_obj_bound_any(obj)) {
3558 ret = i915_gem_object_finish_gpu(obj);
3562 i915_gem_object_finish_gtt(obj);
3564 /* Before SandyBridge, you could not use tiling or fence
3565 * registers with snooped memory, so relinquish any fences
3566 * currently pointing to our region in the aperture.
3568 if (INTEL_INFO(dev)->gen < 6) {
3569 ret = i915_gem_object_put_fence(obj);
3574 if (obj->has_global_gtt_mapping)
3575 i915_gem_gtt_bind_object(obj, cache_level);
3576 if (obj->has_aliasing_ppgtt_mapping)
3577 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3581 list_for_each_entry(vma, &obj->vma_list, vma_link)
3582 vma->node.color = cache_level;
3583 obj->cache_level = cache_level;
3585 if (cpu_write_needs_clflush(obj)) {
3586 u32 old_read_domains, old_write_domain;
3588 /* If we're coming from LLC cached, then we haven't
3589 * actually been tracking whether the data is in the
3590 * CPU cache or not, since we only allow one bit set
3591 * in obj->write_domain and have been skipping the clflushes.
3592 * Just set it to the CPU cache for now.
3594 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3596 old_read_domains = obj->base.read_domains;
3597 old_write_domain = obj->base.write_domain;
3599 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3600 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3602 trace_i915_gem_object_change_domain(obj,
3607 i915_gem_verify_gtt(dev);
3611 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3612 struct drm_file *file)
3614 struct drm_i915_gem_caching *args = data;
3615 struct drm_i915_gem_object *obj;
3618 ret = i915_mutex_lock_interruptible(dev);
3622 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3623 if (&obj->base == NULL) {
3628 switch (obj->cache_level) {
3629 case I915_CACHE_LLC:
3630 case I915_CACHE_L3_LLC:
3631 args->caching = I915_CACHING_CACHED;
3635 args->caching = I915_CACHING_DISPLAY;
3639 args->caching = I915_CACHING_NONE;
3643 drm_gem_object_unreference(&obj->base);
3645 mutex_unlock(&dev->struct_mutex);
3649 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3650 struct drm_file *file)
3652 struct drm_i915_gem_caching *args = data;
3653 struct drm_i915_gem_object *obj;
3654 enum i915_cache_level level;
3657 switch (args->caching) {
3658 case I915_CACHING_NONE:
3659 level = I915_CACHE_NONE;
3661 case I915_CACHING_CACHED:
3662 level = I915_CACHE_LLC;
3664 case I915_CACHING_DISPLAY:
3665 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3671 ret = i915_mutex_lock_interruptible(dev);
3675 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3676 if (&obj->base == NULL) {
3681 ret = i915_gem_object_set_cache_level(obj, level);
3683 drm_gem_object_unreference(&obj->base);
3685 mutex_unlock(&dev->struct_mutex);
3689 static bool is_pin_display(struct drm_i915_gem_object *obj)
3691 /* There are 3 sources that pin objects:
3692 * 1. The display engine (scanouts, sprites, cursors);
3693 * 2. Reservations for execbuffer;
3696 * We can ignore reservations as we hold the struct_mutex and
3697 * are only called outside of the reservation path. The user
3698 * can only increment pin_count once, and so if after
3699 * subtracting the potential reference by the user, any pin_count
3700 * remains, it must be due to another use by the display engine.
3702 return obj->pin_count - !!obj->user_pin_count;
3706 * Prepare buffer for display plane (scanout, cursors, etc).
3707 * Can be called from an uninterruptible phase (modesetting) and allows
3708 * any flushes to be pipelined (for pageflips).
3711 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3713 struct intel_ring_buffer *pipelined)
3715 u32 old_read_domains, old_write_domain;
3718 if (pipelined != obj->ring) {
3719 ret = i915_gem_object_sync(obj, pipelined);
3724 /* Mark the pin_display early so that we account for the
3725 * display coherency whilst setting up the cache domains.
3727 obj->pin_display = true;
3729 /* The display engine is not coherent with the LLC cache on gen6. As
3730 * a result, we make sure that the pinning that is about to occur is
3731 * done with uncached PTEs. This is lowest common denominator for all
3734 * However for gen6+, we could do better by using the GFDT bit instead
3735 * of uncaching, which would allow us to flush all the LLC-cached data
3736 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3738 ret = i915_gem_object_set_cache_level(obj,
3739 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3741 goto err_unpin_display;
3743 /* As the user may map the buffer once pinned in the display plane
3744 * (e.g. libkms for the bootup splash), we have to ensure that we
3745 * always use map_and_fenceable for all scanout buffers.
3747 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3749 goto err_unpin_display;
3751 i915_gem_object_flush_cpu_write_domain(obj, true);
3753 old_write_domain = obj->base.write_domain;
3754 old_read_domains = obj->base.read_domains;
3756 /* It should now be out of any other write domains, and we can update
3757 * the domain values for our changes.
3759 obj->base.write_domain = 0;
3760 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3762 trace_i915_gem_object_change_domain(obj,
3769 obj->pin_display = is_pin_display(obj);
3774 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3776 i915_gem_object_unpin(obj);
3777 obj->pin_display = is_pin_display(obj);
3781 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3785 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3788 ret = i915_gem_object_wait_rendering(obj, false);
3792 /* Ensure that we invalidate the GPU's caches and TLBs. */
3793 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3798 * Moves a single object to the CPU read, and possibly write domain.
3800 * This function returns when the move is complete, including waiting on
3804 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3806 uint32_t old_write_domain, old_read_domains;
3809 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3812 ret = i915_gem_object_wait_rendering(obj, !write);
3816 i915_gem_object_flush_gtt_write_domain(obj);
3818 old_write_domain = obj->base.write_domain;
3819 old_read_domains = obj->base.read_domains;
3821 /* Flush the CPU cache if it's still invalid. */
3822 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3823 i915_gem_clflush_object(obj, false);
3825 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3828 /* It should now be out of any other write domains, and we can update
3829 * the domain values for our changes.
3831 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3833 /* If we're writing through the CPU, then the GPU read domains will
3834 * need to be invalidated at next use.
3837 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3838 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3841 trace_i915_gem_object_change_domain(obj,
3848 /* Throttle our rendering by waiting until the ring has completed our requests
3849 * emitted over 20 msec ago.
3851 * Note that if we were to use the current jiffies each time around the loop,
3852 * we wouldn't escape the function with any frames outstanding if the time to
3853 * render a frame was over 20ms.
3855 * This should get us reasonable parallelism between CPU and GPU but also
3856 * relatively low latency when blocking on a particular request to finish.
3859 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 struct drm_i915_file_private *file_priv = file->driver_priv;
3863 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3864 struct drm_i915_gem_request *request;
3865 struct intel_ring_buffer *ring = NULL;
3866 unsigned reset_counter;
3870 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3874 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3878 spin_lock(&file_priv->mm.lock);
3879 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3880 if (time_after_eq(request->emitted_jiffies, recent_enough))
3883 ring = request->ring;
3884 seqno = request->seqno;
3886 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3887 spin_unlock(&file_priv->mm.lock);
3892 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3894 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3900 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3901 struct i915_address_space *vm,
3903 bool map_and_fenceable,
3906 struct i915_vma *vma;
3909 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3912 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3914 vma = i915_gem_obj_to_vma(obj, vm);
3918 vma->node.start & (alignment - 1)) ||
3919 (map_and_fenceable && !obj->map_and_fenceable)) {
3920 WARN(obj->pin_count,
3921 "bo is already pinned with incorrect alignment:"
3922 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3923 " obj->map_and_fenceable=%d\n",
3924 i915_gem_obj_offset(obj, vm), alignment,
3926 obj->map_and_fenceable);
3927 ret = i915_vma_unbind(vma);
3933 if (!i915_gem_obj_bound(obj, vm)) {
3934 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3936 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3942 if (!dev_priv->mm.aliasing_ppgtt)
3943 i915_gem_gtt_bind_object(obj, obj->cache_level);
3946 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3947 i915_gem_gtt_bind_object(obj, obj->cache_level);
3950 obj->pin_mappable |= map_and_fenceable;
3956 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3958 BUG_ON(obj->pin_count == 0);
3959 BUG_ON(!i915_gem_obj_bound_any(obj));
3961 if (--obj->pin_count == 0)
3962 obj->pin_mappable = false;
3966 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3967 struct drm_file *file)
3969 struct drm_i915_gem_pin *args = data;
3970 struct drm_i915_gem_object *obj;
3973 ret = i915_mutex_lock_interruptible(dev);
3977 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3978 if (&obj->base == NULL) {
3983 if (obj->madv != I915_MADV_WILLNEED) {
3984 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3989 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3990 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3996 if (obj->user_pin_count == ULONG_MAX) {
4001 if (obj->user_pin_count == 0) {
4002 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
4007 obj->user_pin_count++;
4008 obj->pin_filp = file;
4010 args->offset = i915_gem_obj_ggtt_offset(obj);
4012 drm_gem_object_unreference(&obj->base);
4014 mutex_unlock(&dev->struct_mutex);
4019 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4020 struct drm_file *file)
4022 struct drm_i915_gem_pin *args = data;
4023 struct drm_i915_gem_object *obj;
4026 ret = i915_mutex_lock_interruptible(dev);
4030 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4031 if (&obj->base == NULL) {
4036 if (obj->pin_filp != file) {
4037 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4042 obj->user_pin_count--;
4043 if (obj->user_pin_count == 0) {
4044 obj->pin_filp = NULL;
4045 i915_gem_object_unpin(obj);
4049 drm_gem_object_unreference(&obj->base);
4051 mutex_unlock(&dev->struct_mutex);
4056 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4057 struct drm_file *file)
4059 struct drm_i915_gem_busy *args = data;
4060 struct drm_i915_gem_object *obj;
4063 ret = i915_mutex_lock_interruptible(dev);
4067 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4068 if (&obj->base == NULL) {
4073 /* Count all active objects as busy, even if they are currently not used
4074 * by the gpu. Users of this interface expect objects to eventually
4075 * become non-busy without any further actions, therefore emit any
4076 * necessary flushes here.
4078 ret = i915_gem_object_flush_active(obj);
4080 args->busy = obj->active;
4082 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4083 args->busy |= intel_ring_flag(obj->ring) << 16;
4086 drm_gem_object_unreference(&obj->base);
4088 mutex_unlock(&dev->struct_mutex);
4093 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4094 struct drm_file *file_priv)
4096 return i915_gem_ring_throttle(dev, file_priv);
4100 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4101 struct drm_file *file_priv)
4103 struct drm_i915_gem_madvise *args = data;
4104 struct drm_i915_gem_object *obj;
4107 switch (args->madv) {
4108 case I915_MADV_DONTNEED:
4109 case I915_MADV_WILLNEED:
4115 ret = i915_mutex_lock_interruptible(dev);
4119 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4120 if (&obj->base == NULL) {
4125 if (obj->pin_count) {
4130 if (obj->madv != __I915_MADV_PURGED)
4131 obj->madv = args->madv;
4133 /* if the object is no longer attached, discard its backing storage */
4134 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4135 i915_gem_object_truncate(obj);
4137 args->retained = obj->madv != __I915_MADV_PURGED;
4140 drm_gem_object_unreference(&obj->base);
4142 mutex_unlock(&dev->struct_mutex);
4146 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4147 const struct drm_i915_gem_object_ops *ops)
4149 INIT_LIST_HEAD(&obj->global_list);
4150 INIT_LIST_HEAD(&obj->ring_list);
4151 INIT_LIST_HEAD(&obj->obj_exec_link);
4152 INIT_LIST_HEAD(&obj->vma_list);
4156 obj->fence_reg = I915_FENCE_REG_NONE;
4157 obj->madv = I915_MADV_WILLNEED;
4158 /* Avoid an unnecessary call to unbind on the first bind. */
4159 obj->map_and_fenceable = true;
4161 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4164 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4165 .get_pages = i915_gem_object_get_pages_gtt,
4166 .put_pages = i915_gem_object_put_pages_gtt,
4169 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4172 struct drm_i915_gem_object *obj;
4173 struct address_space *mapping;
4176 obj = i915_gem_object_alloc(dev);
4180 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4181 i915_gem_object_free(obj);
4185 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4186 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4187 /* 965gm cannot relocate objects above 4GiB. */
4188 mask &= ~__GFP_HIGHMEM;
4189 mask |= __GFP_DMA32;
4192 mapping = file_inode(obj->base.filp)->i_mapping;
4193 mapping_set_gfp_mask(mapping, mask);
4195 i915_gem_object_init(obj, &i915_gem_object_ops);
4197 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4198 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4201 /* On some devices, we can have the GPU use the LLC (the CPU
4202 * cache) for about a 10% performance improvement
4203 * compared to uncached. Graphics requests other than
4204 * display scanout are coherent with the CPU in
4205 * accessing this cache. This means in this mode we
4206 * don't need to clflush on the CPU side, and on the
4207 * GPU side we only need to flush internal caches to
4208 * get data visible to the CPU.
4210 * However, we maintain the display planes as UC, and so
4211 * need to rebind when first used as such.
4213 obj->cache_level = I915_CACHE_LLC;
4215 obj->cache_level = I915_CACHE_NONE;
4217 trace_i915_gem_object_create(obj);
4222 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4224 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4225 struct drm_device *dev = obj->base.dev;
4226 drm_i915_private_t *dev_priv = dev->dev_private;
4227 struct i915_vma *vma, *next;
4229 intel_runtime_pm_get(dev_priv);
4231 trace_i915_gem_object_destroy(obj);
4234 i915_gem_detach_phys_object(dev, obj);
4237 /* NB: 0 or 1 elements */
4238 WARN_ON(!list_empty(&obj->vma_list) &&
4239 !list_is_singular(&obj->vma_list));
4240 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4241 int ret = i915_vma_unbind(vma);
4242 if (WARN_ON(ret == -ERESTARTSYS)) {
4243 bool was_interruptible;
4245 was_interruptible = dev_priv->mm.interruptible;
4246 dev_priv->mm.interruptible = false;
4248 WARN_ON(i915_vma_unbind(vma));
4250 dev_priv->mm.interruptible = was_interruptible;
4254 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4255 * before progressing. */
4257 i915_gem_object_unpin_pages(obj);
4259 if (WARN_ON(obj->pages_pin_count))
4260 obj->pages_pin_count = 0;
4261 i915_gem_object_put_pages(obj);
4262 i915_gem_object_free_mmap_offset(obj);
4263 i915_gem_object_release_stolen(obj);
4267 if (obj->base.import_attach)
4268 drm_prime_gem_destroy(&obj->base, NULL);
4270 drm_gem_object_release(&obj->base);
4271 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4274 i915_gem_object_free(obj);
4276 intel_runtime_pm_put(dev_priv);
4279 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4280 struct i915_address_space *vm)
4282 struct i915_vma *vma;
4283 list_for_each_entry(vma, &obj->vma_list, vma_link)
4290 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4291 struct i915_address_space *vm)
4293 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4295 return ERR_PTR(-ENOMEM);
4297 INIT_LIST_HEAD(&vma->vma_link);
4298 INIT_LIST_HEAD(&vma->mm_list);
4299 INIT_LIST_HEAD(&vma->exec_list);
4303 /* Keep GGTT vmas first to make debug easier */
4304 if (i915_is_ggtt(vm))
4305 list_add(&vma->vma_link, &obj->vma_list);
4307 list_add_tail(&vma->vma_link, &obj->vma_list);
4313 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4314 struct i915_address_space *vm)
4316 struct i915_vma *vma;
4318 vma = i915_gem_obj_to_vma(obj, vm);
4320 vma = __i915_gem_vma_create(obj, vm);
4325 void i915_gem_vma_destroy(struct i915_vma *vma)
4327 WARN_ON(vma->node.allocated);
4329 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4330 if (!list_empty(&vma->exec_list))
4333 list_del(&vma->vma_link);
4339 i915_gem_suspend(struct drm_device *dev)
4341 drm_i915_private_t *dev_priv = dev->dev_private;
4344 mutex_lock(&dev->struct_mutex);
4345 if (dev_priv->ums.mm_suspended)
4348 ret = i915_gpu_idle(dev);
4352 i915_gem_retire_requests(dev);
4354 /* Under UMS, be paranoid and evict. */
4355 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4356 i915_gem_evict_everything(dev);
4358 i915_kernel_lost_context(dev);
4359 i915_gem_cleanup_ringbuffer(dev);
4361 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4362 * We need to replace this with a semaphore, or something.
4363 * And not confound ums.mm_suspended!
4365 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4367 mutex_unlock(&dev->struct_mutex);
4369 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4370 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4371 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4376 mutex_unlock(&dev->struct_mutex);
4380 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4382 struct drm_device *dev = ring->dev;
4383 drm_i915_private_t *dev_priv = dev->dev_private;
4384 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4385 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4388 if (!HAS_L3_DPF(dev) || !remap_info)
4391 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4396 * Note: We do not worry about the concurrent register cacheline hang
4397 * here because no other code should access these registers other than
4398 * at initialization time.
4400 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4401 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4402 intel_ring_emit(ring, reg_base + i);
4403 intel_ring_emit(ring, remap_info[i/4]);
4406 intel_ring_advance(ring);
4411 void i915_gem_init_swizzling(struct drm_device *dev)
4413 drm_i915_private_t *dev_priv = dev->dev_private;
4415 if (INTEL_INFO(dev)->gen < 5 ||
4416 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4419 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4420 DISP_TILE_SURFACE_SWIZZLING);
4425 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4427 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4428 else if (IS_GEN7(dev))
4429 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4430 else if (IS_GEN8(dev))
4431 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4437 intel_enable_blt(struct drm_device *dev)
4442 /* The blitter was dysfunctional on early prototypes */
4443 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4444 DRM_INFO("BLT not supported on this pre-production hardware;"
4445 " graphics performance will be degraded.\n");
4452 static int i915_gem_init_rings(struct drm_device *dev)
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4457 ret = intel_init_render_ring_buffer(dev);
4462 ret = intel_init_bsd_ring_buffer(dev);
4464 goto cleanup_render_ring;
4467 if (intel_enable_blt(dev)) {
4468 ret = intel_init_blt_ring_buffer(dev);
4470 goto cleanup_bsd_ring;
4473 if (HAS_VEBOX(dev)) {
4474 ret = intel_init_vebox_ring_buffer(dev);
4476 goto cleanup_blt_ring;
4480 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4482 goto cleanup_vebox_ring;
4487 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4489 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4491 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4492 cleanup_render_ring:
4493 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4499 i915_gem_init_hw(struct drm_device *dev)
4501 drm_i915_private_t *dev_priv = dev->dev_private;
4504 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4507 if (dev_priv->ellc_size)
4508 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4510 if (IS_HASWELL(dev))
4511 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4512 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4514 if (HAS_PCH_NOP(dev)) {
4515 u32 temp = I915_READ(GEN7_MSG_CTL);
4516 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4517 I915_WRITE(GEN7_MSG_CTL, temp);
4520 i915_gem_init_swizzling(dev);
4522 ret = i915_gem_init_rings(dev);
4526 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4527 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4530 * XXX: There was some w/a described somewhere suggesting loading
4531 * contexts before PPGTT.
4533 ret = i915_gem_context_init(dev);
4535 i915_gem_cleanup_ringbuffer(dev);
4536 DRM_ERROR("Context initialization failed %d\n", ret);
4540 if (dev_priv->mm.aliasing_ppgtt) {
4541 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4543 i915_gem_cleanup_aliasing_ppgtt(dev);
4544 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4551 int i915_gem_init(struct drm_device *dev)
4553 struct drm_i915_private *dev_priv = dev->dev_private;
4556 mutex_lock(&dev->struct_mutex);
4558 if (IS_VALLEYVIEW(dev)) {
4559 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4560 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4561 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4562 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4565 i915_gem_init_global_gtt(dev);
4567 ret = i915_gem_init_hw(dev);
4568 mutex_unlock(&dev->struct_mutex);
4570 i915_gem_cleanup_aliasing_ppgtt(dev);
4574 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4575 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4576 dev_priv->dri1.allow_batchbuffer = 1;
4581 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4583 drm_i915_private_t *dev_priv = dev->dev_private;
4584 struct intel_ring_buffer *ring;
4587 for_each_ring(ring, dev_priv, i)
4588 intel_cleanup_ring_buffer(ring);
4592 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4593 struct drm_file *file_priv)
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4598 if (drm_core_check_feature(dev, DRIVER_MODESET))
4601 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4602 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4603 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4606 mutex_lock(&dev->struct_mutex);
4607 dev_priv->ums.mm_suspended = 0;
4609 ret = i915_gem_init_hw(dev);
4611 mutex_unlock(&dev->struct_mutex);
4615 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4616 mutex_unlock(&dev->struct_mutex);
4618 ret = drm_irq_install(dev);
4620 goto cleanup_ringbuffer;
4625 mutex_lock(&dev->struct_mutex);
4626 i915_gem_cleanup_ringbuffer(dev);
4627 dev_priv->ums.mm_suspended = 1;
4628 mutex_unlock(&dev->struct_mutex);
4634 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4635 struct drm_file *file_priv)
4637 if (drm_core_check_feature(dev, DRIVER_MODESET))
4640 drm_irq_uninstall(dev);
4642 return i915_gem_suspend(dev);
4646 i915_gem_lastclose(struct drm_device *dev)
4650 if (drm_core_check_feature(dev, DRIVER_MODESET))
4653 ret = i915_gem_suspend(dev);
4655 DRM_ERROR("failed to idle hardware: %d\n", ret);
4659 init_ring_lists(struct intel_ring_buffer *ring)
4661 INIT_LIST_HEAD(&ring->active_list);
4662 INIT_LIST_HEAD(&ring->request_list);
4665 static void i915_init_vm(struct drm_i915_private *dev_priv,
4666 struct i915_address_space *vm)
4668 vm->dev = dev_priv->dev;
4669 INIT_LIST_HEAD(&vm->active_list);
4670 INIT_LIST_HEAD(&vm->inactive_list);
4671 INIT_LIST_HEAD(&vm->global_link);
4672 list_add(&vm->global_link, &dev_priv->vm_list);
4676 i915_gem_load(struct drm_device *dev)
4678 drm_i915_private_t *dev_priv = dev->dev_private;
4682 kmem_cache_create("i915_gem_object",
4683 sizeof(struct drm_i915_gem_object), 0,
4687 INIT_LIST_HEAD(&dev_priv->vm_list);
4688 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4690 INIT_LIST_HEAD(&dev_priv->context_list);
4691 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4692 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4693 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4694 for (i = 0; i < I915_NUM_RINGS; i++)
4695 init_ring_lists(&dev_priv->ring[i]);
4696 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4697 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4698 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4699 i915_gem_retire_work_handler);
4700 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4701 i915_gem_idle_work_handler);
4702 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4704 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4706 I915_WRITE(MI_ARB_STATE,
4707 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4710 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4712 /* Old X drivers will take 0-2 for front, back, depth buffers */
4713 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4714 dev_priv->fence_reg_start = 3;
4716 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4717 dev_priv->num_fence_regs = 32;
4718 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4719 dev_priv->num_fence_regs = 16;
4721 dev_priv->num_fence_regs = 8;
4723 /* Initialize fence registers to zero */
4724 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4725 i915_gem_restore_fences(dev);
4727 i915_gem_detect_bit_6_swizzle(dev);
4728 init_waitqueue_head(&dev_priv->pending_flip_queue);
4730 dev_priv->mm.interruptible = true;
4732 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4733 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4734 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4735 register_shrinker(&dev_priv->mm.inactive_shrinker);
4739 * Create a physically contiguous memory object for this object
4740 * e.g. for cursor + overlay regs
4742 static int i915_gem_init_phys_object(struct drm_device *dev,
4743 int id, int size, int align)
4745 drm_i915_private_t *dev_priv = dev->dev_private;
4746 struct drm_i915_gem_phys_object *phys_obj;
4749 if (dev_priv->mm.phys_objs[id - 1] || !size)
4752 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4758 phys_obj->handle = drm_pci_alloc(dev, size, align);
4759 if (!phys_obj->handle) {
4764 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4767 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4775 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4777 drm_i915_private_t *dev_priv = dev->dev_private;
4778 struct drm_i915_gem_phys_object *phys_obj;
4780 if (!dev_priv->mm.phys_objs[id - 1])
4783 phys_obj = dev_priv->mm.phys_objs[id - 1];
4784 if (phys_obj->cur_obj) {
4785 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4789 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4791 drm_pci_free(dev, phys_obj->handle);
4793 dev_priv->mm.phys_objs[id - 1] = NULL;
4796 void i915_gem_free_all_phys_object(struct drm_device *dev)
4800 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4801 i915_gem_free_phys_object(dev, i);
4804 void i915_gem_detach_phys_object(struct drm_device *dev,
4805 struct drm_i915_gem_object *obj)
4807 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4814 vaddr = obj->phys_obj->handle->vaddr;
4816 page_count = obj->base.size / PAGE_SIZE;
4817 for (i = 0; i < page_count; i++) {
4818 struct page *page = shmem_read_mapping_page(mapping, i);
4819 if (!IS_ERR(page)) {
4820 char *dst = kmap_atomic(page);
4821 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4824 drm_clflush_pages(&page, 1);
4826 set_page_dirty(page);
4827 mark_page_accessed(page);
4828 page_cache_release(page);
4831 i915_gem_chipset_flush(dev);
4833 obj->phys_obj->cur_obj = NULL;
4834 obj->phys_obj = NULL;
4838 i915_gem_attach_phys_object(struct drm_device *dev,
4839 struct drm_i915_gem_object *obj,
4843 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4844 drm_i915_private_t *dev_priv = dev->dev_private;
4849 if (id > I915_MAX_PHYS_OBJECT)
4852 if (obj->phys_obj) {
4853 if (obj->phys_obj->id == id)
4855 i915_gem_detach_phys_object(dev, obj);
4858 /* create a new object */
4859 if (!dev_priv->mm.phys_objs[id - 1]) {
4860 ret = i915_gem_init_phys_object(dev, id,
4861 obj->base.size, align);
4863 DRM_ERROR("failed to init phys object %d size: %zu\n",
4864 id, obj->base.size);
4869 /* bind to the object */
4870 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4871 obj->phys_obj->cur_obj = obj;
4873 page_count = obj->base.size / PAGE_SIZE;
4875 for (i = 0; i < page_count; i++) {
4879 page = shmem_read_mapping_page(mapping, i);
4881 return PTR_ERR(page);
4883 src = kmap_atomic(page);
4884 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4885 memcpy(dst, src, PAGE_SIZE);
4888 mark_page_accessed(page);
4889 page_cache_release(page);
4896 i915_gem_phys_pwrite(struct drm_device *dev,
4897 struct drm_i915_gem_object *obj,
4898 struct drm_i915_gem_pwrite *args,
4899 struct drm_file *file_priv)
4901 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4902 char __user *user_data = to_user_ptr(args->data_ptr);
4904 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4905 unsigned long unwritten;
4907 /* The physical object once assigned is fixed for the lifetime
4908 * of the obj, so we can safely drop the lock and continue
4911 mutex_unlock(&dev->struct_mutex);
4912 unwritten = copy_from_user(vaddr, user_data, args->size);
4913 mutex_lock(&dev->struct_mutex);
4918 i915_gem_chipset_flush(dev);
4922 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4924 struct drm_i915_file_private *file_priv = file->driver_priv;
4926 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4928 /* Clean up our request list when the client is going away, so that
4929 * later retire_requests won't dereference our soon-to-be-gone
4932 spin_lock(&file_priv->mm.lock);
4933 while (!list_empty(&file_priv->mm.request_list)) {
4934 struct drm_i915_gem_request *request;
4936 request = list_first_entry(&file_priv->mm.request_list,
4937 struct drm_i915_gem_request,
4939 list_del(&request->client_list);
4940 request->file_priv = NULL;
4942 spin_unlock(&file_priv->mm.lock);
4946 i915_gem_file_idle_work_handler(struct work_struct *work)
4948 struct drm_i915_file_private *file_priv =
4949 container_of(work, typeof(*file_priv), mm.idle_work.work);
4951 atomic_set(&file_priv->rps_wait_boost, false);
4954 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4956 struct drm_i915_file_private *file_priv;
4958 DRM_DEBUG_DRIVER("\n");
4960 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4964 file->driver_priv = file_priv;
4965 file_priv->dev_priv = dev->dev_private;
4967 spin_lock_init(&file_priv->mm.lock);
4968 INIT_LIST_HEAD(&file_priv->mm.request_list);
4969 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4970 i915_gem_file_idle_work_handler);
4972 idr_init(&file_priv->context_idr);
4977 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4979 if (!mutex_is_locked(mutex))
4982 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4983 return mutex->owner == task;
4985 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4990 static unsigned long
4991 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4993 struct drm_i915_private *dev_priv =
4994 container_of(shrinker,
4995 struct drm_i915_private,
4996 mm.inactive_shrinker);
4997 struct drm_device *dev = dev_priv->dev;
4998 struct drm_i915_gem_object *obj;
5000 unsigned long count;
5002 if (!mutex_trylock(&dev->struct_mutex)) {
5003 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5006 if (dev_priv->mm.shrinker_no_lock_stealing)
5013 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5014 if (obj->pages_pin_count == 0)
5015 count += obj->base.size >> PAGE_SHIFT;
5017 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5021 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
5022 count += obj->base.size >> PAGE_SHIFT;
5026 mutex_unlock(&dev->struct_mutex);
5031 /* All the new VM stuff */
5032 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5033 struct i915_address_space *vm)
5035 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5036 struct i915_vma *vma;
5038 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5039 vm = &dev_priv->gtt.base;
5041 BUG_ON(list_empty(&o->vma_list));
5042 list_for_each_entry(vma, &o->vma_list, vma_link) {
5044 return vma->node.start;
5050 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5051 struct i915_address_space *vm)
5053 struct i915_vma *vma;
5055 list_for_each_entry(vma, &o->vma_list, vma_link)
5056 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5062 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5064 struct i915_vma *vma;
5066 list_for_each_entry(vma, &o->vma_list, vma_link)
5067 if (drm_mm_node_allocated(&vma->node))
5073 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5074 struct i915_address_space *vm)
5076 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5077 struct i915_vma *vma;
5079 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5080 vm = &dev_priv->gtt.base;
5082 BUG_ON(list_empty(&o->vma_list));
5084 list_for_each_entry(vma, &o->vma_list, vma_link)
5086 return vma->node.size;
5091 static unsigned long
5092 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5094 struct drm_i915_private *dev_priv =
5095 container_of(shrinker,
5096 struct drm_i915_private,
5097 mm.inactive_shrinker);
5098 struct drm_device *dev = dev_priv->dev;
5099 unsigned long freed;
5102 if (!mutex_trylock(&dev->struct_mutex)) {
5103 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5106 if (dev_priv->mm.shrinker_no_lock_stealing)
5112 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5113 if (freed < sc->nr_to_scan)
5114 freed += __i915_gem_shrink(dev_priv,
5115 sc->nr_to_scan - freed,
5117 if (freed < sc->nr_to_scan)
5118 freed += i915_gem_shrink_all(dev_priv);
5121 mutex_unlock(&dev->struct_mutex);
5126 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5128 struct i915_vma *vma;
5130 if (WARN_ON(list_empty(&obj->vma_list)))
5133 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5134 if (WARN_ON(vma->vm != obj_to_ggtt(obj)))