drivers/clocksource/sh_cmt.c

   1 /*
   2  * SuperH Timer Support - CMT
   3  *
   4  *  Copyright (C) 2008 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_domain.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/sh_timer.h>
  31 #include <linux/slab.h>
  32 #include <linux/spinlock.h>
  33
  34 struct sh_cmt_device;
  35
  36 /*
  37  * The CMT comes in 5 different identified flavours, depending not only on the
  38  * SoC but also on the particular instance. The following table lists the main
  39  * characteristics of those flavours.
  40  *
  41  *                      16B     32B     32B-F   48B     48B-2
  42  * -----------------------------------------------------------------------------
  43  * Channels             2       1/4     1       6       2/8
  44  * Control Width        16      16      16      16      32
  45  * Counter Width        16      32      32      32/48   32/48
  46  * Shared Start/Stop    Y       Y       Y       Y       N
  47  *
  48  * The 48-bit gen2 version has a per-channel start/stop register located in the
  49  * channel registers block. All other versions have a shared start/stop register
  50  * located in the global space.
  51  *
  52  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  53  * infers the start/stop bit position in the control register and the channel
  54  * registers block address. Some CMT instances have a subset of channels
  55  * available, in which case the index in the documentation doesn't match the
  56  * "real" index as implemented in hardware. This is for instance the case with
  57  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  58  * in the documentation but using start/stop bit 5 and having its registers
  59  * block at 0x60.
  60  *
  61  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  62  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  63  */
  64
  65 enum sh_cmt_model {
  66         SH_CMT_16BIT,
  67         SH_CMT_32BIT,
  68         SH_CMT_32BIT_FAST,
  69         SH_CMT_48BIT,
  70         SH_CMT_48BIT_GEN2,
  71 };
  72
  73 struct sh_cmt_info {
  74         enum sh_cmt_model model;
  75
  76         unsigned long width; /* 16 or 32 bit version of hardware block */
  77         unsigned long overflow_bit;
  78         unsigned long clear_bits;
  79
  80         /* callbacks for CMSTR and CMCSR access */
  81         unsigned long (*read_control)(void __iomem *base, unsigned long offs);
  82         void (*write_control)(void __iomem *base, unsigned long offs,
  83                               unsigned long value);
  84
  85         /* callbacks for CMCNT and CMCOR access */
  86         unsigned long (*read_count)(void __iomem *base, unsigned long offs);
  87         void (*write_count)(void __iomem *base, unsigned long offs,
  88                             unsigned long value);
  89 };
  90
  91 struct sh_cmt_channel {
  92         struct sh_cmt_device *cmt;
  93
  94         unsigned int index;     /* Index in the documentation */
  95         unsigned int hwidx;     /* Real hardware index */
  96
  97         void __iomem *iostart;
  98         void __iomem *ioctrl;
  99
 100         unsigned int timer_bit;
 101         unsigned long flags;
 102         unsigned long match_value;
 103         unsigned long next_match_value;
 104         unsigned long max_match_value;
 105         unsigned long rate;
 106         raw_spinlock_t lock;
 107         struct clock_event_device ced;
 108         struct clocksource cs;
 109         unsigned long total_cycles;
 110         bool cs_enabled;
 111 };
 112
 113 struct sh_cmt_device {
 114         struct platform_device *pdev;
 115
 116         const struct sh_cmt_info *info;
 117
 118         void __iomem *mapbase;
 119         struct clk *clk;
 120
 121         raw_spinlock_t lock; /* Protect the shared start/stop register */
 122
 123         struct sh_cmt_channel *channels;
 124         unsigned int num_channels;
 125
 126         bool has_clockevent;
 127         bool has_clocksource;
 128 };
 129
 130 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 131 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 132 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 133 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 134 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 135 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 136 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 137
 138 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 139 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 140 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 141 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 142 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 143 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 144 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 145 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 146 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 147 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 148 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 149 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 150 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 151 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 152 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 153 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 154 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 155 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 156 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 157
 158 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
 159 {
 160         return ioread16(base + (offs << 1));
 161 }
 162
 163 static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
 164 {
 165         return ioread32(base + (offs << 2));
 166 }
 167
 168 static void sh_cmt_write16(void __iomem *base, unsigned long offs,
 169                            unsigned long value)
 170 {
 171         iowrite16(value, base + (offs << 1));
 172 }
 173
 174 static void sh_cmt_write32(void __iomem *base, unsigned long offs,
 175                            unsigned long value)
 176 {
 177         iowrite32(value, base + (offs << 2));
 178 }
 179
 180 static const struct sh_cmt_info sh_cmt_info[] = {
 181         [SH_CMT_16BIT] = {
 182                 .model = SH_CMT_16BIT,
 183                 .width = 16,
 184                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 185                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 186                 .read_control = sh_cmt_read16,
 187                 .write_control = sh_cmt_write16,
 188                 .read_count = sh_cmt_read16,
 189                 .write_count = sh_cmt_write16,
 190         },
 191         [SH_CMT_32BIT] = {
 192                 .model = SH_CMT_32BIT,
 193                 .width = 32,
 194                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 195                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 196                 .read_control = sh_cmt_read16,
 197                 .write_control = sh_cmt_write16,
 198                 .read_count = sh_cmt_read32,
 199                 .write_count = sh_cmt_write32,
 200         },
 201         [SH_CMT_32BIT_FAST] = {
 202                 .model = SH_CMT_32BIT_FAST,
 203                 .width = 32,
 204                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 205                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 206                 .read_control = sh_cmt_read16,
 207                 .write_control = sh_cmt_write16,
 208                 .read_count = sh_cmt_read32,
 209                 .write_count = sh_cmt_write32,
 210         },
 211         [SH_CMT_48BIT] = {
 212                 .model = SH_CMT_48BIT,
 213                 .width = 32,
 214                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 215                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 216                 .read_control = sh_cmt_read32,
 217                 .write_control = sh_cmt_write32,
 218                 .read_count = sh_cmt_read32,
 219                 .write_count = sh_cmt_write32,
 220         },
 221         [SH_CMT_48BIT_GEN2] = {
 222                 .model = SH_CMT_48BIT_GEN2,
 223                 .width = 32,
 224                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 225                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 226                 .read_control = sh_cmt_read32,
 227                 .write_control = sh_cmt_write32,
 228                 .read_count = sh_cmt_read32,
 229                 .write_count = sh_cmt_write32,
 230         },
 231 };
 232
 233 #define CMCSR 0 /* channel register */
 234 #define CMCNT 1 /* channel register */
 235 #define CMCOR 2 /* channel register */
 236
 237 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 238 {
 239         if (ch->iostart)
 240                 return ch->cmt->info->read_control(ch->iostart, 0);
 241         else
 242                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 243 }
 244
 245 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
 246                                       unsigned long value)
 247 {
 248         if (ch->iostart)
 249                 ch->cmt->info->write_control(ch->iostart, 0, value);
 250         else
 251                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 252 }
 253
 254 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 255 {
 256         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 257 }
 258
 259 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
 260                                       unsigned long value)
 261 {
 262         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 263 }
 264
 265 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 266 {
 267         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 268 }
 269
 270 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
 271                                       unsigned long value)
 272 {
 273         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 274 }
 275
 276 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
 277                                       unsigned long value)
 278 {
 279         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 280 }
 281
 282 static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
 283                                         int *has_wrapped)
 284 {
 285         unsigned long v1, v2, v3;
 286         int o1, o2;
 287
 288         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 289
 290         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 291         do {
 292                 o2 = o1;
 293                 v1 = sh_cmt_read_cmcnt(ch);
 294                 v2 = sh_cmt_read_cmcnt(ch);
 295                 v3 = sh_cmt_read_cmcnt(ch);
 296                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 297         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 298                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 299
 300         *has_wrapped = o1;
 301         return v2;
 302 }
 303
 304 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 305 {
 306         unsigned long flags, value;
 307
 308         /* start stop register shared by multiple timer channels */
 309         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 310         value = sh_cmt_read_cmstr(ch);
 311
 312         if (start)
 313                 value |= 1 << ch->timer_bit;
 314         else
 315                 value &= ~(1 << ch->timer_bit);
 316
 317         sh_cmt_write_cmstr(ch, value);
 318         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 319 }
 320
 321 static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
 322 {
 323         int k, ret;
 324
 325         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 326         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 327
 328         /* enable clock */
 329         ret = clk_enable(ch->cmt->clk);
 330         if (ret) {
 331                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 332                         ch->index);
 333                 goto err0;
 334         }
 335
 336         /* make sure channel is disabled */
 337         sh_cmt_start_stop_ch(ch, 0);
 338
 339         /* configure channel, periodic mode and maximum timeout */
 340         if (ch->cmt->info->width == 16) {
 341                 *rate = clk_get_rate(ch->cmt->clk) / 512;
 342                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 343                                    SH_CMT16_CMCSR_CKS512);
 344         } else {
 345                 *rate = clk_get_rate(ch->cmt->clk) / 8;
 346                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 347                                    SH_CMT32_CMCSR_CMTOUT_IE |
 348                                    SH_CMT32_CMCSR_CMR_IRQ |
 349                                    SH_CMT32_CMCSR_CKS_RCLK8);
 350         }
 351
 352         sh_cmt_write_cmcor(ch, 0xffffffff);
 353         sh_cmt_write_cmcnt(ch, 0);
 354
 355         /*
 356          * According to the sh73a0 user's manual, as CMCNT can be operated
 357          * only by the RCLK (Pseudo 32 KHz), there's one restriction on
 358          * modifying CMCNT register; two RCLK cycles are necessary before
 359          * this register is either read or any modification of the value
 360          * it holds is reflected in the LSI's actual operation.
 361          *
 362          * While at it, we're supposed to clear out the CMCNT as of this
 363          * moment, so make sure it's processed properly here.  This will
 364          * take RCLKx2 at maximum.
 365          */
 366         for (k = 0; k < 100; k++) {
 367                 if (!sh_cmt_read_cmcnt(ch))
 368                         break;
 369                 udelay(1);
 370         }
 371
 372         if (sh_cmt_read_cmcnt(ch)) {
 373                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 374                         ch->index);
 375                 ret = -ETIMEDOUT;
 376                 goto err1;
 377         }
 378
 379         /* enable channel */
 380         sh_cmt_start_stop_ch(ch, 1);
 381         return 0;
 382  err1:
 383         /* stop clock */
 384         clk_disable(ch->cmt->clk);
 385
 386  err0:
 387         return ret;
 388 }
 389
 390 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 391 {
 392         /* disable channel */
 393         sh_cmt_start_stop_ch(ch, 0);
 394
 395         /* disable interrupts in CMT block */
 396         sh_cmt_write_cmcsr(ch, 0);
 397
 398         /* stop clock */
 399         clk_disable(ch->cmt->clk);
 400
 401         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 402         pm_runtime_put(&ch->cmt->pdev->dev);
 403 }
 404
 405 /* private flags */
 406 #define FLAG_CLOCKEVENT (1 << 0)
 407 #define FLAG_CLOCKSOURCE (1 << 1)
 408 #define FLAG_REPROGRAM (1 << 2)
 409 #define FLAG_SKIPEVENT (1 << 3)
 410 #define FLAG_IRQCONTEXT (1 << 4)
 411
 412 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 413                                               int absolute)
 414 {
 415         unsigned long new_match;
 416         unsigned long value = ch->next_match_value;
 417         unsigned long delay = 0;
 418         unsigned long now = 0;
 419         int has_wrapped;
 420
 421         now = sh_cmt_get_counter(ch, &has_wrapped);
 422         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 423
 424         if (has_wrapped) {
 425                 /* we're competing with the interrupt handler.
 426                  *  -> let the interrupt handler reprogram the timer.
 427                  *  -> interrupt number two handles the event.
 428                  */
 429                 ch->flags |= FLAG_SKIPEVENT;
 430                 return;
 431         }
 432
 433         if (absolute)
 434                 now = 0;
 435
 436         do {
 437                 /* reprogram the timer hardware,
 438                  * but don't save the new match value yet.
 439                  */
 440                 new_match = now + value + delay;
 441                 if (new_match > ch->max_match_value)
 442                         new_match = ch->max_match_value;
 443
 444                 sh_cmt_write_cmcor(ch, new_match);
 445
 446                 now = sh_cmt_get_counter(ch, &has_wrapped);
 447                 if (has_wrapped && (new_match > ch->match_value)) {
 448                         /* we are changing to a greater match value,
 449                          * so this wrap must be caused by the counter
 450                          * matching the old value.
 451                          * -> first interrupt reprograms the timer.
 452                          * -> interrupt number two handles the event.
 453                          */
 454                         ch->flags |= FLAG_SKIPEVENT;
 455                         break;
 456                 }
 457
 458                 if (has_wrapped) {
 459                         /* we are changing to a smaller match value,
 460                          * so the wrap must be caused by the counter
 461                          * matching the new value.
 462                          * -> save programmed match value.
 463                          * -> let isr handle the event.
 464                          */
 465                         ch->match_value = new_match;
 466                         break;
 467                 }
 468
 469                 /* be safe: verify hardware settings */
 470                 if (now < new_match) {
 471                         /* timer value is below match value, all good.
 472                          * this makes sure we won't miss any match events.
 473                          * -> save programmed match value.
 474                          * -> let isr handle the event.
 475                          */
 476                         ch->match_value = new_match;
 477                         break;
 478                 }
 479
 480                 /* the counter has reached a value greater
 481                  * than our new match value. and since the
 482                  * has_wrapped flag isn't set we must have
 483                  * programmed a too close event.
 484                  * -> increase delay and retry.
 485                  */
 486                 if (delay)
 487                         delay <<= 1;
 488                 else
 489                         delay = 1;
 490
 491                 if (!delay)
 492                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 493                                  ch->index);
 494
 495         } while (delay);
 496 }
 497
 498 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 499 {
 500         if (delta > ch->max_match_value)
 501                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 502                          ch->index);
 503
 504         ch->next_match_value = delta;
 505         sh_cmt_clock_event_program_verify(ch, 0);
 506 }
 507
 508 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 509 {
 510         unsigned long flags;
 511
 512         raw_spin_lock_irqsave(&ch->lock, flags);
 513         __sh_cmt_set_next(ch, delta);
 514         raw_spin_unlock_irqrestore(&ch->lock, flags);
 515 }
 516
 517 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 518 {
 519         struct sh_cmt_channel *ch = dev_id;
 520
 521         /* clear flags */
 522         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 523                            ch->cmt->info->clear_bits);
 524
 525         /* update clock source counter to begin with if enabled
 526          * the wrap flag should be cleared by the timer specific
 527          * isr before we end up here.
 528          */
 529         if (ch->flags & FLAG_CLOCKSOURCE)
 530                 ch->total_cycles += ch->match_value + 1;
 531
 532         if (!(ch->flags & FLAG_REPROGRAM))
 533                 ch->next_match_value = ch->max_match_value;
 534
 535         ch->flags |= FLAG_IRQCONTEXT;
 536
 537         if (ch->flags & FLAG_CLOCKEVENT) {
 538                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 539                         if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
 540                                 ch->next_match_value = ch->max_match_value;
 541                                 ch->flags |= FLAG_REPROGRAM;
 542                         }
 543
 544                         ch->ced.event_handler(&ch->ced);
 545                 }
 546         }
 547
 548         ch->flags &= ~FLAG_SKIPEVENT;
 549
 550         if (ch->flags & FLAG_REPROGRAM) {
 551                 ch->flags &= ~FLAG_REPROGRAM;
 552                 sh_cmt_clock_event_program_verify(ch, 1);
 553
 554                 if (ch->flags & FLAG_CLOCKEVENT)
 555                         if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
 556                             || (ch->match_value == ch->next_match_value))
 557                                 ch->flags &= ~FLAG_REPROGRAM;
 558         }
 559
 560         ch->flags &= ~FLAG_IRQCONTEXT;
 561
 562         return IRQ_HANDLED;
 563 }
 564
 565 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 566 {
 567         int ret = 0;
 568         unsigned long flags;
 569
 570         raw_spin_lock_irqsave(&ch->lock, flags);
 571
 572         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 573                 ret = sh_cmt_enable(ch, &ch->rate);
 574
 575         if (ret)
 576                 goto out;
 577         ch->flags |= flag;
 578
 579         /* setup timeout if no clockevent */
 580         if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
 581                 __sh_cmt_set_next(ch, ch->max_match_value);
 582  out:
 583         raw_spin_unlock_irqrestore(&ch->lock, flags);
 584
 585         return ret;
 586 }
 587
 588 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 589 {
 590         unsigned long flags;
 591         unsigned long f;
 592
 593         raw_spin_lock_irqsave(&ch->lock, flags);
 594
 595         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 596         ch->flags &= ~flag;
 597
 598         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
 599                 sh_cmt_disable(ch);
 600
 601         /* adjust the timeout to maximum if only clocksource left */
 602         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 603                 __sh_cmt_set_next(ch, ch->max_match_value);
 604
 605         raw_spin_unlock_irqrestore(&ch->lock, flags);
 606 }
 607
 608 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 609 {
 610         return container_of(cs, struct sh_cmt_channel, cs);
 611 }
 612
 613 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
 614 {
 615         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 616         unsigned long flags, raw;
 617         unsigned long value;
 618         int has_wrapped;
 619
 620         raw_spin_lock_irqsave(&ch->lock, flags);
 621         value = ch->total_cycles;
 622         raw = sh_cmt_get_counter(ch, &has_wrapped);
 623
 624         if (unlikely(has_wrapped))
 625                 raw += ch->match_value + 1;
 626         raw_spin_unlock_irqrestore(&ch->lock, flags);
 627
 628         return value + raw;
 629 }
 630
 631 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 632 {
 633         int ret;
 634         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 635
 636         WARN_ON(ch->cs_enabled);
 637
 638         ch->total_cycles = 0;
 639
 640         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 641         if (!ret) {
 642                 __clocksource_updatefreq_hz(cs, ch->rate);
 643                 ch->cs_enabled = true;
 644         }
 645         return ret;
 646 }
 647
 648 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 649 {
 650         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 651
 652         WARN_ON(!ch->cs_enabled);
 653
 654         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 655         ch->cs_enabled = false;
 656 }
 657
 658 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 659 {
 660         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 661
 662         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 663         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 664 }
 665
 666 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 667 {
 668         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 669
 670         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 671         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 672 }
 673
 674 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 675                                        const char *name)
 676 {
 677         struct clocksource *cs = &ch->cs;
 678
 679         cs->name = name;
 680         cs->rating = 125;
 681         cs->read = sh_cmt_clocksource_read;
 682         cs->enable = sh_cmt_clocksource_enable;
 683         cs->disable = sh_cmt_clocksource_disable;
 684         cs->suspend = sh_cmt_clocksource_suspend;
 685         cs->resume = sh_cmt_clocksource_resume;
 686         cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
 687         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 688
 689         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 690                  ch->index);
 691
 692         /* Register with dummy 1 Hz value, gets updated in ->enable() */
 693         clocksource_register_hz(cs, 1);
 694         return 0;
 695 }
 696
 697 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 698 {
 699         return container_of(ced, struct sh_cmt_channel, ced);
 700 }
 701
 702 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 703 {
 704         struct clock_event_device *ced = &ch->ced;
 705
 706         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 707
 708         /* TODO: calculate good shift from rate and counter bit width */
 709
 710         ced->shift = 32;
 711         ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift);
 712         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 713         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 714
 715         if (periodic)
 716                 sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1);
 717         else
 718                 sh_cmt_set_next(ch, ch->max_match_value);
 719 }
 720
 721 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
 722                                     struct clock_event_device *ced)
 723 {
 724         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 725
 726         /* deal with old setting first */
 727         switch (ced->mode) {
 728         case CLOCK_EVT_MODE_PERIODIC:
 729         case CLOCK_EVT_MODE_ONESHOT:
 730                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 731                 break;
 732         default:
 733                 break;
 734         }
 735
 736         switch (mode) {
 737         case CLOCK_EVT_MODE_PERIODIC:
 738                 dev_info(&ch->cmt->pdev->dev,
 739                          "ch%u: used for periodic clock events\n", ch->index);
 740                 sh_cmt_clock_event_start(ch, 1);
 741                 break;
 742         case CLOCK_EVT_MODE_ONESHOT:
 743                 dev_info(&ch->cmt->pdev->dev,
 744                          "ch%u: used for oneshot clock events\n", ch->index);
 745                 sh_cmt_clock_event_start(ch, 0);
 746                 break;
 747         case CLOCK_EVT_MODE_SHUTDOWN:
 748         case CLOCK_EVT_MODE_UNUSED:
 749                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 750                 break;
 751         default:
 752                 break;
 753         }
 754 }
 755
 756 static int sh_cmt_clock_event_next(unsigned long delta,
 757                                    struct clock_event_device *ced)
 758 {
 759         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 760
 761         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 762         if (likely(ch->flags & FLAG_IRQCONTEXT))
 763                 ch->next_match_value = delta - 1;
 764         else
 765                 sh_cmt_set_next(ch, delta - 1);
 766
 767         return 0;
 768 }
 769
 770 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 771 {
 772         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 773
 774         pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
 775         clk_unprepare(ch->cmt->clk);
 776 }
 777
 778 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 779 {
 780         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 781
 782         clk_prepare(ch->cmt->clk);
 783         pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
 784 }
 785
 786 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 787                                       const char *name)
 788 {
 789         struct clock_event_device *ced = &ch->ced;
 790         int irq;
 791         int ret;
 792
 793         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 794         if (irq < 0) {
 795                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
 796                         ch->index);
 797                 return irq;
 798         }
 799
 800         ret = request_irq(irq, sh_cmt_interrupt,
 801                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 802                           dev_name(&ch->cmt->pdev->dev), ch);
 803         if (ret) {
 804                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 805                         ch->index, irq);
 806                 return ret;
 807         }
 808
 809         ced->name = name;
 810         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 811         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 812         ced->rating = 125;
 813         ced->cpumask = cpu_possible_mask;
 814         ced->set_next_event = sh_cmt_clock_event_next;
 815         ced->set_mode = sh_cmt_clock_event_mode;
 816         ced->suspend = sh_cmt_clock_event_suspend;
 817         ced->resume = sh_cmt_clock_event_resume;
 818
 819         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 820                  ch->index);
 821         clockevents_register_device(ced);
 822
 823         return 0;
 824 }
 825
 826 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 827                            bool clockevent, bool clocksource)
 828 {
 829         int ret;
 830
 831         if (clockevent) {
 832                 ch->cmt->has_clockevent = true;
 833                 ret = sh_cmt_register_clockevent(ch, name);
 834                 if (ret < 0)
 835                         return ret;
 836         }
 837
 838         if (clocksource) {
 839                 ch->cmt->has_clocksource = true;
 840                 sh_cmt_register_clocksource(ch, name);
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 847                                 unsigned int hwidx, bool clockevent,
 848                                 bool clocksource, struct sh_cmt_device *cmt)
 849 {
 850         int ret;
 851
 852         /* Skip unused channels. */
 853         if (!clockevent && !clocksource)
 854                 return 0;
 855
 856         ch->cmt = cmt;
 857         ch->index = index;
 858         ch->hwidx = hwidx;
 859
 860         /*
 861          * Compute the address of the channel control register block. For the
 862          * timers with a per-channel start/stop register, compute its address
 863          * as well.
 864          */
 865         switch (cmt->info->model) {
 866         case SH_CMT_16BIT:
 867                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 868                 break;
 869         case SH_CMT_32BIT:
 870         case SH_CMT_48BIT:
 871                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 872                 break;
 873         case SH_CMT_32BIT_FAST:
 874                 /*
 875                  * The 32-bit "fast" timer has a single channel at hwidx 5 but
 876                  * is located at offset 0x40 instead of 0x60 for some reason.
 877                  */
 878                 ch->ioctrl = cmt->mapbase + 0x40;
 879                 break;
 880         case SH_CMT_48BIT_GEN2:
 881                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 882                 ch->ioctrl = ch->iostart + 0x10;
 883                 break;
 884         }
 885
 886         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 887                 ch->max_match_value = ~0;
 888         else
 889                 ch->max_match_value = (1 << cmt->info->width) - 1;
 890
 891         ch->match_value = ch->max_match_value;
 892         raw_spin_lock_init(&ch->lock);
 893
 894         ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
 895
 896         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 897                               clockevent, clocksource);
 898         if (ret) {
 899                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 900                         ch->index);
 901                 return ret;
 902         }
 903         ch->cs_enabled = false;
 904
 905         return 0;
 906 }
 907
 908 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 909 {
 910         struct resource *mem;
 911
 912         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 913         if (!mem) {
 914                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 915                 return -ENXIO;
 916         }
 917
 918         cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
 919         if (cmt->mapbase == NULL) {
 920                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 921                 return -ENXIO;
 922         }
 923
 924         return 0;
 925 }
 926
 927 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 928 {
 929         struct sh_timer_config *cfg = pdev->dev.platform_data;
 930         const struct platform_device_id *id = pdev->id_entry;
 931         unsigned int mask;
 932         unsigned int i;
 933         int ret;
 934
 935         memset(cmt, 0, sizeof(*cmt));
 936         cmt->pdev = pdev;
 937         raw_spin_lock_init(&cmt->lock);
 938
 939         if (!cfg) {
 940                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 941                 return -ENXIO;
 942         }
 943
 944         cmt->info = (const struct sh_cmt_info *)id->driver_data;
 945
 946         /* Get hold of clock. */
 947         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 948         if (IS_ERR(cmt->clk)) {
 949                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
 950                 return PTR_ERR(cmt->clk);
 951         }
 952
 953         ret = clk_prepare(cmt->clk);
 954         if (ret < 0)
 955                 goto err_clk_put;
 956
 957         /* Map the memory resource(s). */
 958         ret = sh_cmt_map_memory(cmt);
 959         if (ret < 0)
 960                 goto err_clk_unprepare;
 961
 962         /* Allocate and setup the channels. */
 963         cmt->num_channels = hweight8(cfg->channels_mask);
 964
 965         cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
 966                                 GFP_KERNEL);
 967         if (cmt->channels == NULL) {
 968                 ret = -ENOMEM;
 969                 goto err_unmap;
 970         }
 971
 972         /*
 973          * Use the first channel as a clock event device and the second channel
 974          * as a clock source. If only one channel is available use it for both.
 975          */
 976         for (i = 0, mask = cfg->channels_mask; i < cmt->num_channels; ++i) {
 977                 unsigned int hwidx = ffs(mask) - 1;
 978                 bool clocksource = i == 1 || cmt->num_channels == 1;
 979                 bool clockevent = i == 0;
 980
 981                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
 982                                            clockevent, clocksource, cmt);
 983                 if (ret < 0)
 984                         goto err_unmap;
 985
 986                 mask &= ~(1 << hwidx);
 987         }
 988
 989         platform_set_drvdata(pdev, cmt);
 990
 991         return 0;
 992
 993 err_unmap:
 994         kfree(cmt->channels);
 995         iounmap(cmt->mapbase);
 996 err_clk_unprepare:
 997         clk_unprepare(cmt->clk);
 998 err_clk_put:
 999         clk_put(cmt->clk);
1000         return ret;
1001 }
1002
1003 static int sh_cmt_probe(struct platform_device *pdev)
1004 {
1005         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1006         int ret;
1007
1008         if (!is_early_platform_device(pdev)) {
1009                 pm_runtime_set_active(&pdev->dev);
1010                 pm_runtime_enable(&pdev->dev);
1011         }
1012
1013         if (cmt) {
1014                 dev_info(&pdev->dev, "kept as earlytimer\n");
1015                 goto out;
1016         }
1017
1018         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1019         if (cmt == NULL)
1020                 return -ENOMEM;
1021
1022         ret = sh_cmt_setup(cmt, pdev);
1023         if (ret) {
1024                 kfree(cmt);
1025                 pm_runtime_idle(&pdev->dev);
1026                 return ret;
1027         }
1028         if (is_early_platform_device(pdev))
1029                 return 0;
1030
1031  out:
1032         if (cmt->has_clockevent || cmt->has_clocksource)
1033                 pm_runtime_irq_safe(&pdev->dev);
1034         else
1035                 pm_runtime_idle(&pdev->dev);
1036
1037         return 0;
1038 }
1039
1040 static int sh_cmt_remove(struct platform_device *pdev)
1041 {
1042         return -EBUSY; /* cannot unregister clockevent and clocksource */
1043 }
1044
1045 static const struct platform_device_id sh_cmt_id_table[] = {
1046         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
1047         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
1048         { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
1049         { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] },
1050         { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] },
1051         { }
1052 };
1053 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
1054
1055 static struct platform_driver sh_cmt_device_driver = {
1056         .probe          = sh_cmt_probe,
1057         .remove         = sh_cmt_remove,
1058         .driver         = {
1059                 .name   = "sh_cmt",
1060         },
1061         .id_table       = sh_cmt_id_table,
1062 };
1063
1064 static int __init sh_cmt_init(void)
1065 {
1066         return platform_driver_register(&sh_cmt_device_driver);
1067 }
1068
1069 static void __exit sh_cmt_exit(void)
1070 {
1071         platform_driver_unregister(&sh_cmt_device_driver);
1072 }
1073
1074 early_platform_init("earlytimer", &sh_cmt_device_driver);
1075 subsys_initcall(sh_cmt_init);
1076 module_exit(sh_cmt_exit);
1077
1078 MODULE_AUTHOR("Magnus Damm");
1079 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1080 MODULE_LICENSE("GPL v2");