2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 //only used in fdl2 .in uart download, the debug infors from serial will break the download process.
24 #define CONFIG_FDL2_PRINT 0
25 #define BOOT_NATIVE_LINUX 1
26 #define BOOT_NATIVE_LINUX_MODEM 1
27 #define CALIBRATION_FLAG 0x89FFFC00
28 #define CALIBRATION_FLAG_WCDMA 0x89FFFC00
29 #define CONFIG_SILENT_CONSOLE
30 #define CONFIG_GPIOLIB 1
33 #define CONFIG_SDRAMDISK
35 #define U_BOOT_SPRD_VER 1
36 /*#define SPRD_EVM_TAG_ON 1*/
37 #ifdef SPRD_EVM_TAG_ON
38 #define SPRD_EVM_ADDR_START 0x00026000
39 #define SPRD_EVM_TAG(_x) (*(((unsigned long *)SPRD_EVM_ADDR_START)+_x) = *(volatile unsigned long *)0x87003004)
41 #define CONFIG_L2_OFF 1
45 #define CONFIG_YAFFS2 1
47 #define BOOT_PART "boot"
48 //#define BOOT_PART "kernel"
49 #define RECOVERY_PART "recovery"
51 * SPREADTRUM BIGPHONE board - SoC Configuration
54 #define CONFIG_SPX15_WCDMA
57 #define CONFIG_AUTODLOADER
58 #define CONFIG_SP8830WCN
60 #define CHIP_ENDIAN_LITTLE
61 #define _LITTLE_ENDIAN 1
63 #define CONFIG_RAM512M
65 #define CONFIG_EMMC_BOOT
67 #ifdef CONFIG_EMMC_BOOT
68 #define EMMC_SECTOR_SIZE 512
71 #define CONFIG_FS_EXT4
72 #define CONFIG_EXT4_WRITE
73 #define CONFIG_CMD_EXT4
74 #define CONFIG_CMD_EXT4_WRITE
76 //#define CONFIG_TIGER_MMC
77 #define CONFIG_UEFI_PARTITION
78 #define CONFIG_EFI_PARTITION
79 #define CONFIG_EXT4_SPARSE_DOWNLOAD
80 //#define CONFIG_EMMC_SPL
81 #define CONFIG_SYS_EMMC_U_BOOT_SECTOR_NUM ((CONFIG_SYS_NAND_U_BOOT_SIZE+EMMC_SECTOR_SIZE-1)/EMMC_SECTOR_SIZE)
87 #define CONFIG_CMD_MMC
89 #define CONFIG_CMD_FAT 1
90 #define CONFIG_FAT_WRITE 1
92 #define CONFIG_GENERIC_MMC 1
93 #define CONFIG_SDHCI 1
94 #define CONFIG_SDHCI_CTRL_NO_HISPD 1 /* disable high speed control */
95 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
96 #define CONFIG_MMC_SDMA 1
97 #define CONFIG_MV_SDHCI 1
98 #define CONFIG_DOS_PARTITION 1
99 #define CONFIG_EFI_PARTITION 1
100 #define CONFIG_SYS_MMC_NUM 1
101 #define CONFIG_SYS_MMC_BASE {0x20600000}
102 #define CONFIG_SYS_SD_BASE 0x20300000
105 #define BB_DRAM_TYPE_256MB_32BIT
107 #define CONFIG_SYS_HZ 1000
108 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
110 //#define CONFIG_SYS_HUSH_PARSER
112 #ifdef CONFIG_SYS_HUSH_PARSER
113 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
116 #define FIXNV_SIZE (256 * 1024)
117 #define MODEM_SIZE (0x800000)
118 #define DSP_SIZE (0x200000) /* 3968K */
119 #define VMJALUNA_SIZE (0x64000) /* 400K */
120 #define RUNTIMENV_SIZE (384 * 1024)
121 #define CONFIG_SPL_LOAD_LEN (0x6000)
124 /*#define CMDLINE_NEED_CONV */
126 #define WATCHDOG_LOAD_VALUE 0x4000
127 #define CONFIG_SYS_STACK_SIZE 0x400
128 //#define CONFIG_SYS_TEXT_BASZE 0x80f00000
130 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
132 /* NAND BOOT is the only boot method */
133 #define CONFIG_NAND_U_BOOT
134 #define DYNAMIC_CRC_TABLE
135 /* Start copying real U-boot from the second page */
136 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
137 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x8A000
138 #define RAM_TYPPE_IS_SDRAM 0
139 //#define FPGA_TRACE_DOWNLOAD //for download image from trace
141 /* Load U-Boot to this address */
142 #define CONFIG_SYS_NAND_U_BOOT_DST 0x8f800000
143 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
144 #define CONFIG_SYS_SDRAM_BASE 0x80000000
145 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + 256*1024*1024)
147 #ifdef CONFIG_NAND_SPL
148 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_END - 0x40000)
151 #define CONFIG_MMU_TABLE_ADDR (0x00020000)
152 #define CONFIG_SYS_INIT_SP_ADDR \
153 (CONFIG_SYS_SDRAM_END - 0x10000 - GENERATED_GBL_DATA_SIZE)
155 #define CONFIG_SKIP_LOWLEVEL_INIT
158 #define CONFIG_HW_WATCHDOG
159 //#define CONFIG_AUTOBOOT //used for FPGA test, auto boot other image
160 //#define CONFIG_DISPLAY_CPUINFO
162 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
163 #define CONFIG_SETUP_MEMORY_TAGS 1
164 #define CONFIG_INITRD_TAG 1
170 #define CONFIG_SYS_MALLOC_LEN (2 << 20) /* 1 MiB */
172 * Board has 2 32MB banks of DRAM but there is a bug when using
173 * both so only the first is configured
175 #define CONFIG_NR_DRAM_BANKS 1
177 #define PHYS_SDRAM_1 0x80000000
178 #define PHYS_SDRAM_1_SIZE 0x10000000
179 #if (CONFIG_NR_DRAM_BANKS == 2)
180 #define PHYS_SDRAM_2 0x90000000
181 #define PHYS_SDRAM_2_SIZE 0x10000000
184 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
185 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
186 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
191 #define CONFIG_SPRD_UART 1
192 #define CONFIG_SYS_SC8800X_UART1 1
193 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
194 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
195 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
196 #define CONFIG_SPRD_SPI
197 #define CONFIG_SPRD_I2C
198 #define CONFIG_SC8830_I2C
200 * Flash & Environment
202 /* No NOR flash present */
203 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
204 #define CONFIG_SYS_NO_FLASH 1
205 #define CONFIG_ENV_IS_NOWHERE
206 #define CONFIG_ENV_SIZE (128 * 1024)
208 #define CONFIG_ENV_IS_IN_NAND
209 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
210 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
214 #define CONFIG_CLK_PARA
215 //#define CONFIG_FPGA
217 #ifndef CONFIG_CLK_PARA
220 #define MAGIC_HEADER 0x5555AAAA
221 #define MAGIC_END 0xAAAA5555
222 #define CONFIG_PARA_VERSION 1
223 #define CLK_CA7_CORE ARM_CLK_1000M
224 #define CLK_CA7_AXI ARM_CLK_500M
225 #define CLK_CA7_DGB ARM_CLK_200M
226 #define CLK_CA7_AHB AHB_CLK_192M
227 #define CLK_CA7_APB APB_CLK_64M
228 #define CLK_PUB_AHB PUB_AHB_CLK_153_6M
229 #define CLK_AON_APB AON_APB_CLK_128M
230 #define DDR_FREQ 333000000
231 #define DCDC_ARM 1200
232 #define DCDC_CORE 1100
233 #define CONFIG_VOL_PARA
235 //---these three macro below,only one can be open
240 //#define DDR_TYPE DRAM_LPDDR2_2CS_8G_X32
241 #define DDR_TYPE DRAM_LPDDR2_1CS_4G_X32
242 //#define DDR_TYPE DRAM_LPDDR2_1CS_8G_X32
243 //#define DDR_TYPE DRAM_LPDDR2_2CS_16G_X32
244 //#define DDR_TYPE DRAM_DDR3_1CS_2G_X8_4P
245 //#define DDR_TYPE DRAM_DDR3_1CS_4G_X16_2P
247 #define DDR3_DLL_ON TRUE
249 #define DDR_APB_CLK 128
250 #define DDR_DFS_SUPPORT
251 #define DDR_DFS_VAL_BASE 0X1c00
253 //#define DDR_SCAN_SUPPORT
254 #define MEM_IO_DS LPDDR2_DS_40R
256 #define PUBL_LPDDR1_DS PUBL_LPDDR1_DS_48OHM
257 #define PUBL_LPDDR2_DS PUBL_LPDDR2_DS_40OHM
258 #define PUBL_DDR3_DS PUBL_DDR3_DS_34OHM
261 #define CONFIG_NAND_DOLPHIN
262 #define CONFIG_SPRD_NAND_REGS_BASE (0x20B00000)
263 #define CONFIG_SYS_MAX_NAND_DEVICE 1
264 #define CONFIG_SYS_NAND_BASE (0x20B00000)
265 //#define CONFIG_JFFS2_NAND
266 //#define CONFIG_SPRD_NAND_HWECC
267 #define CONFIG_SYS_NAND_HW_ECC
268 #define CONFIG_SYS_NAND_LARGEPAGE
269 //#define CONFIG_SYS_NAND_5_ADDR_CYCLE
271 #define CONFIG_SYS_64BIT_VSPRINTF
273 #define CONFIG_CMD_MTDPARTS
274 #define CONFIG_MTD_PARTITIONS
275 #define CONFIG_MTD_DEVICE
276 #define CONFIG_CMD_UBI
277 #define CONFIG_RBTREE
279 /* U-Boot general configuration */
280 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
281 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
282 /* Print buffer sz */
283 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
284 sizeof(CONFIG_SYS_PROMPT) + 16)
285 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
286 /* Boot Argument Buffer Size */
287 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
288 #define CONFIG_CMDLINE_EDITING
289 #define CONFIG_SYS_LONGHELP
291 /* support OS choose */
292 #undef CONFIG_BOOTM_NETBSD
293 #undef CONFIG_BOOTM_RTEMS
295 /* U-Boot commands */
296 #include <config_cmd_default.h>
297 #define CONFIG_CMD_NAND
298 #undef CONFIG_CMD_FPGA
299 #undef CONFIG_CMD_LOADS
300 #undef CONFIG_CMD_NET
301 #undef CONFIG_CMD_NFS
302 #undef CONFIG_CMD_SETGETDCR
304 #define CONFIG_ENV_OVERWRITE
306 #ifdef SPRD_EVM_TAG_ON
307 #define CONFIG_BOOTDELAY 0
309 #define CONFIG_BOOTDELAY 0
310 #define CONFIG_ZERO_BOOTDELAY_CHECK
313 #define CONFIG_LOADADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - 4*1024*1024) /* loadaddr env var */
314 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
316 #define xstr(s) str(s)
319 #define MTDIDS_DEFAULT "nand0=sprd-nand"
320 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:256k(spl),2m(2ndbl),256k(tdmodem),256k(tddsp),256k(tdfixnv1),256k(tdruntimenv),256k(wmodem),256k(wdsp),256k(wfixnv1),256k(wruntimenv1),256k(prodinfo1),256k(prodinfo3),1024k(logo),1024k(fastbootlogo),10m(boot),300m(system),150m(cache),10m(recovery),256k(misc),256k(sd),512k(userdata)"
321 #define CONFIG_BOOTARGS "mem=512M loglevel=1 console=ttyS1,115200n8 init=/init " MTDPARTS_DEFAULT
322 #define COPY_LINUX_KERNEL_SIZE (0x600000)
323 #define LINUX_INITRD_NAME "modem"
325 #define CONFIG_BOOTCOMMAND "cboot normal"
326 #define CONFIG_EXTRA_ENV_SETTINGS ""
328 #ifdef CONFIG_CMD_NET
329 #define CONFIG_IPADDR 192.168.10.2
330 #define CONFIG_SERVERIP 192.168.10.5
331 #define CONFIG_NETMASK 255.255.255.0
332 #define CONFIG_USBNET_DEVADDR 26:03:ee:00:87:9f
333 #define CONFIG_USBNET_HOSTADDR 9a:04:c7:d6:30:d0
336 #define CONFIG_NET_MULTI
337 #define CONFIG_CMD_DNS
338 #define CONFIG_CMD_NFS
339 #define CONFIG_CMD_RARP
340 #define CONFIG_CMD_PING
341 /*#define CONFIG_CMD_SNTP */
344 #define CONFIG_USB_CORE_IP_293A
345 #define CONFIG_USB_GADGET_SC8800G
346 #define CONFIG_USB_DWC
347 #define CONFIG_USB_GADGET_DUALSPEED
348 //#define CONFIG_USB_ETHER
349 #define CONFIG_CMD_FASTBOOT
350 #define SCRATCH_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
351 #define FB_DOWNLOAD_BUF_SIZE (CONFIG_SYS_NAND_U_BOOT_DST - SCRATCH_ADDR-0x800000)
352 #define SCRATCH_ADDR_EXT1 (CONFIG_SYS_NAND_U_BOOT_DST + 32*1024*1024)
353 #define FB_DOWNLOAD_BUF_EXT1_SIZE (224*1024*1024)
355 #define CONFIG_MODEM_CALIBERATE
359 #define CONFIG_SPLASH_SCREEN
360 #define LCD_BPP LCD_COLOR16
361 //#define CONFIG_LCD_HVGA 1
362 //#define CONFIG_LCD_QVGA 1
363 //#define CONFIG_LCD_QHD 1
364 //#define CONFIG_LCD_720P 1
365 #define CONFIG_LCD_FWVGA 1
367 //#define CONFIG_LCD_INFO
368 //#define LCD_TEST_PATTERN
369 //#define CONFIG_LCD_LOGO
370 //#define CONFIG_FB_LCD_S6D0139
371 //#define CONFIG_FB_LCD_SSD2075_MIPI
372 //#define CONFIG_FB_LCD_NT35516_MIPI
373 #define CONFIG_FB_LCD_HX8363_RGB_SPI
374 //#define CONFIG_FB_LCD_HX8363_MCU
376 #define CONFIG_SYS_WHITE_ON_BLACK
377 #ifdef LCD_TEST_PATTERN
378 #define CONSOLE_COLOR_RED 0xf800
379 #define CONSOLE_COLOR_GREEN 0x07e0
380 #define CONSOLE_COLOR_YELLOW 0x07e0
381 #define CONSOLE_COLOR_BLUE 0x001f
382 #define CONSOLE_COLOR_MAGENTA 0x001f
383 #define CONSOLE_COLOR_CYAN 0x001f
387 #define CONFIG_SPRD_SYSDUMP
388 #include <asm/sizes.h>
389 #define SPRD_SYSDUMP_MAGIC ((PHYS_OFFSET_ADDR & (~(SZ_512M - 1))) + SZ_512M - SZ_1M)
390 #define CALIBRATE_ENUM_MS 3000
391 #define CALIBRATE_IO_MS 2000
393 //#define LOW_BAT_ADC_LEVEL 782 /*phone battery adc value low than this value will not boot up*/
394 #define LOW_BAT_VOL 3500 /*phone battery voltage low than this value will not boot up*/
395 #define LOW_BAT_VOL_CHG 3200 //3.3V charger connect
397 #define PWR_KEY_DETECT_CNT 12 /*this should match the count of boot_pwr_check() function */
398 #define ALARM_LEAD_SET_MS 0 /* time set for alarm boot in advancd */
400 #define PHYS_OFFSET_ADDR 0x80000000
401 #define TD_CP_OFFSET_ADDR 0x8000000 /*128*/
402 #define TD_CP_SDRAM_SIZE 0x1800000 /*24M*/
403 #define WCDMA_CP_OFFSET_ADDR 0x8000000 /*128M*/
404 #define WCDMA_CP_SDRAM_SIZE 0x2000000 /*32M*/
406 #define WCN_CP_OFFSET_ADDR 0xa800000 /*168M*/
407 #define WCN_CP_SDRAM_SIZE 0x500000 /*5M*/
409 #define SIPC_APCP_RESET_ADDR_SIZE 0xC00 /*3K*/
410 #define SIPC_APCP_RESET_SIZE 0x1000 /*4K*/
411 #define SIPC_WCDMA_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCDMA_CP_OFFSET_ADDR + WCDMA_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
412 #define SIPC_WCN_APCP_START_ADDR (PHYS_OFFSET_ADDR + WCN_CP_OFFSET_ADDR + WCN_CP_SDRAM_SIZE - SIPC_APCP_RESET_SIZE)
414 //#define CALIBRATION_FLAG 0x89700000
416 #define CONFIG_CMD_SOUND 1
417 #define CONFIG_CMD_FOR_HTC 1
418 #define CONFIG_SOUND_CODEC_SPRD_V3 1
419 #define CONFIG_SOUND_DAI_VBC_R2P0 1
420 /* #define CONFIG_SPRD_AUDIO_DEBUG */
422 #define CONFIG_RAMDUMP_NO_SPLIT 1 /* Don't split sysdump file */
424 #define CONFIG_PBINT_7S_RESET_V1
425 /* short reset when power key reset trigged */
426 #define CONFIG_PBINT_7S_RST_SW_SHORT 1
427 /* reset then release the power key when reset trigged */
428 /* #define CONFIG_PBINT_7S_RST_SW_LONG 1 */
429 /* reset then release the power key when reset trigged */
430 /* #define CONFIG_PBINT_7S_RST_HW_LONG 1 */
431 /* rang:2-16 unit: s */
432 /* #define CONFIG_PBINT_7S_RST_THRESHOLD 7 */
434 /* #define CONFIG_SMPL_MODE */
435 /* rang:0(0.5s) - 7(4s) unit: s step: 0.5s */
436 /* #define CONFIG_SMPL_THRESHOLD 0 */
438 #endif /* __CONFIG_H */