drivers/yp_mmc/sdio_reg.h

   1 /*********************************************************************\r
   2  ** File Name:          sdio_reg.h\r
   3  ** Author:                     yanping.xie\r
   4  ** DATE:                       09/05/2013\r
   5  ** Copyright:                  2004 Spreadtrum, Incoporated. All Rights Reserved.\r
   6  ** Description:                This file describe operation of sdio host.\r
   7  *********************************************************************\r
   8
   9  *********************************************************************\r
  10  **                               Edit History                                                                                   **\r
  11  ** ------------------------------------------------------------------------- **\r
  12  ** DATE                                NAME                            DESCRIPTION\r
  13  ** 09/05/2013          ypxie                           Create.\r
  14  ********************************************************************/\r
  15 #ifndef __SDIO_REG_H_\r
  16 #define __SDIO_REG_H_\r
  17 \r
  18 /* REG[0x0040], REG[0x0044], REG[0x0048] : capability */\r
  19 typedef struct sdhost_cap_v20_t_tag\r
  20 {\r
  21         /* CAP[0x0040] */\r
  22         uint32 timeout_clk_freq         : 6;                                                            ///< [5:0]\r
  23         uint32 rsrvd0                           : 1;                                                            ///< [6]\r
  24         uint32 timeout_lk_uint          : 1;                                                            ///< [7]\r
  25         uint32 base_clk_freq            : 6;                                                            ///< [13:8]\r
  26         uint32 rsrvd1                           : 2;                                                            ///< [15:14]\r
  27         uint32 max_blk_size             : 2;                                                            ///< [17:16]\r
  28         uint32 rsrvd2                           : 3;                                                            ///< [20:18]\r
  29         uint32 spprt_high_speed : 1;                                                            ///< [21]\r
  30         uint32 spprt_dma                        : 1;                                                            ///< [22]\r
  31         uint32 spprt_susp_res           : 1;                                                            ///< [23]\r
  32         uint32 spprt_volt_33            : 1;                                                            ///< [24]\r
  33         uint32 spprt_volt_30            : 1;                                                            ///< [25]\r
  34         uint32 spprt_volt_18            : 1;                                                            ///< [26]\r
  35         uint32 rsrvd3                           : 5;                                                            ///< [31:27]\r
  36 \r
  37         /* CAP2[0x0044] */\r
  38         uint32 cap2;                                                                                            ///< reserved\r
  39 \r
  40         /* MAX_CUR_CAP[0x0048] */\r
  41         uint32 max_cur_volt_33          : 8;                                                            ///< [7:0]\r
  42         uint32 max_cur_volt_30          : 8;                                                            ///< [15:8]\r
  43         uint32 max_cur_volt_18          : 8;                                                            ///< [23:16]\r
  44         uint32 rsrvd4                           : 8;\r
  45 } sdhost_cap_v20_t;\r
  46 \r
  47 typedef struct sdhost_cap_v30_t_tag\r
  48 {
  49         /* CAP[0x0040] */\r
  50         uint32 timeout_clk_freq         : 6;                                                            ///< [5:0]\r
  51         uint32 rsrvd0                           : 1;                                                            ///< [6]\r
  52         uint32 timeout_lk_uint          : 1;                                                            ///< [7]\r
  53         uint32 base_clk_freq            : 8;                                                            ///< [15:8]\r
  54         uint32 max_blk_size             : 2;                                                            ///< [17:16]\r
  55         uint32 spprt_8bit                       : 1;                                                            ///< [18]\r
  56         uint32 spprt_adma2              : 1;                                                            ///< [19]\r
  57         uint32 rsrvd1                           : 1;                                                            ///< [20]\r
  58         uint32 spprt_high_speed : 1;                                                            ///< [21]\r
  59         uint32 spprt_dma                        : 1;                                                            ///< [22]\r
  60         uint32 spprt_susp_res           : 1;                                                            ///< [23]\r
  61         uint32 spprt_volt_33            : 1;                                                            ///< [24]\r
  62         uint32 spprt_volt_30            : 1;                                                            ///< [25]\r
  63         uint32 spprt_volt_18            : 1;                                                            ///< [26]\r
  64         uint32 rsrvd2                           : 1;                                                            ///< [27]\r
  65         uint32 spprt_64bit_sys          : 1;                                                            ///< [28]\r
  66         uint32 spprt_async_int          : 1;                                                            ///< [29]\r
  67         uint32 rsrvd3                           : 2;                                                            ///< [31:30]\r
  68 \r
  69         /* CAP2[0x0044] */\r
  70         uint32 spprt_sdr52                      : 1;                                                            ///< [0]\r
  71         uint32 spprt_sdr104             : 1;                                                            ///< [1]\r
  72         uint32 spprt_ddr52                      : 1;                                                            ///< [2]\r
  73         uint32 rsrvd4                           : 29;                                                   ///< [31:3]\r
  74 \r
  75         /* MAX_CUR_CAP[0x0048] */\r
  76         uint32 max_cur_volt_33          : 8;                                                            ///< [7:0]\r
  77         uint32 max_cur_volt_30          : 8;                                                            ///< [15:8]\r
  78         uint32 max_cur_volt_18          : 8;                                                            ///< [23:16]\r
  79 } sdhost_cap_v30_t;\r
  80 \r
  81 /* REG[0x000C] : cmd trans mode */\r
  82 /* [cmd_index] bit[29:24] */\r
  83 /* [cmd_type] bit[23:22] */\r
  84 #define SDIO_CMD_TYPE_ABORT                             ( 3 << 22 )\r
  85 #define SDIO_CMD_TYPE_RESUME                    ( 2 << 22 )\r
  86 #define SDIO_CMD_TYPE_SUSPEND                   ( 1 << 22 )\r
  87 #define SDIO_CMD_TYPE_NML                               ( 0 << 22 )\r
  88 \r
  89 /* [transmode] bit[6:0], bit[21], bit[31], bit[30] */\r
  90 #define SDIO_BOOT_ACK                                   BIT_31                          ///< v3.0\r
  91 #define SDIO_CMD_LINE_BOOT                              BIT_30                          ///< v3.0\r
  92 #define SDIO_DATA_PRE                                   BIT_21\r
  93 \r
  94 /* v3.0 auto cmd12 is bit[3:2] , v2.0 auto cmd12 is bit[2] */\r
  95 #define SDIO_TRANS_DIS_AUTO                             ( 0x00 << 2 )                   ///< v3.0\r
  96 #define SDIO_TRANS_AUTO_CMD12_EN                BIT_2                           ///< v2.0\r
  97 #define SDIO_TRANS_AUTO_CMD23_EN                ( 0x02 << 2 )                   ///< v3.0\r
  98 \r
  99 #define SDIO_TRANS_COMP_ATA                     BIT_6\r
 100 #define SDIO_TRANS_MULTIBLK                             BIT_5\r
 101 #define SDIO_TRANS_DIR_READ                             BIT_4\r
 102 #define SDIO_TRANS_BLK_CNT_EN                   BIT_1\r
 103 #define SDIO_TRANS_DMA_EN                               BIT_0\r
 104 \r
 105 /* [response] bit[17:16], bit[20], bit[19]*/\r
 106 #define SDIO_CMD_INDEX_CHK                              BIT_20\r
 107 #define SDIO_CMD_CRC_CHK                                BIT_19\r
 108 \r
 109 #define SDIO_CMD_NO_RSP                                 ( 0x00 << 16 )\r
 110 #define SDIO_CMD_RSP_136                                ( 0x01 << 16 )\r
 111 #define SDIO_CMD_RSP_48                                 ( 0x02 << 16 )\r
 112 #define SDIO_CMD_RSP_48_BUSY                    ( 0x03 << 16 )\r
 113 \r
 114 #define SDIO_NO_RSP     0x00\r
 115 #define SDIO_R1         ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 116 #define SDIO_R2         ( SDIO_CMD_RSP_136 | SDIO_CMD_CRC_CHK )\r
 117 #define SDIO_R3         SDIO_CMD_RSP_48\r
 118 #define SDIO_R4         SDIO_CMD_RSP_48\r
 119 #define SDIO_R5         ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 120 #define SDIO_R6         ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 121 #define SDIO_R7         ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 122 #define SDIO_R1B                ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 123 #define SDIO_R5B                ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )\r
 124 \r
 125 /* REG[0x0030], REG[0x0034], REG[0x0038] : interrupt */\r
 126 #define INT_CMD_CMPLT                                   BIT_0\r
 127 #define INT_TR_CMPLT                                            BIT_1\r
 128 #define INT_CAP_EVENT                                   BIT_2\r
 129 #define INT_DMA_INT                                             BIT_3\r
 130 #define INT_BUF_WR_RDY                                  BIT_4\r
 131 #define INT_BUF_RD_RDY                                  BIT_5\r
 132 #define INT_CARD_INT                                            BIT_8\r
 133 \r
 134 #define INT_ERR_INT                                             BIT_15\r
 135 \r
 136 #define INT_CMD_TIMEOUT                                 BIT_16\r
 137 #define INT_CMD_CRC                                             BIT_17\r
 138 #define INT_CMD_END_BIT                                 BIT_18\r
 139 #define INT_CMD_IND                                             BIT_19\r
 140 #define INT_DATA_TIMEOUT                                BIT_20\r
 141 #define INT_DATA_CRC                                            BIT_21\r
 142 #define INT_DATA_END_BIT                                        BIT_22\r
 143 #define INT_CUR_LMT                                             BIT_23\r
 144 #define INT_AUTO_CMD12                                  BIT_24\r
 145 #define INT_TRGT_RESP                                   BIT_28\r
 146 #define INT_VNDR_ERR_ST                                 (BIT_29 | BIT_30 | BIT_31)\r
 147 \r
 148 #define INT_ALL                                                 (BIT_15 | BIT_8 | 0xFF)\r
 149 \r
 150 typedef struct sdio_reg_v20_t_tag\r
 151 {\r
 152         volatile uint32                                 dma_addr;                                       ///< 0x0000\r
 153         volatile uint32                                 blk_size_cnt;                                   ///< 0x0004\r
 154         volatile uint32                                 cmd_argu;                                       ///< 0x0008\r
 155         volatile uint32                                 tr_mode;                                                ///< 0x000C\r
 156         volatile uint32                                 resp0;                                          ///< 0x0010\r
 157         volatile uint32                                 resp1;                                          ///< 0x0014\r
 158         volatile uint32                                 resp2;                                          ///< 0x0018\r
 159         volatile uint32                                 resp3;                                          ///< 0x001C\r
 160         volatile uint32                                 buf_port;                                               ///< 0x0020\r
 161         volatile uint32                                 pres_state;                                     ///< 0x0024\r
 162         volatile uint32                                 sd_ctrl1;                                               ///< 0x0028\r
 163         volatile uint32                                 sd_ctrl2;                                               ///< 0x002C\r
 164         volatile uint32                                 int_st;                                         ///< 0x0030\r
 165         volatile uint32                                 int_st_en;                                      ///< 0x0034\r
 166         volatile uint32                                 int_sig_en;                                     ///< 0x0038\r
 167         volatile uint32                                 cmd12_st;                                       ///< 0x003C\r
 168         volatile uint32                                 cap1;                                           ///< 0x0040\r
 169         volatile uint32                                 cap2;                                           ///< 0x0044\r
 170         volatile uint32                                 cur_cap1;                                       ///< 0x0048\r
 171         volatile uint32                                 cur_cap2;                                       ///< 0x004C\r
 172 } sdio_reg_v20_t, *sdio_reg_ptr;\r
 173 \r
 174 typedef struct sdio_reg_v30_t_tag\r
 175 {\r
 176         volatile uint32                                 dma_addr;                                       ///< 0x0000\r
 177         volatile uint32                                 blk_size_cnt;                                   ///< 0x0004\r
 178         volatile uint32                                 cmd_argu;                                       ///< 0x0008\r
 179         volatile uint32                                 tr_mode;                                                ///< 0x000C\r
 180         volatile uint32                                 resp0;                                          ///< 0x0010\r
 181         volatile uint32                                 resp1;                                          ///< 0x0014\r
 182         volatile uint32                                 resp2;                                          ///< 0x0018\r
 183         volatile uint32                                 resp3;                                          ///< 0x001C\r
 184         volatile uint32                                 buf_port;                                               ///< 0x0020\r
 185         volatile uint32                                 pres_state;                                     ///< 0x0024\r
 186         volatile uint32                                 sd_ctrl1;                                               ///< 0x0028\r
 187         volatile uint32                                 sd_ctrl2;                                               ///< 0x002C\r
 188         volatile uint32                                 int_st;                                         ///< 0x0030\r
 189         volatile uint32                                 int_st_en;                                      ///< 0x0034\r
 190         volatile uint32                                 int_sig_en;                                     ///< 0x0038\r
 191         volatile uint32                                 sd_ctrl3;                                               ///< 0x003C\r
 192         volatile uint32                                 cap1;                                           ///< 0x0040\r
 193         volatile uint32                                 cap2;                                           ///< 0x0044\r
 194         volatile uint32                                 cur_cap1;                                       ///< 0x0048\r
 195         volatile uint32                                 cur_cap2;                                       ///< 0x004C\r
 196         volatile uint32                                 force_evt;                                      ///< 0x0050\r
 197         volatile uint32                                 reserved0;                                      ///< 0x0054\r
 198         volatile uint32                                 reserved1;                                      ///< 0x0058\r
 199         volatile uint32                                 reserved2;                                      ///< 0x005C\r
 200         volatile uint32                                 pre_val_def;                                    ///< 0x0060\r
 201         volatile uint32                                 pre_val_high;                                   ///< 0x0064\r
 202         volatile uint32                                 pre_val_sdr52;                          ///< 0x0068\r
 203         volatile uint32                                 pre_val_ddr52;                          ///< 0x006C\r
 204         volatile uint32                                 reserved3;                                      ///< 0x0070\r
 205         volatile uint32                                 reserved4;                                      ///< 0x0074\r
 206         volatile uint32                                 reserved5;                                      ///< 0x0078\r
 207         volatile uint32                                 reserved6;                                      ///< 0x007C\r
 208         volatile uint32                                 wr_dly;                                         ///< 0x0080\r
 209         volatile uint32                                 rd_pos_dly;                                     ///< 0x0080\r
 210         volatile uint32                                 rd_neg_dly;                                     ///< 0x0088\r
 211         /* slt_int_st   ...   0x00FC is slot interrupt status */\r
 212 } sdio_reg_v30_t, *sdio_reg_v30_ptr;\r
 213 \r
 214 typedef struct sdio_reg_slave_t_tag\r
 215 {\r
 216         volatile uint32                                 dma_addr;                                       ///< 0x0000\r
 217         volatile uint32                                 rst_dma_set;                                    ///< 0x0004\r
 218         volatile uint32                                 reserved0;                                      ///< 0x0008\r
 219         volatile uint32                                 blk_size_cnt;                                   ///< 0x000C\r
 220         volatile uint32                                 tr_mode;                                                ///< 0x0010\r
 221         volatile uint32                                 cur_st;                                         ///< 0x0014\r
 222         volatile uint32                                 cmd_argu;                                       ///< 0x0018\r
 223         volatile uint32                                 rsp_argu;                                       ///< 0x001C\r
 224         volatile uint32                                 buf_port;                                               ///< 0x0020\r
 225         volatile uint32                                 reserved1;                                      ///< 0x0024\r
 226         volatile uint32                                 reserved2;                                      ///< 0x0028\r
 227         volatile uint32                                 reserved3;                                      ///< 0x002C\r
 228         volatile uint32                                 int_en;                                         ///< 0x0030\r
 229         volatile uint32                                 int_clr;                                                ///< 0x0034\r
 230         volatile uint32                                 int_raw_st;                                     ///< 0x0038\r
 231         volatile uint32                                 int_mask;                                       ///< 0x003C\r
 232         volatile uint32                                 supt_ocr;                                               ///< 0x0040\r
 233         volatile uint32                                 cur_ocr;                                                ///< 0x0044\r
 234 } sdio_reg_slave_t, *sdio_reg_slave_ptr;\r
 235 \r
 236 #endif /* __SDIO_REG_H_ */