drivers/video/sprdfb/sprdfb_chip_9630.h

   1 /******************************************************************************
   2  ** File Name:    sprdfb_chip_9630.h                                     *
   3  ** Author:       congfu.zhao                                           *
   4  ** DATE:         30/04/2013                                        *
   5  ** Copyright:    2013 Spreatrum, Incoporated. All Rights Reserved. *
   6  ** Description:                                                    *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                               *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                       *
  12
  13  ******************************************************************************/
  14 #ifndef _SC9630_DISPC_GLB_REG_U_H_
  15 #define _SC9630_DISPC_GLB_REG_U_H_
  16
  17
  18 #include <asm/arch/sprd_reg.h>
  19 #include <asm/arch/sprd_reg_base.h>
  20 #include <asm/arch/sprd_reg_global.h>
  21 #include <asm/arch/adi_hal_internal.h>
  22
  23
  24 #define BIT(x) (1<<x)
  25
  26 #define SPRD_MIPI_DPHY_GEN2
  27
  28 #define DSI_CTL_BEGIN                           CTL_BASE_DSI
  29
  30 #define DSI_AHB_SOFT_RST                        REG_AP_AHB_AHB_RST
  31 #define BIT_DSI_SOFT_RST                        ( BIT(0) )
  32
  33 #define DSI_REG_EB                              REG_AP_AHB_AHB_EB
  34 #define DSI_BIT_EB                                      BIT_DSI_EB
  35
  36 #define DISPC_AHB_SOFT_RST              REG_AP_AHB_AHB_RST
  37 //#define BIT_DISPC_SOFT_RST                    BIT_DISPC_SOFT_RST
  38
  39 #define DISPC_AHB_EN                            (REG_AP_AHB_AHB_EB)
  40 #define BIT_DISPC_AHB_EN                        (BIT_DISPC_EB)
  41
  42 #define DISPC_CORE_EN                   (REG_AP_APB_APB_EB)
  43 #define BIT_DISPC_CORE_EN                       (BIT_AP_CKG_EB)
  44
  45 #define DISPC_EMC_EN                            (REG_AON_APB_APB_EB1)
  46 #define BIT_DISPC_EMC_EN                        (BIT_DISP_EMC_EB)
  47
  48 #define DISPC_PLL_SEL_CFG                       REG_AP_CLK_DISPC0_CFG
  49 #define BITS_DISPC_PLL_SEL_CFG          0
  50 #define BIT0_DISPC_PLL_SEL_CFG          BIT(0)
  51 #define BIT1_DISPC_PLL_SEL_CFG          BIT(1)
  52 #define BIT_DISPC_PLL_SEL_MSK           BIT1_DISPC_PLL_SEL_CFG | BIT0_DISPC_PLL_SEL_CFG
  53
  54 #define DISPC_PLL_DIV_CFG                       REG_AP_CLK_DISPC0_CFG
  55 #define BITS_DISPC_PLL_DIV_CFG          8
  56 #define BIT0_DISPC_PLL_DIV_CFG          BIT(8)
  57 #define BIT1_DISPC_PLL_DIV_CFG          BIT(9)
  58 #define BIT2_DISPC_PLL_DIV_CFG          BIT(10)
  59 #define BIT_DISPC_PLL_DIV_MSK           BIT0_DISPC_PLL_DIV_CFG | BIT1_DISPC_PLL_DIV_CFG | BIT2_DISPC_PLL_DIV_CFG
  60
  61 #define DISPC_DBI_SEL_CFG                       REG_AP_CLK_DISPC0_DBI_CFG
  62 #define BITS_DISPC_DBI_SEL_CFG          0
  63 #define BIT0_DISPC_DBI_SEL_CFG          BIT(0)
  64 #define BIT1_DISPC_DBI_SEL_CFG          BIT(1)
  65 #define BIT_DISPC_DBI_SEL_MSK           BIT0_DISPC_DBI_SEL_CFG | BIT1_DISPC_DBI_SEL_CFG
  66
  67 #define DISPC_DBI_DIV_CFG                       REG_AP_CLK_DISPC0_DBI_CFG
  68 #define BITS_DISPC_DBI_DIV_CFG          8
  69 #define BIT0_DISPC_DBI_DIV_CFG          BIT(8)
  70 #define BIT1_DISPC_DBI_DIV_CFG          BIT(9)
  71 #define BIT2_DISPC_DBI_DIV_CFG          BIT(10)
  72 #define BIT_DISPC_DBI_DIV_MSK           BIT0_DISPC_DBI_DIV_CFG | BIT1_DISPC_DBI_DIV_CFG | BIT2_DISPC_DBI_DIV_CFG
  73
  74 #define DISPC_DPI_SEL_CFG                       REG_AP_CLK_DISPC0_DPI_CFG
  75 #define BITS_DISPC_DPI_SEL_CFG          0
  76 #define BIT0_DISPC_DPI_SEL_CFG          BIT(0)
  77 #define BIT1_DISPC_DPI_SEL_CFG          BIT(1)
  78 #define BIT_DISPC_DPI_SEL_MSK           BIT0_DISPC_DPI_SEL_CFG | BIT1_DISPC_DPI_SEL_CFG
  79
  80 #define DISPC_DPI_DIV_CFG                       REG_AP_CLK_DISPC0_DPI_CFG
  81 #define BITS_DISPC_DPI_DIV_CFG          8
  82 #define BIT0_DISPC_DPI_DIV_CFG          BIT(8)
  83 #define BIT1_DISPC_DPI_DIV_CFG          BIT(9)
  84 #define BIT2_DISPC_DPI_DIV_CFG          BIT(10)
  85 #define BIT3_DISPC_DPI_DIV_CFG          BIT(11)
  86 #define BIT4_DISPC_DPI_DIV_CFG          BIT(12)
  87 #define BIT5_DISPC_DPI_DIV_CFG          BIT(13)
  88 #define BIT6_DISPC_DPI_DIV_CFG          BIT(14)
  89 #define BIT7_DISPC_DPI_DIV_CFG          BIT(15)
  90 #define BIT_DISPC_DPI_DIV_MSK           BIT0_DISPC_DPI_DIV_CFG | BIT1_DISPC_DPI_DIV_CFG | BIT2_DISPC_DPI_DIV_CFG | BIT3_DISPC_DPI_DIV_CFG \
  91                                         | BIT4_DISPC_DPI_DIV_CFG | BIT5_DISPC_DPI_DIV_CFG | BIT6_DISPC_DPI_DIV_CFG | BIT7_DISPC_DPI_DIV_CFG
  92
  93
  94 enum{
  95         DISPC_PLL_SEL_96M = 0,
  96         DISPC_PLL_SEL_192M,
  97         DISPC_PLL_SEL_256M,
  98         DISPC_PLL_SEL_312M
  99 };
 100
 101 enum{
 102         DISPC_DBI_SEL_128M = 0,
 103         DISPC_DBI_SEL_153_6M,
 104         DISPC_DBI_SEL_192M,
 105         DISPC_DBI_SEL_256M
 106 };
 107
 108 enum{
 109         DISPC_DPI_SEL_128M = 0,
 110         DISPC_DPI_SEL_153_6M,
 111         DISPC_DPI_SEL_192M,
 112         DISPC_DPI_SEL_384M
 113 };
 114
 115 #define DISPC_PLL_SEL_DEFAULT   DISPC_PLL_SEL_256M
 116 #define DISPC_DBI_SEL_DEFAULT   DISPC_DBI_SEL_256M
 117 #define DISPC_DPI_SEL_DEFAULT   DISPC_DPI_SEL_384M
 118
 119 #define DISPC_PLL_DIV_DEFAULT   0
 120 #define DISPC_DBI_DIV_DEFAULT   0
 121 #define DISPC_DPI_DIV_DEFAULT   6
 122
 123
 124
 125 void dsi_enable(void);
 126 void dsi_disable(void);
 127
 128 void dispc_print_clk(void);
 129
 130
 131
 132 #endif