drivers/video/sprdfb/sprdfb_chip_7715.h

   1 /******************************************************************************
   2  ** File Name:    sprdfb_chip_7715.h                                     *
   3  ** Author:       congfu.zhao                                           *
   4  ** DATE:         30/04/2013                                        *
   5  ** Copyright:    2013 Spreatrum, Incoporated. All Rights Reserved. *
   6  ** Description:                                                    *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                               *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                       *
  12
  13  ******************************************************************************/
  14 #ifndef _SC7715_DISPC_GLB_REG_U_H_
  15 #define _SC7715_DISPC_GLB_REG_U_H_
  16
  17
  18 #include <asm/arch/sprd_reg.h>
  19 #include <asm/arch/sprd_reg_base.h>
  20 #include <asm/arch/sprd_reg_global.h>
  21 #include <asm/arch/adi_hal_internal.h>
  22
  23
  24 #define BIT(x) (1<<x)
  25
  26 //no mipi
  27
  28 #define DISPC_AHB_SOFT_RST              REG_AP_AHB_AHB_RST
  29 #define BIT_DISPC_SOFT_RST                      BIT_DISPC0_SOFT_RST
  30
  31 #define DISPC_AHB_EN                            (REG_AP_AHB_AHB_EB)
  32 #define BIT_DISPC_AHB_EN                        (BIT_DISPC0_EB)
  33
  34 #define DISPC_CORE_EN                   (REG_AP_APB_APB_EB)
  35 #define BIT_DISPC_CORE_EN                       (BIT_AP_CKG_EB)
  36
  37 #define DISPC_EMC_EN                            (REG_AON_APB_APB_EB1)
  38 #define BIT_DISPC_EMC_EN                        (BIT_DISP_EMC_EB)
  39
  40 #define DISPC_PLL_SEL_CFG                       REG_AP_CLK_DISPC0_CFG
  41 #define BITS_DISPC_PLL_SEL_CFG          0
  42 #define BIT0_DISPC_PLL_SEL_CFG          BIT(0)
  43 #define BIT1_DISPC_PLL_SEL_CFG          BIT(1)
  44 #define BIT_DISPC_PLL_SEL_MSK           BIT1_DISPC_PLL_SEL_CFG | BIT0_DISPC_PLL_SEL_CFG
  45
  46 #define DISPC_PLL_DIV_CFG                       REG_AP_CLK_DISPC0_CFG
  47 #define BITS_DISPC_PLL_DIV_CFG          8
  48 #define BIT0_DISPC_PLL_DIV_CFG          BIT(8)
  49 #define BIT1_DISPC_PLL_DIV_CFG          BIT(9)
  50 #define BIT2_DISPC_PLL_DIV_CFG          BIT(10)
  51 #define BIT_DISPC_PLL_DIV_MSK           BIT0_DISPC_PLL_DIV_CFG | BIT1_DISPC_PLL_DIV_CFG | BIT2_DISPC_PLL_DIV_CFG
  52
  53 #define DISPC_DBI_SEL_CFG                       REG_AP_CLK_DISPC0_DBI_CFG
  54 #define BITS_DISPC_DBI_SEL_CFG          0
  55 #define BIT0_DISPC_DBI_SEL_CFG          BIT(0)
  56 #define BIT1_DISPC_DBI_SEL_CFG          BIT(1)
  57 #define BIT_DISPC_DBI_SEL_MSK           BIT0_DISPC_DBI_SEL_CFG | BIT1_DISPC_DBI_SEL_CFG
  58
  59 #define DISPC_DBI_DIV_CFG                       REG_AP_CLK_DISPC0_DBI_CFG
  60 #define BITS_DISPC_DBI_DIV_CFG          8
  61 #define BIT0_DISPC_DBI_DIV_CFG          BIT(8)
  62 #define BIT1_DISPC_DBI_DIV_CFG          BIT(9)
  63 #define BIT2_DISPC_DBI_DIV_CFG          BIT(10)
  64 #define BIT_DISPC_DBI_DIV_MSK           BIT0_DISPC_DBI_DIV_CFG | BIT1_DISPC_DBI_DIV_CFG | BIT2_DISPC_DBI_DIV_CFG
  65
  66 #define DISPC_DPI_SEL_CFG                       REG_AP_CLK_DISPC0_DPI_CFG
  67 #define BITS_DISPC_DPI_SEL_CFG          0
  68 #define BIT0_DISPC_DPI_SEL_CFG          BIT(0)
  69 #define BIT1_DISPC_DPI_SEL_CFG          BIT(1)
  70 #define BIT_DISPC_DPI_SEL_MSK           BIT0_DISPC_DPI_SEL_CFG | BIT1_DISPC_DPI_SEL_CFG
  71
  72 #define DISPC_DPI_DIV_CFG                       REG_AP_CLK_DISPC0_DPI_CFG
  73 #define BITS_DISPC_DPI_DIV_CFG          8
  74 #define BIT0_DISPC_DPI_DIV_CFG          BIT(8)
  75 #define BIT1_DISPC_DPI_DIV_CFG          BIT(9)
  76 #define BIT2_DISPC_DPI_DIV_CFG          BIT(10)
  77 #define BIT3_DISPC_DPI_DIV_CFG          BIT(11)
  78 #define BIT4_DISPC_DPI_DIV_CFG          BIT(12)
  79 #define BIT5_DISPC_DPI_DIV_CFG          BIT(13)
  80 #define BIT6_DISPC_DPI_DIV_CFG          BIT(14)
  81 #define BIT7_DISPC_DPI_DIV_CFG          BIT(15)
  82 #define BIT_DISPC_DPI_DIV_MSK           BIT0_DISPC_DPI_DIV_CFG | BIT1_DISPC_DPI_DIV_CFG | BIT2_DISPC_DPI_DIV_CFG | BIT3_DISPC_DPI_DIV_CFG \
  83                                         | BIT4_DISPC_DPI_DIV_CFG | BIT5_DISPC_DPI_DIV_CFG | BIT6_DISPC_DPI_DIV_CFG | BIT7_DISPC_DPI_DIV_CFG
  84
  85
  86 enum{
  87         DISPC_PLL_SEL_153_6M = 0,
  88         DISPC_PLL_SEL_192M,
  89 };
  90
  91 enum{
  92         DISPC_DBI_SEL_128M = 0,
  93         DISPC_DBI_SEL_153_6M,
  94         DISPC_DBI_SEL_192M,
  95         DISPC_DBI_SEL_256M
  96 };
  97
  98 enum{
  99         DISPC_DPI_SEL_128M = 0,
 100         DISPC_DPI_SEL_153_6M,
 101         DISPC_DPI_SEL_192M,
 102         DISPC_DPI_SEL_384M,
 103 };
 104
 105 #define DISPC_PLL_SEL_DEFAULT   DISPC_PLL_SEL_192M
 106 #define DISPC_DBI_SEL_DEFAULT   DISPC_DBI_SEL_256M
 107 #define DISPC_DPI_SEL_DEFAULT   DISPC_DPI_SEL_384M
 108
 109 #define DISPC_PLL_DIV_DEFAULT   0
 110 #define DISPC_DBI_DIV_DEFAULT   0
 111 #define DISPC_DPI_DIV_DEFAULT   14
 112
 113 void dsi_enable(void);
 114
 115 void dispc_print_clk(void);
 116
 117
 118
 119 #endif