drivers/video/sprdfb/sprdfb_chip_7710.h

   1 /******************************************************************************
   2  ** File Name:    sprdfb_chip_7710.h                                     *
   3  ** Author:       congfu.zhao                                           *
   4  ** DATE:         30/04/2013                                        *
   5  ** Copyright:    2013 Spreatrum, Incoporated. All Rights Reserved. *
   6  ** Description:                                                    *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                               *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                       *
  12
  13  ******************************************************************************/
  14 #ifndef _SC7710_DISPC_GLB_REG_U_H_
  15 #define _SC7710_DISPC_GLB_REG_U_H_
  16
  17
  18 #include <asm/arch/sc8810_reg_ahb.h>
  19 #include <asm/arch/sc8810_reg_global.h>
  20
  21
  22 #define BIT(x) (1<<x)
  23
  24
  25 #define DISPC_AHB_SOFT_RST              AHB_SOFT2_RST
  26 #define BIT_DISPC_SOFT_RST                      BIT(2)
  27
  28 #define DISPC_AHB_EN                            (AHB_CTL6)
  29 #define BIT_DISPC_AHB_EN                        (BIT(0))
  30
  31 #define DISPC_CORE_EN                   (AHB_CTL6)
  32 #define BIT_DISPC_CORE_EN                       (BIT(0))
  33
  34 #define DISPC_EMC_EN                            (AHB_CTL6)
  35 #define BIT_DISPC_EMC_EN                        (BIT(0))
  36
  37 #define DISPC_PLL_SEL_CFG                       AHB_CTL6
  38 #define BITS_DISPC_PLL_SEL_CFG          30
  39 #define BIT0_DISPC_PLL_SEL_CFG          BIT(30)
  40 #define BIT1_DISPC_PLL_SEL_CFG          BIT(31)
  41 #define BIT_DISPC_PLL_SEL_MSK           BIT1_DISPC_PLL_SEL_CFG | BIT0_DISPC_PLL_SEL_CFG
  42
  43 #define DISPC_PLL_DIV_CFG                       AHB_CTL6
  44 #define BITS_DISPC_PLL_DIV_CFG          27
  45 #define BIT0_DISPC_PLL_DIV_CFG          BIT(27)
  46 #define BIT1_DISPC_PLL_DIV_CFG          BIT(28)
  47 #define BIT2_DISPC_PLL_DIV_CFG          BIT(29)
  48 #define BIT_DISPC_PLL_DIV_MSK           BIT0_DISPC_PLL_DIV_CFG | BIT1_DISPC_PLL_DIV_CFG | BIT2_DISPC_PLL_DIV_CFG
  49
  50 #define DISPC_DBI_SEL_CFG                       AHB_CTL6
  51 #define BITS_DISPC_DBI_SEL_CFG          25
  52 #define BIT0_DISPC_DBI_SEL_CFG          BIT(25)
  53 #define BIT1_DISPC_DBI_SEL_CFG          BIT(26)
  54 #define BIT_DISPC_DBI_SEL_MSK           BIT0_DISPC_DBI_SEL_CFG | BIT1_DISPC_DBI_SEL_CFG
  55
  56 #define DISPC_DBI_DIV_CFG                       AHB_CTL6
  57 #define BITS_DISPC_DBI_DIV_CFG          22
  58 #define BIT0_DISPC_DBI_DIV_CFG          BIT(22)
  59 #define BIT1_DISPC_DBI_DIV_CFG          BIT(23)
  60 #define BIT2_DISPC_DBI_DIV_CFG          BIT(24)
  61 #define BIT_DISPC_DBI_DIV_MSK           BIT0_DISPC_DBI_DIV_CFG | BIT1_DISPC_DBI_DIV_CFG | BIT2_DISPC_DBI_DIV_CFG
  62
  63 #define DISPC_DPI_SEL_CFG                       AHB_CTL6
  64 #define BITS_DISPC_DPI_SEL_CFG          20
  65 #define BIT0_DISPC_DPI_SEL_CFG          BIT(20)
  66 #define BIT1_DISPC_DPI_SEL_CFG          BIT(21)
  67 #define BIT_DISPC_DPI_SEL_MSK           BIT0_DISPC_DPI_SEL_CFG | BIT1_DISPC_DPI_SEL_CFG
  68
  69 #define DISPC_DPI_DIV_CFG                       AHB_CTL6
  70 #define BITS_DISPC_DPI_DIV_CFG          12
  71 #define BIT0_DISPC_DPI_DIV_CFG          BIT(12)
  72 #define BIT1_DISPC_DPI_DIV_CFG          BIT(13)
  73 #define BIT2_DISPC_DPI_DIV_CFG          BIT(14)
  74 #define BIT3_DISPC_DPI_DIV_CFG          BIT(15)
  75 #define BIT4_DISPC_DPI_DIV_CFG          BIT(16)
  76 #define BIT5_DISPC_DPI_DIV_CFG          BIT(17)
  77 #define BIT6_DISPC_DPI_DIV_CFG          BIT(18)
  78 #define BIT7_DISPC_DPI_DIV_CFG          BIT(19)
  79 #define BIT_DISPC_DPI_DIV_MSK           BIT0_DISPC_DPI_DIV_CFG | BIT1_DISPC_DPI_DIV_CFG | BIT2_DISPC_DPI_DIV_CFG | BIT3_DISPC_DPI_DIV_CFG \
  80                                         | BIT4_DISPC_DPI_DIV_CFG | BIT5_DISPC_DPI_DIV_CFG | BIT6_DISPC_DPI_DIV_CFG | BIT7_DISPC_DPI_DIV_CFG
  81
  82
  83 enum{
  84         DISPC_PLL_SEL_256M = 0,
  85         DISPC_PLL_SEL_192M,
  86         DISPC_PLL_SEL_96M,
  87         DISPC_PLL_SEL_153_6M
  88 };
  89
  90 enum{
  91         DISPC_DBI_SEL_256M = 0,
  92         DISPC_DBI_SEL_128M,
  93         DISPC_DBI_SEL_192M,
  94         DISPC_DBI_SEL_153_6M
  95 };
  96
  97 enum{
  98         DISPC_DPI_SEL_384M = 0,
  99         DISPC_DPI_SEL_128M,
 100         DISPC_DPI_SEL_192M,
 101         DISPC_DPI_SEL_153_6M
 102 };
 103
 104 #define DISPC_PLL_SEL_DEFAULT   DISPC_PLL_SEL_256M
 105 #define DISPC_DBI_SEL_DEFAULT   DISPC_DBI_SEL_256M
 106 #define DISPC_DPI_SEL_DEFAULT   DISPC_DPI_SEL_384M
 107
 108 #define DISPC_PLL_DIV_DEFAULT   0
 109 #define DISPC_DBI_DIV_DEFAULT   0
 110 #define DISPC_DPI_DIV_DEFAULT   10
 111
 112
 113
 114 void dispc_print_clk(void);
 115
 116
 117
 118
 119
 120
 121 #endif