2 * @file mipi_dsih_hal.h
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8 The Synopsys Software Driver and documentation (hereinafter "Software")
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9 is an unsupported proprietary work of Synopsys, Inc. unless otherwise
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10 expressly agreed to in writing between Synopsys and you.
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12 The Software IS NOT an item of Licensed Software or Licensed Product under
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13 any End User Software License Agreement or Agreement for Licensed Product
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14 with Synopsys or any supplement thereto. Permission is hereby granted,
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15 free of charge, to any person obtaining a copy of this software annotated
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16 with this license and the Software, to deal in the Software without
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17 restriction, including without limitation the rights to use, copy, modify,
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18 merge, publish, distribute, sublicense, and/or sell copies of the Software,
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19 and to permit persons to whom the Software is furnished to do so, subject
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20 to the following conditions:
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22 The above copyright notice and this permission notice shall be included in
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23 all copies or substantial portions of the Software.
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25 THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
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26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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28 ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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30 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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31 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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33 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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34 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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38 #ifndef MIPI_DSIH_HAL_H_
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39 #define MIPI_DSIH_HAL_H_
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41 #include "mipi_dsih_local.h"
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44 #define R_DSI_HOST_VERSION (0x00)
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45 #define R_DSI_HOST_PWR_UP (0x04)
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46 #define R_DSI_HOST_CLK_MGR (0x08)
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47 #define R_DSI_HOST_DPI_VCID (0x0C)
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48 #define R_DSI_HOST_DPI_COLOR_CODE (0x10)
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49 #define R_DSI_HOST_DPI_CFG_POL (0x14)
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50 #define R_DSI_HOST_DPI_LP_CMD_TIM (0x18)
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51 #define R_DSI_HOST_DBI_VCID (0x1C)
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52 #define R_DSI_HOST_DBI_CFG (0x20)
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53 #define R_DSI_HOST_DBI_PARTITION_EN (0x24)
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54 #define R_DSI_HOST_DBI_CMDSIZE (0x28)
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55 #define R_DSI_HOST_PCKHDL_CFG (0x2C)
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56 #define R_DSI_HOST_GEN_VCID (0x30)
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57 #define R_DSI_HOST_MODE_CFG (0x34)
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58 #define R_DSI_HOST_VID_MODE_CFG (0x38)
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59 #define R_DSI_HOST_VID_PKT_SIZE (0x3C)
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60 #define R_DSI_HOST_VID_NUM_CHUNKS (0x40)
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61 #define R_DSI_HOST_VID_NULL_SIZE (0x44)
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62 #define R_DSI_HOST_VID_HSA_TIME (0x48)
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63 #define R_DSI_HOST_VID_HBP_TIME (0x4C)
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64 #define R_DSI_HOST_VID_HLINE_TIME (0x50)
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65 #define R_DSI_HOST_VID_VSA_LINES (0x54)
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66 #define R_DSI_HOST_VID_VBP_LINES (0x58)
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67 #define R_DSI_HOST_VID_VFP_LINES (0x5C)
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68 #define R_DSI_HOST_VID_VACTIVE_LINES (0x60)
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69 #define R_DSI_HOST_EDPI_CMD_SIZE (0x64)
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70 #define R_DSI_HOST_CMD_MODE_CFG (0x68)
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71 #define R_DSI_HOST_GEN_HDR (0x6C)
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72 #define R_DSI_HOST_GEN_PLD_DATA (0x70)
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73 #define R_DSI_HOST_CMD_PKT_STATUS (0x74)
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74 #define R_DSI_HOST_TO_CNT_CFG (0x78)
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75 #define R_DSI_HOST_HS_RD_TO_CNT (0x7C)
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76 #define R_DSI_HOST_LP_RD_TO_CNT (0x80)
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77 #define R_DSI_HOST_HS_WR_TO_CNT (0x84)
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78 #define R_DSI_HOST_LP_WR_TO_CNT (0x88)
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79 #define R_DSI_HOST_BTA_TO_CNT (0x8C)
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81 #define R_DSI_HOST_SDF_3D (0x90)
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83 #define R_DSI_HOST_LPCLK_CTRL (0x94)
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84 #define R_DSI_HOST_PHY_TMR_LPCLK_CFG (0x98)
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85 #define R_DSI_HOST_PHY_TMR_CFG (0x9C)
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86 #define R_DSI_HOST_INT_ST0 (0xBC)
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87 #define R_DSI_HOST_INT_ST1 (0xC0)
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88 #define R_DSI_HOST_INT_MSK0 (0xC4)
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89 #define R_DSI_HOST_INT_MSK1 (0xC8)
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90 #define R_DSI_HOST_PHY_STATUS (0xB0)
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93 typedef struct _DSIH1P21A_REG_T_
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95 union _DSIH1P21A_VERSION_tag_t {
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96 struct _DSIH1P21A_VERSION_map_t
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98 volatile unsigned int version :
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102 volatile unsigned int dwVersion;
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105 union _DSIH1P21A_PWR_UP_tag_t {
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106 struct _DSIH1P21A_PWR_UP_map_t
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108 volatile unsigned int power_up :
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109 1; //[0] 1 power up , 0 reset core
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110 volatile unsigned int reserved_0 :
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111 31; //[31:1] Reserved
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114 volatile unsigned int dValue;
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118 union _DSIH1P21A_CLKMGR_CFG_tag_t {
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119 struct _DSIH1P21A_CLKMGR_CFG_map_t
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121 volatile unsigned int tx_esc_clk_division :
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122 8; //[7:0] This field indicates the division factor for the TX Escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation
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123 volatile unsigned int to_clk_division :
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124 8; //[15:8] This field indicates the division factor for the Time Out clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
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125 volatile unsigned int reserved_0 :
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126 16; //[31:16] Reserved
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129 volatile unsigned int dValue;
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130 }CLKMGR_CFG;// 0x0008
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132 union _DSIH1P21A_DPI_VCID_tag_t {
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133 struct _DSIH1P21A_DPI_VCID_map_t
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135 volatile unsigned int dpi_vcid :
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136 2; //[1:0] This field configures the DPI virtual channel id that is indexed to the Video mode packets.
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137 volatile unsigned int reserved_0 :
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138 30; //[31:2] Reserved
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141 volatile unsigned int dValue;
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142 }DPI_VCID;// 0x000C
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143 //======================
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145 union _DSIH1P21A_DPI_COLOR_CODING_tag_t {
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146 struct _DSIH1P21A_DPI_COLOR_CODING_map_t
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148 volatile unsigned int dpi_color_coding :
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151 This field configures the DPI color coding as follows:
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152 0000: 16-bit configuration 1
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153 0001: 16-bit configuration 2
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154 0010: 16-bit configuration 3
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155 0011: 18-bit configuration 1
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156 0100: 18-bit configuration 2
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158 0110: 20-bit YCbCr 4:2:2 loosely packed
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159 0111: 24-bit YCbCr 4:2:2
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160 1000: 16-bit YCbCr 4:2:2
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163 1011-1111: 12-bit YCbCr 4:2:0
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164 Note: If the eDPI interface is chosen and currently works in the
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165 Command mode (cmd_video_mode = 1), then
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168 volatile unsigned int reserved_0 :
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169 4; //[7:4] Reserved
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170 volatile unsigned int loosely18_en :
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171 1; //[8] When set to 1, this bit activates loosely packed variant to 18-bit configurations.
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172 volatile unsigned int reserved_1 :
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173 23; //[31:9] Reserved
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176 volatile unsigned int dValue;
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177 }DPI_COLOR_CODING;// 0x0010
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180 union _DSIH1P21A_DPI_CFG_POL_tag_t {
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181 struct _DSIH1P21A_DPI_CFG_POL_map_t
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183 volatile unsigned int dataen_active_low :
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184 1; //[0] When set to 1, this bit configures the data enable pin (dpidataen) asactive low.
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185 volatile unsigned int vsync_active_low :
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186 1; //[1] When set to 1, this bit configures the vertical synchronism pin (dpivsync) as active low.
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187 volatile unsigned int hsync_active_low :
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188 1; //[2] When set to 1, this bit configures the horizontal synchronism pin (dpihsync) as active low.
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189 volatile unsigned int shutd_active_low :
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190 1; //[3] When set to 1, this bit configures the shutdown pin (dpishutdn) as active low
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191 volatile unsigned int colorm_active_low :
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192 1; //[4] When set to 1, this bit configures the color mode pin (dpicolorm) as active low.
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193 volatile unsigned int reserved_0 :
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197 volatile unsigned int dValue;
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198 }DPI_CFG_POL;// 0x0014
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201 union _DSIH1P21A_DPI_LP_CMD_TIM_tag_t {
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202 struct _DSIH1P21A_DPI_LP_CMD_TIM_map_t
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204 volatile unsigned int invact_lpcmd_time :
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205 8; //[7:0] This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during the VACT region.
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206 volatile unsigned int reserved_0 :
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207 8; //[15:8] Reserved
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208 volatile unsigned int outvact_lpcmd_time :
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209 8; //[23:16] This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during the VSA, VBP, and VFP regions.
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210 volatile unsigned int reserved_1 :
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211 8; //[31:24] Reserved
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214 volatile unsigned int dValue;
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215 }DPI_LP_CMD_TIM;// 0x0018
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217 union _DSIH1P21A_DBI_VCID_tag_t {
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218 struct _DSIH1P21A_DBI_VCID_map_t
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220 volatile unsigned int dbi_vcid :
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221 2; //[1:0] This field configures the virtual channel id that is indexed to the DCS packets from DBI.
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222 volatile unsigned int reserved_0 :
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223 30; //[31:2] Reserved
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226 volatile unsigned int dValue;
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227 }DBI_VCID;// 0x001C
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229 union _DSIH1P21A_DBI_CFG_tag_t {
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230 struct _DSIH1P21A_DBI_CFG_map_t
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232 volatile unsigned int in_dbi_conf :
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235 This field configures the DBI input pixel data as follows:
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243 0111: 16-bit 12 bpp
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244 1000: 16-bit 16 bpp
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245 1001: 16-bit 18 bpp, option 1
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246 1010: 16-bit 18 bpp, option 2
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247 1011: 16-bit 24 bpp, option 1
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248 1100: 16-bit 24 bpp, option 2
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250 volatile unsigned int reserved_0 :
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251 4; //[7:4] Reserved
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252 volatile unsigned int out_dbi_conf :
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255 This field configures the DBI output pixel data as follows:
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263 0111: 16-bit 12 bpp
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264 1000: 16-bit 16 bpp
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265 1001: 16-bit 18 bpp, option 1
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266 1010: 16-bit 18 bpp, option 2
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267 1011: 16-bit 24 bpp, option 1
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268 1100: 16-bit 24 bpp, option 2
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270 volatile unsigned int reserved_1 :
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271 4; //[15:12] Reserved
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273 volatile unsigned int lut_size_conf :
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276 This field configures the size used to transport the write Lut
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277 commands as follows:
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278 00: 16-bit color display
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279 01: 18-bit color display
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280 10: 24-bit color display
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281 11: 16-bit color display
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284 volatile unsigned int reserved_2 :
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285 14; //[31:18] Reserved
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288 volatile unsigned int dValue;
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291 union _DSIH1P21A_DBI_PARTITIONING_EN_tag_t {
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292 struct _DSIH1P21A_DBI_PARTITIONING_EN_map_t
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294 volatile unsigned int partitioning_en :
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297 When set to 1, this bit enables the use of write_memory_continue
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298 input commands (system needs to ensure correct partitioning of Long
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299 Write commands). When not set, partitioning is automatically
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300 performed in the DWC_mipi_dsi_host.
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302 volatile unsigned int reserved_0 :
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303 31; //[31:1] Reserved
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306 volatile unsigned int dValue;
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307 }DBI_PARTITIONING_EN;// 0x0024
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309 union _DSIH1P21A_DBI_CMDSIZE_tag_t {
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310 struct _DSIH1P21A_DBI_CMDSIZE_map_t
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312 volatile unsigned int wr_cmd_size :
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315 This field configures the size of the DCS write memory commands.
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316 The size of DSI packet payload is the actual payload size minus 1,
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317 because the DCS command is in the DSI packet payload
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319 volatile unsigned int allowed_cmd_size :
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322 This field configures the maximum allowed size for a DCS write
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323 memory command. This field is used to partition a write memory
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324 command into one write_memory_start and a variable number of
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325 write_memory_continue commands. It is only used if the
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326 partitioning_en bit of the DBI_CFG register is disabled.
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327 The size of the DSI packet payload is the actual payload size minus 1,
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328 because the DCS command is in the DSI packet payload.
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333 volatile unsigned int dValue;
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334 }DBI_CMDSIZE;// 0x0028
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336 union _DSIH1P21A_PCKHDL_CFG_tag_t {
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337 struct _DSIH1P21A_PCKHDL_CFG_map_t
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339 volatile unsigned int eotp_tx_en :
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340 1; //[0] When set to 1, this bit enables the EoTp transmission
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341 volatile unsigned int eotp_rx_en :
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342 1; //[1] When set to 1, this bit enables the EoTp reception.
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343 volatile unsigned int bta_en :
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344 1; //[2] When set to 1, this bit enables the Bus Turn-Around (BTA) request.
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345 volatile unsigned int ecc_rx_en :
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346 1; //[3] When set to 1, this bit enables the ECC reception, error correction, and reporting.
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347 volatile unsigned int crc_rx_en :
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348 1; //[4] When set to 1, this bit enables the CRC reception and error reporting. Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or DSI_GENERIC = 1. Otherwise, this bit is reserved.
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349 volatile unsigned int reserved_0 :
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353 volatile unsigned int dValue;
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354 }PCKHDL_CFG;// 0x002C
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356 union _DSIH1P21A_GEN_VCID_tag_t {
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357 struct _DSIH1P21A_GEN_VCID_map_t
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359 volatile unsigned int gen_vcid_rx :
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360 2; //[1:0] This field indicates the Generic interface read-back virtual channel identification.
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361 volatile unsigned int reserved_0 :
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362 30; //[31:2] Reserved
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365 volatile unsigned int dValue;
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366 }GEN_VCID;// 0x0030
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368 union _DSIH1P21A_MODE_CFG_tag_t {
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369 struct _DSIH1P21A_MODE_CFG_map_t
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371 volatile unsigned int cmd_video_mode :
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372 1; //[0] This bit configures the operation mode:0: Video mode ; 1: Command mode
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373 volatile unsigned int reserved_0 :
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374 31; //[31:1] Reserved
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377 volatile unsigned int dValue;
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378 }MODE_CFG;// 0x0034
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380 union _DSIH1P21A_VID_MODE_CFG_tag_t {
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381 struct _DSIH1P21A_VID_MODE_CFG_map_t
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383 volatile unsigned int vid_mode_type :
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386 This field indicates the video mode transmission type as follows:
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387 00: Non-burst with sync pulses
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388 01: Non-burst with sync events
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389 10 and 11: Burst mode
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391 volatile unsigned int reserved_0 :
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393 volatile unsigned int lp_vsa_en :
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394 1; //[8] When set to 1, this bit enables the return to low-power inside the VSA period when timing allows.
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395 volatile unsigned int lp_vbp_en :
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396 1; //[9] When set to 1, this bit enables the return to low-power inside the VBP period when timing allows.
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397 volatile unsigned int lp_vfp_en :
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398 1; //[10] When set to 1, this bit enables the return to low-power inside the VFP period when timing allows.
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399 volatile unsigned int lp_vact_en :
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400 1; //[11] When set to 1, this bit enables the return to low-power inside the VACT period when timing allows.
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401 volatile unsigned int lp_hbp_en :
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402 1; //[12] When set to 1, this bit enables the return to low-power inside the HBP period when timing allows.
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403 volatile unsigned int lp_hfp_en :
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404 1; //[13] When set to 1, this bit enables the return to low-power inside the HFP period when timing allows.
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405 volatile unsigned int frame_bta_ack_en :
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406 1; //[14] When set to 1, this bit enables the request for an acknowledgeresponse at the end of a frame
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407 volatile unsigned int lp_cmd_en :
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408 1; //[15] When set to 1, this bit enables the command transmission only in lowpower mode.
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409 volatile unsigned int reserved_1 :
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413 volatile unsigned int dValue;
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414 }VID_MODE_CFG;// 0x0038
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416 union _DSIH1P21A_VID_PKT_SIZE_tag_t {
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417 struct _DSIH1P21A_VID_PKT_SIZE_map_t
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419 volatile unsigned int vid_pkt_size :
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420 14; //[13:0] This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2, as described in the DSI specification.
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421 volatile unsigned int reserved_0 :
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422 18; //[31:14] Reserved
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425 volatile unsigned int dValue;
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426 }VID_PKT_SIZE;// 0x003C
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428 union _DSIH1P21A_VID_NUM_CHUNKS_tag_t {
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429 struct _DSIH1P21A_VID_NUM_CHUNKS_map_t
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431 volatile unsigned int vid_num_chunks :
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434 This register configures the number of chunks to be transmitted during
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435 a Line period (a chunk consists of a video packet and a null packet).
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436 If set to 0 or 1, the video line is transmitted in a single packet.
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437 If set to 1, the packet is part of a chunk, so a null packet follows it if
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438 vid_null_size > 0. Otherwise, multiple chunks are used to transmit each video line.
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440 volatile unsigned int reserved_0 :
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441 19; //[31:13] Reserved
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444 volatile unsigned int dValue;
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445 }VID_NUM_CHUNKS;// 0x0040
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447 union _DSIH1P21A_VID_NULL_SIZE_tag_t {
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448 struct _DSIH1P21A_VID_NULL_SIZE_map_t
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450 volatile unsigned int vid_null_size :
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453 This register configures the number of bytes inside a null packet.
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454 Setting it to 0 disables the null packets.
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456 volatile unsigned int reserved_0 :
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457 19; //[31:13] Reserved
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460 volatile unsigned int dValue;
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461 }VID_NULL_SIZE;// 0x0044
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463 union _DSIH1P21A_VID_HSA_TIME_tag_t {
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464 struct _DSIH1P21A_VID_HSA_TIME_map_t
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466 volatile unsigned int vid_hsa_time :
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467 12; //[11:0] This field configures the Horizontal Synchronism Active period in lane byte clock cycles
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468 volatile unsigned int reserved_0 :
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469 20; //[31:12] Reserved
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472 volatile unsigned int dValue;
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473 }VID_HSA_TIME;// 0x0048
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475 union _DSIH1P21A_VID_HBP_TIME_tag_t {
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476 struct _DSIH1P21A_VID_HBP_TIME_map_t
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478 volatile unsigned int vid_hbp_time :
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479 12; //[11:0] This field configures the Horizontal Back Porch period in lane byte clock cycles.
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480 volatile unsigned int reserved_0 :
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481 20; //[31:12] Reserved
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484 volatile unsigned int dValue;
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485 }VID_HBP_TIME;// 0x004C
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487 union _DSIH1P21A_VID_HLINE_TIME_tag_t {
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488 struct _DSIH1P21A_VID_HLINE_TIME_map_t
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490 volatile unsigned int vid_hline_time :
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491 15; //[14:0] This field configures the size of the total line time (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.
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492 volatile unsigned int reserved_0 :
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493 17; //[31:15] Reserved
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496 volatile unsigned int dValue;
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497 }VID_HLINE_TIME;// 0x0050
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499 union _DSIH1P21A_VID_VSA_LINES_tag_t {
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500 struct _DSIH1P21A_VID_VSA_LINES_map_t
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502 volatile unsigned int vsa_lines :
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503 10; //[9:0] This field configures the Vertical Synchronism Active period measured in number of horizontal lines
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504 volatile unsigned int reserved_0 :
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505 22; //[31:10] Reserved
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508 volatile unsigned int dValue;
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509 }VID_VSA_LINES;// 0x0054
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511 union _DSIH1P21A_VID_VBP_LINES_tag_t {
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512 struct _DSIH1P21A_VID_VBP_LINES_map_t
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514 volatile unsigned int vbp_lines :
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515 10; //[9:0] This field configures the Vertical Back Porch period measured in number of horizontal lines.
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516 volatile unsigned int reserved_0 :
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517 22; //[31:10] Reserved
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520 volatile unsigned int dValue;
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521 }VID_VBP_LINES;// 0x0058
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523 union _DSIH1P21A_VID_VFP_LINES_tag_t {
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524 struct _DSIH1P21A_VID_VFP_LINES_map_t
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526 volatile unsigned int vfp_lines :
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527 10; //[9:0] This field configures the Vertical Front Porch period measured in number of horizontal lines.
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528 volatile unsigned int reserved_0 :
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529 22; //[31:10] Reserved
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532 volatile unsigned int dValue;
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533 }VID_VFP_LINES;// 0x005C
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535 union _DSIH1P21A_VID_VACTIVE_LINES_tag_t {
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536 struct _DSIH1P21A_VID_VACTIVE_LINES_map_t
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538 volatile unsigned int v_active_lines :
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539 14; //[13:0] This field configures the Vertical Active period measured in number of horizontal lines.
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540 volatile unsigned int reserved_0 :
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541 18; //[31:14] Reserved
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544 volatile unsigned int dValue;
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545 }VID_VACTIVE_LINES;// 0x0060
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547 union _DSIH1P21A_EDPI_CMD_SIZE_tag_t {
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548 struct _DSIH1P21A_EDPI_CMD_SIZE_map_t
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550 volatile unsigned int edpi_allowed_cmd_size :
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551 16; //[15:0] This field configures the maximum allowed size for an eDPI write memory command, measured in pixels. Automatic partitioning of data obtained from eDPI is permanently enabled.
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552 volatile unsigned int reserved_0 :
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553 16; //[31:16] Reserved
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556 volatile unsigned int dValue;
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557 }EDPI_CMD_SIZE;// 0x0064
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559 union _DSIH1P21A_CMD_MODE_CFG_tag_t {
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560 struct _DSIH1P21A_CMD_MODE_CFG_map_t
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562 volatile unsigned int tear_fx_en :
\r
563 1; //[0] When set to 1, this bit enables the tearing effect acknowledge request.
\r
564 volatile unsigned int ack_rqst_en :
\r
565 1; //[1] When set to 1, this bit enables the acknowledge request after each packet transmission.
\r
566 volatile unsigned int reserved_0 :
\r
568 volatile unsigned int gen_sw_0p_tx :
\r
569 1; //[8] This bit configures the Generic short write packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
570 volatile unsigned int gen_sw_1p_tx :
\r
571 1; //[9] This bit configures the Generic short write packet with one parameter command transmission type: 0: High-speed 1: Low-power
\r
572 volatile unsigned int gen_sw_2p_tx :
\r
573 1; //[10] This bit configures the Generic short write packet with two parameters command transmission type:0: High-speed 1: Low-power
\r
574 volatile unsigned int gen_sr_0p_tx :
\r
575 1; //[11] This bit configures the Generic short read packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
576 volatile unsigned int gen_sr_1p_tx :
\r
577 1; //[12] This bit configures the Generic short read packet with one parameter command transmission type:0: High-speed 1: Low-power
\r
578 volatile unsigned int gen_sr_2p_tx :
\r
579 1; //[13] This bit configures the Generic short read packet with two parameters command transmission type:0: High-speed 1: Low-power
\r
580 volatile unsigned int gen_lw_tx :
\r
581 1; //[14] This bit configures the Generic long write packet command transmission type:0: High-speed 1: Low-power
\r
582 volatile unsigned int reserved_1 :
\r
584 volatile unsigned int dcs_sw_0p_tx :
\r
585 1; //[16] This bit configures the DCS short write packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
586 volatile unsigned int dcs_sw_1p_tx :
\r
587 1; //[17] This bit configures the DCS short write packet with one parameter command transmission type:0: High-speed 1: Low-power
\r
588 volatile unsigned int dcs_sr_0p_tx :
\r
589 1; //[18] This bit configures the DCS short read packet with zero parameter command transmission type:0: High-speed 1: Low-power
\r
590 volatile unsigned int dcs_lw_tx :
\r
591 1; //[19] This bit configures the DCS long write packet command transmission type:0: High-speed 1: Low-power
\r
592 volatile unsigned int reserved_2 :
\r
594 volatile unsigned int max_rd_pkt_size :
\r
595 1; //[24] This bit configures the maximum read packet size command transmission type:0: High-speed 1: Low-power
\r
596 volatile unsigned int reserved_3 :
\r
600 volatile unsigned int dValue;
\r
601 }CMD_MODE_CFG;// 0x0068
\r
603 union _DSIH1P21A_GEN_HDR_tag_t {
\r
604 struct _DSIH1P21A_GEN_HDR_map_t
\r
606 volatile unsigned int gen_dt :
\r
607 6; //[5:0] This field configures the packet data type of the header packet.
\r
608 volatile unsigned int gen_vc :
\r
609 2; //[7:6] Reserved
\r
610 volatile unsigned int gen_wc_lsbyte :
\r
611 8; //[15:8] This field configures the least significant byte of the header packet's Word count for long packets or data 0 for short packets.
\r
612 volatile unsigned int gen_wc_msbyte :
\r
613 8; //[23:16] This field configures the most significant byte of the header packet's word count for long packets or data 1 for short packets.
\r
614 volatile unsigned int reserved_0 :
\r
615 8; //[31:24] Reserved
\r
618 volatile unsigned int dValue;
\r
621 union _DSIH1P21A_GEN_PLD_DATA_tag_t {
\r
622 struct _DSIH1P21A_GEN_PLD_DATA_map_t
\r
624 volatile unsigned int gen_pld_b1 :
\r
625 8; //[7:0] This field indicates byte 1 of the packet payload.
\r
626 volatile unsigned int gen_pld_b2 :
\r
627 8; //[15:8] This field indicates byte 2 of the packet payload.
\r
628 volatile unsigned int gen_pld_b3 :
\r
629 8; //[23:16] This field indicates byte 3 of the packet payload.
\r
630 volatile unsigned int gen_pld_b4 :
\r
631 8; //[31:24] This field indicates byte 4 of the packet payload.
\r
634 volatile unsigned int dValue;
\r
635 }GEN_PLD_DATA;// 0x0070
\r
637 union _DSIH1P21A_CMD_PKT_STATUS_tag_t {
\r
638 struct _DSIH1P21A_CMD_PKT_STATUS_map_t
\r
640 volatile unsigned int gen_cmd_empty :
\r
643 This bit indicates the empty status of the generic command FIFO.
\r
644 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
645 Value after reset: 0x1
\r
647 volatile unsigned int gen_cmd_full :
\r
650 This bit indicates the full status of the generic command FIFO.
\r
651 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
652 Value after reset: 0x0
\r
654 volatile unsigned int gen_pld_w_empty :
\r
657 This bit indicates the empty status of the generic write payload FIFO.
\r
658 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
659 Value after reset: 0x1
\r
661 volatile unsigned int gen_pld_w_full :
\r
664 This bit indicates the full status of the generic write payload FIFO.
\r
665 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
666 Value after reset: 0x0
\r
668 volatile unsigned int gen_pld_r_empty :
\r
671 This bit indicates the empty status of the generic read payload FIFO.
\r
672 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
673 Value after reset: 0x1
\r
675 volatile unsigned int gen_pld_r_full :
\r
678 This bit indicates the full status of the generic read payload FIFO.
\r
679 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
680 Value after reset: 0x0
\r
682 volatile unsigned int gen_rd_cmd_busy :
\r
685 This bit is set when a read command is issued and cleared when the
\r
686 entire response is stored in the FIFO.
\r
687 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
688 Value after reset: 0x0
\r
690 volatile unsigned int reserved_0 :
\r
694 volatile unsigned int dbi_cmd_empy :
\r
697 This bit indicates the empty status of the DBI command FIFO.
\r
698 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
699 Otherwise, this bit is reserved.
\r
700 Value after reset: 0x1
\r
702 volatile unsigned int dbi_cmd_full :
\r
705 This bit indicates the full status of the DBI command FIFO.
\r
706 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
707 Otherwise, this bit is reserved.
\r
708 Value after reset: 0x0
\r
710 volatile unsigned int dbi_pld_w_empty :
\r
713 This bit indicates the empty status of the DBI write payload FIFO.
\r
714 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
715 Otherwise, this bit is reserved.
\r
716 Value after reset: 0x1
\r
718 volatile unsigned int dbi_pld_w_full :
\r
721 This bit indicates the full status of the DBI write payload FIFO.
\r
722 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
723 Otherwise, this bit is reserved.
\r
724 Value after reset: 0x0
\r
726 volatile unsigned int dbi_pld_r_empty :
\r
729 This bit indicates the empty status of the DBI read payload FIFO.
\r
730 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
731 Otherwise, this bit is reserved.
\r
732 Value after reset: 0x1
\r
734 volatile unsigned int dbi_pld_r_full :
\r
737 This bit indicates the full status of the DBI read payload FIFO.
\r
738 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
739 Otherwise, this bit is reserved.
\r
740 Value after reset: 0x0
\r
742 volatile unsigned int dbi_rd_cmd_busy :
\r
745 This bit is set when a read command is issued and cleared when the
\r
746 entire response is stored in the FIFO.
\r
747 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
748 Otherwise, this bit is reserved.
\r
749 Value after reset: 0x0
\r
751 volatile unsigned int reserved_1 :
\r
755 volatile unsigned int dValue;
\r
757 CMD_PKT_STATUS;// 0x0074
\r
759 union _DSIH1P21A_TO_CNT_CFG_tag_t {
\r
760 struct _DSIH1P21A_TO_CNT_CFG_map_t
\r
762 volatile unsigned int lprx_to_cnt :
\r
765 This field configures the timeout counter that triggers a low-power
\r
766 reception timeout contention detection (measured in
\r
767 TO_CLK_DIVISION cycles).
\r
769 volatile unsigned int hstx_to_cnt :
\r
772 This field configures the timeout counter that triggers a high-speed
\r
773 transmission timeout contention detection (measured in
\r
774 TO_CLK_DIVISION cycles).
\r
775 If using the non-burst mode and there is no sufficient time to switch
\r
776 from HS to LP and back in the period which is from one line data
\r
777 finishing to the next line sync start, the DSI link returns the LP state
\r
778 once per frame, then you should configure the TO_CLK_DIVISION
\r
779 and hstx_to_cnt to be in accordance with:
\r
780 hstx_to_cnt * lanebyteclkperiod * TO_CLK_DIVISION >= the time of
\r
781 one FRAME data transmission * (1 + 10%)
\r
782 In burst mode, RGB pixel packets are time-compressed, leaving more
\r
783 time during a scan line. Therefore, if in burst mode and there is
\r
784 sufficient time to switch from HS to LP and back in the period of time
\r
785 from one line data finishing to the next line sync start, the DSI link can
\r
786 return LP mode and back in this time interval to save power. For this,
\r
787 configure the TO_CLK_DIVISION and hstx_to_cnt to be in accordance
\r
789 hstx_to_cnt * lanebyteclkperiod * TO_CLK_DIVISION >= the time of
\r
790 one LINE data transmission * (1 + 10%)
\r
794 volatile unsigned int dValue;
\r
796 TO_CNT_CFG;// 0x0078
\r
798 union _DSIH1P21A_HS_RD_TO_CNT_tag_t {
\r
799 struct _DSIH1P21A_HS_RD_TO_CNT_map_t
\r
801 volatile unsigned int hs_rd_to_cnt :
\r
804 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
805 link still, after sending a high-speed read operation. This period is
\r
806 measured in cycles of lanebyteclk. The counting starts when the
\r
807 D-PHY enters the Stop state and causes no interrupts.
\r
809 volatile unsigned int reserved_0 :
\r
813 volatile unsigned int dValue;
\r
815 HS_RD_TO_CNT;// 0x007C
\r
817 union _DSIH1P21A_LP_RD_TO_CNT_tag_t {
\r
818 struct _DSIH1P21A_LP_RD_TO_CNT_map_t
\r
820 volatile unsigned int lp_rd_to_cnt :
\r
823 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
824 link still, after sending a low-power read operation. This period is
\r
825 measured in cycles of lanebyteclk. The counting starts when the
\r
826 D-PHY enters the Stop state and causes no interrupts.
\r
828 volatile unsigned int reserved_0 :
\r
832 volatile unsigned int dValue;
\r
834 LP_RD_TO_CNT;// 0x0080
\r
836 union _DSIH1P21A_HS_WR_TO_CNT_tag_t {
\r
837 struct _DSIH1P21A_HS_WR_TO_CNT_map_t
\r
839 volatile unsigned int hs_wr_to_cnt :
\r
842 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
843 link inactive after sending a high-speed write operation. This period is
\r
844 measured in cycles of lanebyteclk. The counting starts when the
\r
845 D-PHY enters the Stop state and causes no interrupts.
\r
847 volatile unsigned int reserved_0 :
\r
849 volatile unsigned int presp_to_mode :
\r
852 When set to 1, this bit ensures that the peripheral response timeout
\r
853 caused by hs_wr_to_cnt is used only once per eDPI frame, when both
\r
854 the following conditions are met:
\r
855 dpivsync_edpiwms has risen and fallen.
\r
856 Packets originated from eDPI have been transmitted and its FIFO
\r
858 In this scenario no non-eDPI requests are sent to the D-PHY, even if
\r
859 there is traffic from generic or DBI ready to be sent, making it return to
\r
860 stop state. When it does so, PRESP_TO counter is activated and only
\r
861 when it finishes does the controller send any other traffic that is ready.
\r
862 Dependency: DSI_DATAINTERFACE = 4. Otherwise, this bit is
\r
865 volatile unsigned int reserved_1 :
\r
869 volatile unsigned int dValue;
\r
871 HS_WR_TO_CNT;// 0x0084
\r
873 union _DSIH1P21A_LP_WR_TO_CNT_tag_t {
\r
874 struct _DSIH1P21A_LP_WR_TO_CNT_map_t
\r
876 volatile unsigned int lp_wr_to_cnt :
\r
879 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
880 link still, after sending a low-power write operation. This period is
\r
881 measured in cycles of lanebyteclk. The counting starts when the
\r
882 D-PHY enters the Stop state and causes no interrupts
\r
884 volatile unsigned int reserved_0 :
\r
888 volatile unsigned int dValue;
\r
890 LP_WR_TO_CNT;// 0x0088
\r
892 union _DSIH1P21A_BTA_TO_CNT_tag_t {
\r
893 struct _DSIH1P21A_BTA_TO_CNT_map_t
\r
895 volatile unsigned int bta_to_cnt :
\r
898 This field sets a period for which the DWC_mipi_dsi_host keeps the
\r
899 link still, after completing a Bus Turn-Around. This period is measured
\r
900 in cycles of lanebyteclk. The counting starts when the D-PHY enters
\r
901 the Stop state and causes no interrupts.
\r
903 volatile unsigned int reserved_0 :
\r
907 volatile unsigned int dValue;
\r
909 BTA_TO_CNT;// 0x008C
\r
911 union _DSIH1P21A_SDF_3D_tag_t {
\r
912 struct _DSIH1P21A_SDF_3D_map_t
\r
914 volatile unsigned int mode_3d :
\r
917 This field defines the 3D mode on/off and display orientation:
\r
918 00: 3D mode off (2D mode on)
\r
919 01: 3D mode on, portrait orientation
\r
920 10: 3D mode on, landscape orientation
\r
924 volatile unsigned int ormat_3d :
\r
927 This field defines the 3D image format:
\r
928 00: Line (alternating lines of left and right data)
\r
929 01: Frame (alternating frames of left and right data)
\r
930 10: Pixel (alternating pixels of left and right data)
\r
934 volatile unsigned int second_vsync :
\r
937 This field defines whether there is a second VSYNC pulse between
\r
938 Left and Right Images, when 3D Image Format is Frame-based:
\r
939 0: No sync pulses between left and right data
\r
940 1: Sync pulse (HSYNC, VSYNC, blanking) between left and right
\r
943 volatile unsigned int right_first :
\r
946 This bit defines the left or right order:
\r
947 0: Left eye data is sent first, and then the right eye data is sent.
\r
948 1: Right eye data is sent first, and then the left eye data is sent.
\r
950 volatile unsigned int reserved_0 :
\r
952 volatile unsigned int send_3d_cfg :
\r
955 When set, causes the next VSS packet to include 3D control payload
\r
956 in every VSS packet.
\r
958 volatile unsigned int reserved_1 :
\r
962 volatile unsigned int dValue;
\r
966 union _DSIH1P21A_LPCLK_CTRL_tag_t {
\r
967 struct _DSIH1P21A_LPCLK_CTRL_map_t
\r
969 volatile unsigned int phy_txrequestclkhs :
\r
970 1; //[0] This bit controls the D-PHY PPI txrequestclkhs signal
\r
971 volatile unsigned int auto_clklane_ctrl :
\r
972 1; //[0] This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows
\r
973 volatile unsigned int reserved_0 :
\r
977 volatile unsigned int dValue;
\r
979 LPCLK_CTRL;// 0x0094
\r
981 union _DSIH1P21A_PHY_TMR_LPCLK_CFG_tag_t {
\r
982 struct _DSIH1P21A_PHY_TMR_LPCLK_CFG_map_t
\r
984 volatile unsigned int phy_clklp2hs_time :
\r
987 This field configures the maximum time that the D-PHY clock lane
\r
988 takes to go from low-power to high-speed transmission measured in
\r
989 lane byte clock cycles.
\r
991 volatile unsigned int reserved_0 :
\r
993 volatile unsigned int phy_clkhs2lp_time :
\r
996 This field configures the maximum time that the D-PHY clock lane
\r
997 takes to go from high-speed to low-power transmission measured in
\r
998 lane byte clock cycles.
\r
1000 volatile unsigned int reserved_1 :
\r
1004 volatile unsigned int dValue;
\r
1006 PHY_TMR_LPCLK_CFG;// 0x0098
\r
1008 union _DSIH1P21A_PHY_TMR_CFG_tag_t {
\r
1009 struct _DSIH1P21A_PHY_TMR_CFG_map_t
\r
1011 volatile unsigned int max_rd_time :
\r
1014 This field configures the maximum time required to perform a read
\r
1015 command in lane byte clock cycles. This register can only be modified
\r
1016 when no read command is in progress.
\r
1018 volatile unsigned int reserved_0 :
\r
1020 volatile unsigned int phy_lp2hs_time :
\r
1023 This field configures the maximum time that the D-PHY data lanes
\r
1024 take to go from low-power to high-speed transmission measured in
\r
1025 lane byte clock cycles.
\r
1027 volatile unsigned int phy_hs2lp_time :
\r
1030 This field configures the maximum time that the D-PHY data lanes
\r
1031 take to go from high-speed to low-power transmission measured in
\r
1032 lane byte clock cycles.
\r
1036 volatile unsigned int dValue;
\r
1037 } PHY_TMR_CFG;// 0x009C
\r
1039 union _DSIH1P21A_PHY_RSTZ_tag_t {
\r
1040 struct _DSIH1P21A_PHY_RSTZ_map_t
\r
1042 volatile unsigned int phy_shutdownz :
\r
1043 1; //[0] When set to 0, this bit places the D-PHY macro in power-down state
\r
1044 volatile unsigned int phy_rstz :
\r
1045 1; //[1] When set to 0, this bit places the digital section of the D-PHY in the reset state.
\r
1046 volatile unsigned int phy_enableclk :
\r
1047 1; //[2] When set to1, this bit enables the D-PHY Clock Lane module.
\r
1048 volatile unsigned int phy_forcepll :
\r
1051 When the D-PHY is in ULPS, this bit enables the D-PHY PLL.
\r
1052 Dependency: DSI_HOST_FPGA = 0. Otherwise, this bit is reserved
\r
1054 volatile unsigned int reserved_0 :
\r
1058 volatile unsigned int dValue;
\r
1060 } PHY_RSTZ;// 0x00A0
\r
1062 union _DSIH1P21A_PHY_IF_CFG_tag_t {
\r
1063 struct _DSIH1P21A_PHY_IF_CFG_map_t
\r
1065 volatile unsigned int n_lanes :
\r
1068 This field configures the number of active data lanes:
\r
1069 00: One data lane (lane 0)
\r
1070 01: Two data lanes (lanes 0 and 1)
\r
1071 10: Three data lanes (lanes 0, 1, and 2)
\r
1072 11: Four data lanes (lanes 0, 1, 2, and 3)
\r
1074 volatile unsigned int reserved_0 :
\r
1076 volatile unsigned int phy_stop_wait_time :
\r
1077 8; //[15:8] This field configures the minimum wait period to request a high-speed transmission after the Stop state.
\r
1078 volatile unsigned int reserved_1 :
\r
1082 volatile unsigned int dValue;
\r
1083 }PHY_IF_CFG;// 0x00A4
\r
1085 union _DSIH1P21A_PHY_ULPS_CTRL_tag_t {
\r
1086 struct _DSIH1P21A_PHY_ULPS_CTRL_map_t
\r
1088 volatile unsigned int phy_txrequlpsclk :
\r
1089 1; //[0] ULPS mode Request on clock lane.
\r
1090 volatile unsigned int phy_txexitulpsclk :
\r
1091 1; //[1] ULPS mode Exit on clock lane.
\r
1092 volatile unsigned int phy_txrequlpslan :
\r
1093 1; //[2] ULPS mode Request on all active data lanes.
\r
1094 volatile unsigned int phy_txexitulpslan :
\r
1095 1; //[3] ULPS mode Exit on all active data lanes.
\r
1096 volatile unsigned int reserved_0 :
\r
1100 volatile unsigned int dValue;
\r
1102 PHY_ULPS_CTRL;// 0x00A8
\r
1104 union _DSIH1P21A_PHY_TX_TRIGGERS_tag_t {
\r
1105 struct _DSIH1P21A_PHY_TX_TRIGGERS_map_t
\r
1107 volatile unsigned int phy_tx_triggers :
\r
1108 4; //[3:0] This field controls the trigger transmissions
\r
1109 volatile unsigned int reserved_0 :
\r
1113 volatile unsigned int dValue;
\r
1115 PHY_TX_TRIGGERS;// 0x00AC
\r
1117 union _DSIH1P21A_PHY_STATUS_tag_t {
\r
1118 struct _DSIH1P21A_PHY_STATUS_map_t
\r
1120 volatile unsigned int phy_lock :
\r
1121 1; //[0] This bit indicates the status of phylock D-PHY signal.
\r
1122 volatile unsigned int phy_direction :
\r
1123 1; //[1] This bit indicates the status of phydirection D-PHY signal.
\r
1124 volatile unsigned int phy_stopstateclklane :
\r
1125 1; //[2] This bit indicates the status of phystopstateclklane D-PHY signal.
\r
1126 volatile unsigned int phy_ulpsactivenotclk :
\r
1127 1; //[3] This bit indicates the status of phyulpsactivenotclk D-PHY signal.
\r
1128 volatile unsigned int phy_stopstate0lane :
\r
1129 1; //[4] This bit indicates the status of phystopstate0lane D-PHY signal.
\r
1130 volatile unsigned int phy_ulpsactivenot0lane :
\r
1131 1; //[5] This bit indicates the status of ulpsactivenot0lane D-PHY signal.
\r
1132 volatile unsigned int phy_rxulpsesc0lane :
\r
1133 1; //[6] This bit indicates the status of rxulpsesc0lane D-PHY signal.
\r
1134 volatile unsigned int phy_stopstate1lane :
\r
1137 This bit indicates the status of phystopstate1lane D-PHY signal.
\r
1138 Dependency: DSI_HOST_NUMBER_OF_LANES > 1
\r
1139 If DSI_HOST_NUMBER_OF_LANES <= 1, this bit is reserved.
\r
1141 volatile unsigned int phy_ulpsactivenot1lane :
\r
1144 This bit indicates the status of ulpsactivenot1lane D-PHY signal.
\r
1145 Dependency: DSI_HOST_NUMBER_OF_LANES > 1
\r
1146 If DSI_HOST_NUMBER_OF_LANES <= 1, this bit is reserved.
\r
1148 volatile unsigned int phy_stopstate2lane :
\r
1151 This bit indicates the status of phystopstate2lane D-PHY signal.
\r
1152 Dependency: DSI_HOST_NUMBER_OF_LANES > 2
\r
1153 If DSI_HOST_NUMBER_OF_LANES <= 2, this bit is reserved.
\r
1155 volatile unsigned int phy_ulpsactivenot2lane :
\r
1158 This bit indicates the status of ulpsactivenot2lane D-PHY signal.
\r
1159 Dependency: DSI_HOST_NUMBER_OF_LANES > 2
\r
1160 If DSI_HOST_NUMBER_OF_LANES <= 2, this bit is reserved.
\r
1162 volatile unsigned int phy_stopstate3lane :
\r
1165 This bit indicates the status of phystopstate3lane D-PHY signal.
\r
1166 Dependency: DSI_HOST_NUMBER_OF_LANES > 3
\r
1167 If DSI_HOST_NUMBER_OF_LANES <= 3, this bit is reserved
\r
1169 volatile unsigned int phy_ulpsactivenot3lane :
\r
1172 This bit indicates the status of ulpsactivenot3lane D-PHY signal.
\r
1173 Dependency: DSI_HOST_NUMBER_OF_LANES > 3
\r
1174 If DSI_HOST_NUMBER_OF_LANES <= 3, this bit is reserved
\r
1176 volatile unsigned int reserved_0 :
\r
1180 volatile unsigned int dValue;
\r
1181 } PHY_STATUS;// 0x00B0
\r
1183 union _DSIH1P21A_PHY_TST_CTRL0_tag_t {
\r
1184 struct _DSIH1P21A_PHY_TST_CTRL0_map_t
\r
1186 volatile unsigned int phy_testclr :
\r
1187 1; //[0] PHY test interface clear (active high).
\r
1188 volatile unsigned int phy_testclk :
\r
1189 1; //[1] This bit is used to clock the TESTDIN bus into the D-PHY.
\r
1190 volatile unsigned int reserved_0 :
\r
1194 volatile unsigned int dValue;
\r
1196 PHY_TST_CTRL0;// 0x00B4
\r
1198 union _DSIH1P21A_PHY_TST_CTRL1_tag_t {
\r
1199 struct _DSIH1P21A_PHY_TST_CTRL1_map_t
\r
1201 volatile unsigned int phy_testdin :
\r
1202 8; //[7:0] PHY test interface input 8-bit data bus for internal register programming and test functionalities access.
\r
1203 volatile unsigned int pht_testdout :
\r
1204 8; //[15:8] PHY output 8-bit data bus for read-back and internal probing functionalities.
\r
1205 volatile unsigned int phy_testen :
\r
1208 PHY test interface operation selector:
\r
1209 1: The address write operation is set on the falling edge of the testclk signal.
\r
1210 0: The data write operation is set on the rising edge of the testclk signal.
\r
1212 volatile unsigned int reserved_0 :
\r
1216 volatile unsigned int dValue;
\r
1218 PHY_TST_CTRL1;// 0x00B8
\r
1220 union _DSIH1P21A_INT_ST0_tag_t {
\r
1221 struct _DSIH1P21A_INT_ST0_map_t
\r
1223 volatile unsigned int ack_with_err_0 :
\r
1224 1; //[0] This bit retrieves the SoT error from the Acknowledge error report.
\r
1225 volatile unsigned int ack_with_err_1 :
\r
1226 1; //[1] This bit retrieves the SoT Sync error from the Acknowledge error report.
\r
1227 volatile unsigned int ack_with_err_2 :
\r
1228 1; //[2] This bit retrieves the EoT Sync error from the Acknowledge error report.
\r
1229 volatile unsigned int ack_with_err_3 :
\r
1230 1; //[3] This bit retrieves the Escape Mode Entry Command error from the Acknowledge error report.
\r
1231 volatile unsigned int ack_with_err_4 :
\r
1232 1; //[4] This bit retrieves the LP Transmit Sync error from the Acknowledge error report.
\r
1233 volatile unsigned int ack_with_err_5 :
\r
1234 1; //[5] This bit retrieves the Peripheral Timeout error from the Acknowledge Error report.
\r
1235 volatile unsigned int ack_with_err_6 :
\r
1236 1; //[6] This bit retrieves the False Control error from the Acknowledge error report.
\r
1237 volatile unsigned int ack_with_err_7 :
\r
1238 1; //[7] This bit retrieves the reserved (specific to device) from the Acknowledge error report.
\r
1239 volatile unsigned int ack_with_err_8 :
\r
1240 1; //[8] This bit retrieves the ECC error, single-bit (detected and corrected) from the Acknowledge error report.
\r
1241 volatile unsigned int ack_with_err_9 :
\r
1242 1; //[9] This bit retrieves the ECC error, multi-bit (detected, not corrected) from the Acknowledge error report.
\r
1243 volatile unsigned int ack_with_err_10 :
\r
1244 1; //[10]This bit retrieves the checksum error (long packet only) from the Acknowledge error report.
\r
1245 volatile unsigned int ack_with_err_11 :
\r
1246 1; //[11] This bit retrieves the not recognized DSI data type from the Acknowledge error report.
\r
1247 volatile unsigned int ack_with_err_12 :
\r
1248 1; //[12] This bit retrieves the DSI VC ID Invalid from the Acknowledge error report.
\r
1249 volatile unsigned int ack_with_err_13 :
\r
1250 1; //[13] This bit retrieves the invalid transmission length from the Acknowledge error report.
\r
1251 volatile unsigned int ack_with_err_14 :
\r
1252 1; //[14] This bit retrieves the reserved (specific to device) from the Acknowledge error report
\r
1253 volatile unsigned int ack_with_err_15 :
\r
1254 1; //[15] This bit retrieves the DSI protocol violation from the Acknowledge error report.
\r
1255 volatile unsigned int dphy_errors_0 :
\r
1256 1; //[16] This bit indicates ErrEsc escape entry error from Lane 0.
\r
1257 volatile unsigned int dphy_errors_1 :
\r
1258 1; //[17] This bit indicates ErrSyncEsc low-power data transmission synchronization error from Lane 0.
\r
1259 volatile unsigned int dphy_errors_2 :
\r
1260 1; //[18] This bit indicates the ErrControl error from Lane 0.
\r
1261 volatile unsigned int dphy_errors_3 :
\r
1262 1; //[19] This bit indicates the LP0 contention error ErrContentionLP0 from Lane 0.
\r
1263 volatile unsigned int dphy_errors_4 :
\r
1264 1; //[20] This bit indicates the LP1 contention error ErrContentionLP1 from Lane 0.
\r
1265 volatile unsigned int reserved_0 :
\r
1269 volatile unsigned int dValue;
\r
1273 union _DSIH1P21A_INT_ST1_tag_t {
\r
1274 struct _DSIH1P21A_INT_ST1_map_t
\r
1276 volatile unsigned int to_hs_tx :
\r
1279 This bit indicates that the high-speed transmission timeout counter
\r
1280 reached the end and contention is detected.
\r
1282 volatile unsigned int to_lp_rx :
\r
1285 This bit indicates that the low-power reception timeout counter reached
\r
1286 the end and contention is detected.
\r
1288 volatile unsigned int ecc_single_err :
\r
1291 This bit indicates that the ECC single error is detected and corrected in a
\r
1294 volatile unsigned int ecc_multi_err :
\r
1297 This bit indicates that the ECC multiple error is detected in a received
\r
1300 volatile unsigned int crc_err :
\r
1303 This bit indicates that the CRC error is detected in the received packet
\r
1305 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or
\r
1306 DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1308 volatile unsigned int pkt_size_err :
\r
1311 This bit indicates that the packet size error is detected during the packet
\r
1314 volatile unsigned int eopt_err :
\r
1317 This bit indicates that the EoTp packet is not received at the end of the
\r
1318 incoming peripheral transmission
\r
1320 volatile unsigned int dpi_pld_wr_err :
\r
1323 This bit indicates that during a DPI pixel line storage, the payload FIFO
\r
1324 becomes full and the data stored is corrupted.
\r
1325 Dependency: DSI_DATAINTERFACE = 2 or DSI_DATAINTERFACE = 3 or
\r
1326 DSI_DATAINTERFACE = 4. Otherwise, this bit is reserved.
\r
1328 volatile unsigned int gen_cmd_wr_err :
\r
1331 This bit indicates that the system tried to write a command through the
\r
1332 Generic interface and the FIFO is full. Therefore, the command is not
\r
1334 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1336 volatile unsigned int gen_pld_wr_err :
\r
1339 This bit indicates that the system tried to write a payload data through the
\r
1340 Generic interface and the FIFO is full. Therefore, the payload is not
\r
1342 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1344 volatile unsigned int gen_pld_send_err :
\r
1347 This bit indicates that during a Generic interface packet build, the payload
\r
1348 FIFO becomes empty and corrupt data is sent.
\r
1349 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1351 volatile unsigned int gen_pld_rd_err :
\r
1354 This bit indicates that during a DCS read data, the payload FIFO becomes
\r
1355 empty and the data sent to the interface is corrupted.
\r
1356 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1358 volatile unsigned int gen_pld_recev_err :
\r
1361 This bit indicates that during a generic interface packet read back, the
\r
1362 payload FIFO becomes full and the received data is corrupted.
\r
1363 Dependency: DSI_GENERIC = 1
\r
1364 If DSI_GENERIC = 0, this bit is reserved.
\r
1366 volatile unsigned int dbi_cmd_wr_err :
\r
1369 This bit indicates that the system tried to write a command through the
\r
1370 DBI but the command FIFO is full. Therefore, the command is not written.
\r
1371 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1372 Otherwise, this bit is reserved.
\r
1374 volatile unsigned int dbi_pld_wr_err :
\r
1377 This bit indicates that the system tried to write the payload data through
\r
1378 the DBI interface and the FIFO is full. Therefore, the command is not
\r
1380 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1381 Otherwise, this bit is reserved.
\r
1383 volatile unsigned int dbi_pld_rd_err :
\r
1386 This bit indicates that during a DCS read data, the payload FIFO goes
\r
1387 empty and the data sent to the interface is corrupted.
\r
1388 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1389 Otherwise, this bit is reserved.
\r
1391 volatile unsigned int dbi_pld_recv_err :
\r
1394 This bit indicates that during a DBI read back packet, the payload FIFO
\r
1395 becomes full and the received data is corrupted.
\r
1396 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1397 Otherwise, this bit is reserved.
\r
1400 volatile unsigned int dbi_ilegal_comm_err :
\r
1403 This bit indicates that an attempt to write an illegal command on the DBI
\r
1404 interface is made and the core is blocked by transmission.
\r
1405 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1406 Otherwise, this bit is reserved.
\r
1408 volatile unsigned int reserved_0 :
\r
1412 volatile unsigned int dValue;
\r
1417 union _DSIH1P21A_INT_MSK0_tag_t {
\r
1418 struct _DSIH1P21A_INT_MSK0_map_t
\r
1420 volatile unsigned int ack_with_err_0 :
\r
1421 1; //[0] This bit retrieves the SoT error from the Acknowledge error report.
\r
1422 volatile unsigned int ack_with_err_1 :
\r
1423 1; //[1] This bit retrieves the SoT Sync error from the Acknowledge error report.
\r
1424 volatile unsigned int ack_with_err_2 :
\r
1425 1; //[2] This bit retrieves the EoT Sync error from the Acknowledge error report.
\r
1426 volatile unsigned int ack_with_err_3 :
\r
1427 1; //[3] This bit retrieves the Escape Mode Entry Command error from the Acknowledge error report.
\r
1428 volatile unsigned int ack_with_err_4 :
\r
1429 1; //[4] This bit retrieves the LP Transmit Sync error from the Acknowledge error report.
\r
1430 volatile unsigned int ack_with_err_5 :
\r
1431 1; //[5] This bit retrieves the Peripheral Timeout error from the Acknowledge Error report.
\r
1432 volatile unsigned int ack_with_err_6 :
\r
1433 1; //[6] This bit retrieves the False Control error from the Acknowledge error report.
\r
1434 volatile unsigned int ack_with_err_7 :
\r
1435 1; //[7] This bit retrieves the reserved (specific to device) from the Acknowledge error report.
\r
1436 volatile unsigned int ack_with_err_8 :
\r
1437 1; //[8] This bit retrieves the ECC error, single-bit (detected and corrected) from the Acknowledge error report.
\r
1438 volatile unsigned int ack_with_err_9 :
\r
1439 1; //[9] This bit retrieves the ECC error, multi-bit (detected, not corrected) from the Acknowledge error report.
\r
1440 volatile unsigned int ack_with_err_10 :
\r
1441 1; //[10]This bit retrieves the checksum error (long packet only) from the Acknowledge error report.
\r
1442 volatile unsigned int ack_with_err_11 :
\r
1443 1; //[11] This bit retrieves the not recognized DSI data type from the Acknowledge error report.
\r
1444 volatile unsigned int ack_with_err_12 :
\r
1445 1; //[12] This bit retrieves the DSI VC ID Invalid from the Acknowledge error report.
\r
1446 volatile unsigned int ack_with_err_13 :
\r
1447 1; //[13] This bit retrieves the invalid transmission length from the Acknowledge error report.
\r
1448 volatile unsigned int ack_with_err_14 :
\r
1449 1; //[14] This bit retrieves the reserved (specific to device) from the Acknowledge error report
\r
1450 volatile unsigned int ack_with_err_15 :
\r
1451 1; //[15] This bit retrieves the DSI protocol violation from the Acknowledge error report.
\r
1452 volatile unsigned int dphy_errors_0 :
\r
1453 1; //[16] This bit indicates ErrEsc escape entry error from Lane 0.
\r
1454 volatile unsigned int dphy_errors_1 :
\r
1455 1; //[17] This bit indicates ErrSyncEsc low-power data transmission synchronization error from Lane 0.
\r
1456 volatile unsigned int dphy_errors_2 :
\r
1457 1; //[18] This bit indicates the ErrControl error from Lane 0.
\r
1458 volatile unsigned int dphy_errors_3 :
\r
1459 1; //[19] This bit indicates the LP0 contention error ErrContentionLP0 from Lane 0.
\r
1460 volatile unsigned int dphy_errors_4 :
\r
1461 1; //[20] This bit indicates the LP1 contention error ErrContentionLP1 from Lane 0.
\r
1462 volatile unsigned int reserved_0 :
\r
1466 volatile unsigned int dValue;
\r
1468 INT_MSK0;// 0x00C4
\r
1471 union _DSIH1P21A_INT_MSK1_tag_t {
\r
1472 struct _DSIH1P21A_INT_MSK1_map_t
\r
1474 volatile unsigned int to_hs_tx :
\r
1477 This bit indicates that the high-speed transmission timeout counter
\r
1478 reached the end and contention is detected.
\r
1480 volatile unsigned int to_lp_rx :
\r
1483 This bit indicates that the low-power reception timeout counter reached
\r
1484 the end and contention is detected.
\r
1486 volatile unsigned int ecc_single_err :
\r
1489 This bit indicates that the ECC single error is detected and corrected in a
\r
1492 volatile unsigned int ecc_multi_err :
\r
1495 This bit indicates that the ECC multiple error is detected in a received
\r
1498 volatile unsigned int crc_err :
\r
1501 This bit indicates that the CRC error is detected in the received packet
\r
1503 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3 or
\r
1504 DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1506 volatile unsigned int pkt_size_err :
\r
1509 This bit indicates that the packet size error is detected during the packet
\r
1512 volatile unsigned int eopt_err :
\r
1515 This bit indicates that the EoTp packet is not received at the end of the
\r
1516 incoming peripheral transmission
\r
1518 volatile unsigned int dpi_pld_wr_err :
\r
1521 This bit indicates that during a DPI pixel line storage, the payload FIFO
\r
1522 becomes full and the data stored is corrupted.
\r
1523 Dependency: DSI_DATAINTERFACE = 2 or DSI_DATAINTERFACE = 3 or
\r
1524 DSI_DATAINTERFACE = 4. Otherwise, this bit is reserved.
\r
1526 volatile unsigned int gen_cmd_wr_err :
\r
1529 This bit indicates that the system tried to write a command through the
\r
1530 Generic interface and the FIFO is full. Therefore, the command is not
\r
1532 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1534 volatile unsigned int gen_pld_wr_err :
\r
1537 This bit indicates that the system tried to write a payload data through the
\r
1538 Generic interface and the FIFO is full. Therefore, the payload is not
\r
1540 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1542 volatile unsigned int gen_pld_send_err :
\r
1545 This bit indicates that during a Generic interface packet build, the payload
\r
1546 FIFO becomes empty and corrupt data is sent.
\r
1547 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved
\r
1549 volatile unsigned int gen_pld_rd_err :
\r
1552 This bit indicates that during a DCS read data, the payload FIFO becomes
\r
1553 empty and the data sent to the interface is corrupted.
\r
1554 Dependency: DSI_GENERIC = 1. Otherwise, this bit is reserved.
\r
1556 volatile unsigned int gen_pld_recev_err :
\r
1559 This bit indicates that during a generic interface packet read back, the
\r
1560 payload FIFO becomes full and the received data is corrupted.
\r
1561 Dependency: DSI_GENERIC = 1
\r
1562 If DSI_GENERIC = 0, this bit is reserved.
\r
1564 volatile unsigned int dbi_cmd_wr_err :
\r
1567 This bit indicates that the system tried to write a command through the
\r
1568 DBI but the command FIFO is full. Therefore, the command is not written.
\r
1569 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1570 Otherwise, this bit is reserved.
\r
1572 volatile unsigned int dbi_pld_wr_err :
\r
1575 This bit indicates that the system tried to write the payload data through
\r
1576 the DBI interface and the FIFO is full. Therefore, the command is not
\r
1578 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1579 Otherwise, this bit is reserved.
\r
1581 volatile unsigned int dbi_pld_rd_err :
\r
1584 This bit indicates that during a DCS read data, the payload FIFO goes
\r
1585 empty and the data sent to the interface is corrupted.
\r
1586 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1587 Otherwise, this bit is reserved.
\r
1589 volatile unsigned int dbi_pld_recv_err :
\r
1592 This bit indicates that during a DBI read back packet, the payload FIFO
\r
1593 becomes full and the received data is corrupted.
\r
1594 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1595 Otherwise, this bit is reserved.
\r
1598 volatile unsigned int dbi_ilegal_comm_err :
\r
1601 This bit indicates that an attempt to write an illegal command on the DBI
\r
1602 interface is made and the core is blocked by transmission.
\r
1603 Dependency: DSI_DATAINTERFACE = 1 or DSI_DATAINTERFACE = 3.
\r
1604 Otherwise, this bit is reserved.
\r
1606 volatile unsigned int reserved_0 :
\r
1610 volatile unsigned int dValue;
\r
1612 INT_MSK1;// 0x00C8
\r
1614 uint32_t mipi_dsih_hal_get_version(dsih_ctrl_t * instance);
\r
1616 void mipi_dsih_hal_power(dsih_ctrl_t * instance, int on);
\r
1618 int mipi_dsih_hal_get_power(dsih_ctrl_t * instance);
\r
1620 void mipi_dsih_hal_tx_escape_division(dsih_ctrl_t * instance, uint8_t tx_escape_division);
\r
1622 void mipi_dsih_hal_dpi_video_vc(dsih_ctrl_t * instance, uint8_t vc);
\r
1624 uint8_t mipi_dsih_hal_dpi_get_video_vc(dsih_ctrl_t * instance);
\r
1626 dsih_error_t mipi_dsih_hal_dpi_color_coding(dsih_ctrl_t * instance, dsih_color_coding_t color_coding);
\r
1627 dsih_color_coding_t mipi_dsih_hal_dpi_get_color_coding(dsih_ctrl_t * instance);
\r
1628 uint8_t mipi_dsih_hal_dpi_get_color_depth(dsih_ctrl_t * instance);
\r
1629 uint8_t mipi_dsih_hal_dpi_get_color_config(dsih_ctrl_t * instance);
\r
1630 void mipi_dsih_hal_dpi_18_loosely_packet_en(dsih_ctrl_t * instance, int enable);
\r
1631 void mipi_dsih_hal_dpi_color_mode_pol(dsih_ctrl_t * instance, int active_low);
\r
1632 void mipi_dsih_hal_dpi_shut_down_pol(dsih_ctrl_t * instance, int active_low);
\r
1633 void mipi_dsih_hal_dpi_hsync_pol(dsih_ctrl_t * instance, int active_low);
\r
1634 void mipi_dsih_hal_dpi_vsync_pol(dsih_ctrl_t * instance, int active_low);
\r
1635 void mipi_dsih_hal_dpi_dataen_pol(dsih_ctrl_t * instance, int active_low);
\r
1636 void mipi_dsih_hal_dpi_frame_ack_en(dsih_ctrl_t * instance, int enable);
\r
1637 void mipi_dsih_hal_dpi_null_packet_en(dsih_ctrl_t * instance, int enable);
\r
1638 void mipi_dsih_hal_dpi_multi_packet_en(dsih_ctrl_t * instance, int enable);
\r
1639 void mipi_dsih_hal_dpi_lp_during_hfp(dsih_ctrl_t * instance, int enable);
\r
1640 void mipi_dsih_hal_dpi_lp_during_hbp(dsih_ctrl_t * instance, int enable);
\r
1641 void mipi_dsih_hal_dpi_lp_during_vactive(dsih_ctrl_t * instance, int enable);
\r
1642 void mipi_dsih_hal_dpi_lp_during_vfp(dsih_ctrl_t * instance, int enable);
\r
1643 void mipi_dsih_hal_dpi_lp_during_vbp(dsih_ctrl_t * instance, int enable);
\r
1644 void mipi_dsih_hal_dpi_lp_during_vsync(dsih_ctrl_t * instance, int enable);
\r
1646 dsih_error_t mipi_dsih_hal_dpi_video_mode_type(dsih_ctrl_t * instance, dsih_video_mode_t type);
\r
1647 void mipi_dsih_hal_dpi_video_mode_en(dsih_ctrl_t * instance, int enable);
\r
1648 int mipi_dsih_hal_dpi_is_video_mode(dsih_ctrl_t * instance);
\r
1649 dsih_error_t mipi_dsih_hal_dpi_null_packet_size(dsih_ctrl_t * instance, uint16_t size);
\r
1650 dsih_error_t mipi_dsih_hal_dpi_chunks_no(dsih_ctrl_t * instance, uint16_t no);
\r
1651 dsih_error_t mipi_dsih_hal_dpi_video_packet_size(dsih_ctrl_t * instance, uint16_t size);
\r
1653 void mipi_dsih_hal_tear_effect_ack_en(dsih_ctrl_t * instance, int enable);
\r
1655 void mipi_dsih_hal_cmd_ack_en(dsih_ctrl_t * instance, int enable);
\r
1656 dsih_error_t mipi_dsih_hal_dcs_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1657 dsih_error_t mipi_dsih_hal_dcs_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1658 /*Jessica add to support max rd packet size command*/
\r
1659 dsih_error_t mipi_dsih_hal_max_rd_packet_size_type(dsih_ctrl_t * instance, int lp);
\r
1660 dsih_error_t mipi_dsih_hal_gen_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1661 dsih_error_t mipi_dsih_hal_gen_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp);
\r
1662 void mipi_dsih_hal_max_rd_size_type(dsih_ctrl_t * instance, int lp);
\r
1663 void mipi_dsih_hal_gen_cmd_mode_en(dsih_ctrl_t * instance, int enable);
\r
1664 int mipi_dsih_hal_gen_is_cmd_mode(dsih_ctrl_t * instance);
\r
1666 void mipi_dsih_hal_dpi_hline(dsih_ctrl_t * instance, uint16_t time);
\r
1667 void mipi_dsih_hal_dpi_hbp(dsih_ctrl_t * instance, uint16_t time);
\r
1668 void mipi_dsih_hal_dpi_hsa(dsih_ctrl_t * instance, uint16_t time);
\r
1669 void mipi_dsih_hal_dpi_vactive(dsih_ctrl_t * instance, uint16_t lines);
\r
1670 void mipi_dsih_hal_dpi_vfp(dsih_ctrl_t * instance, uint16_t lines);
\r
1671 void mipi_dsih_hal_dpi_vbp(dsih_ctrl_t * instance, uint16_t lines);
\r
1672 void mipi_dsih_hal_dpi_vsync(dsih_ctrl_t * instance, uint16_t lines);
\r
1674 void mipi_dsih_hal_edpi_max_allowed_size(dsih_ctrl_t * instance, uint16_t size);
\r
1676 dsih_error_t mipi_dsih_hal_gen_packet_header(dsih_ctrl_t * instance, uint8_t vc, uint8_t packet_type, uint8_t ms_byte, uint8_t ls_byte);
\r
1677 dsih_error_t mipi_dsih_hal_gen_packet_payload(dsih_ctrl_t * instance, uint32_t payload);
\r
1678 dsih_error_t mipi_dsih_hal_gen_read_payload(dsih_ctrl_t * instance, uint32_t* payload);
\r
1680 void mipi_dsih_hal_timeout_clock_division(dsih_ctrl_t * instance, uint8_t byte_clk_division_factor);
\r
1681 void mipi_dsih_hal_lp_rx_timeout(dsih_ctrl_t * instance, uint16_t count);
\r
1682 void mipi_dsih_hal_hs_tx_timeout(dsih_ctrl_t * instance, uint16_t count);
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1684 uint32_t mipi_dsih_hal_int_status_0(dsih_ctrl_t * instance, uint32_t mask);
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1685 uint32_t mipi_dsih_hal_int_status_1(dsih_ctrl_t * instance, uint32_t mask);
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1686 void mipi_dsih_hal_int_mask_0(dsih_ctrl_t * instance, uint32_t mask);
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1687 void mipi_dsih_hal_int_mask_1(dsih_ctrl_t * instance, uint32_t mask);
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1688 uint32_t mipi_dsih_hal_int_get_mask_0(dsih_ctrl_t * instance, uint32_t mask);
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1689 uint32_t mipi_dsih_hal_int_get_mask_1(dsih_ctrl_t * instance, uint32_t mask);
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1690 /* DBI command interface */
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1691 void mipi_dsih_hal_dbi_out_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);
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1692 void mipi_dsih_hal_dbi_in_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);
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1693 void mipi_dsih_hal_dbi_lut_size(dsih_ctrl_t * instance, uint8_t size);
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1694 void mipi_dsih_hal_dbi_partitioning_en(dsih_ctrl_t * instance, int enable);
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1695 void mipi_dsih_hal_dbi_dcs_vc(dsih_ctrl_t * instance, uint8_t vc);
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1697 void mipi_dsih_hal_dbi_cmd_size(dsih_ctrl_t * instance, uint16_t size);
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1698 void mipi_dsih_hal_dbi_max_cmd_size(dsih_ctrl_t * instance, uint16_t size);
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1699 int mipi_dsih_hal_dbi_rd_cmd_busy(dsih_ctrl_t * instance);
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1700 int mipi_dsih_hal_dbi_read_fifo_full(dsih_ctrl_t * instance);
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1701 int mipi_dsih_hal_dbi_read_fifo_empty(dsih_ctrl_t * instance);
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1702 int mipi_dsih_hal_dbi_write_fifo_full(dsih_ctrl_t * instance);
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1703 int mipi_dsih_hal_dbi_write_fifo_empty(dsih_ctrl_t * instance);
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1704 int mipi_dsih_hal_dbi_cmd_fifo_full(dsih_ctrl_t * instance);
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1705 int mipi_dsih_hal_dbi_cmd_fifo_empty(dsih_ctrl_t * instance);
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1706 /* Generic command interface */
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1707 void mipi_dsih_hal_gen_rd_vc(dsih_ctrl_t * instance, uint8_t vc);
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1708 void mipi_dsih_hal_gen_eotp_rx_en(dsih_ctrl_t * instance, int enable);
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1709 void mipi_dsih_hal_gen_eotp_tx_en(dsih_ctrl_t * instance, int enable);
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1710 void mipi_dsih_hal_bta_en(dsih_ctrl_t * instance, int enable);
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1711 void mipi_dsih_hal_gen_ecc_rx_en(dsih_ctrl_t * instance, int enable);
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1712 void mipi_dsih_hal_gen_crc_rx_en(dsih_ctrl_t * instance, int enable);
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1713 int mipi_dsih_hal_gen_rd_cmd_busy(dsih_ctrl_t * instance);
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1714 int mipi_dsih_hal_gen_read_fifo_full(dsih_ctrl_t * instance);
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1715 int mipi_dsih_hal_gen_read_fifo_empty(dsih_ctrl_t * instance);
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1716 int mipi_dsih_hal_gen_write_fifo_full(dsih_ctrl_t * instance);
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1717 int mipi_dsih_hal_gen_write_fifo_empty(dsih_ctrl_t * instance);
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1718 int mipi_dsih_hal_gen_cmd_fifo_full(dsih_ctrl_t * instance);
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1719 int mipi_dsih_hal_gen_cmd_fifo_empty(dsih_ctrl_t * instance);
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1722 dsih_error_t mipi_dsih_phy_hs2lp_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
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1723 dsih_error_t mipi_dsih_phy_lp2hs_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
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1724 dsih_error_t mipi_dsih_phy_clk_lp2hs_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
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1725 dsih_error_t mipi_dsih_phy_clk_hs2lp_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles);
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1726 dsih_error_t mipi_dsih_phy_bta_time(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1727 void mipi_dsih_non_continuous_clock(dsih_ctrl_t * instance, int enable);
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1728 int mipi_dsih_non_continuous_clock_status(dsih_ctrl_t * instance);
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1729 /* PRESP Time outs */
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1730 void mipi_dsih_hal_presp_timeout_low_power_write(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1731 void mipi_dsih_hal_presp_timeout_low_power_read(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1732 void mipi_dsih_hal_presp_timeout_high_speed_write(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1733 void mipi_dsih_hal_presp_timeout_high_speed_read(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1734 void mipi_dsih_hal_presp_timeout_bta(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles);
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1735 /* bsp abstraction */
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1736 void mipi_dsih_write_word(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data);
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1737 void mipi_dsih_write_part(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data, uint8_t shift, uint8_t width);
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1738 uint32_t mipi_dsih_read_word(dsih_ctrl_t * instance, uint32_t reg_address);
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1739 uint32_t mipi_dsih_read_part(dsih_ctrl_t * instance, uint32_t reg_address, uint8_t shift, uint8_t width);
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1741 #endif /* MIPI_DSI_API_H_ */
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projects / kernel / u-boot-tm1.git / blob