drivers/video/sprdfb/dsi_1_21a/mipi_dsih_dphy.h

   1 /*\r
   2  * @file mipi_dsih_dphy.h\r
   3  *\r
   4  *  Synopsys Inc.\r
   5  *  SG DWC PT02\r
   6  */\r
   7 \r
   8 #ifndef MIPI_DSIH_DPHY_H_\r
   9 #define MIPI_DSIH_DPHY_H_\r
  10 \r
  11 #include "mipi_dsih_local.h"\r
  12 \r
  13 #define R_DPHY_LPCLK_CTRL       (0x94)\r
  14 #define R_DPHY_RSTZ             (0xA0)\r
  15 #define R_DPHY_IF_CFG           (0xA4)\r
  16 #define R_DPHY_ULPS_CTRL        (0xA8)\r
  17 #define R_DPHY_TX_TRIGGERS  (0xAC)\r
  18 #define R_DPHY_STATUS           (0xB0)\r
  19 #define R_DPHY_TST_CRTL0        (0xB4)\r
  20 #define R_DPHY_TST_CRTL1        (0xB8)\r
  21 \r
  22 /* obligatory functions - code can be changed for different phys*/\r
  23 dsih_error_t mipi_dsih_dphy_open(dphy_t * phy);\r
  24 dsih_error_t mipi_dsih_dphy_configure(dphy_t * phy, uint8_t no_of_lanes, uint32_t output_freq);\r
  25 dsih_error_t mipi_dsih_dphy_close(dphy_t * phy);\r
  26 \r
  27 void mipi_dsih_dphy_clock_en(dphy_t * instance, int en);\r
  28 void mipi_dsih_dphy_reset(dphy_t * instance, int reset);\r
  29 void mipi_dsih_dphy_shutdown(dphy_t * instance, int powerup);\r
  30 int mipi_dsih_dphy_get_force_pll(dphy_t * instance);\r
  31 void mipi_dsih_dphy_force_pll(dphy_t * instance, int force);\r
  32 int mipi_dsih_dphy_wakeup_pll(dphy_t * instance);\r
  33 \r
  34 void mipi_dsih_dphy_stop_wait_time(dphy_t * instance, uint8_t no_of_byte_cycles);\r
  35 void mipi_dsih_dphy_no_of_lanes(dphy_t * instance, uint8_t no_of_lanes);\r
  36 uint8_t mipi_dsih_dphy_get_no_of_lanes(dphy_t * instance);\r
  37 void mipi_dsih_dphy_enable_nc_clk(dphy_t * instance, int enable);\r
  38 void mipi_dsih_dphy_enable_hs_clk(dphy_t * instance, int enable);\r
  39 dsih_error_t mipi_dsih_dphy_escape_mode_trigger(dphy_t * instance, uint8_t trigger_request);\r
  40  #ifdef GEN_2\r
  41 dsih_error_t mipi_dsih_dphy_ulps_data_lanes(dphy_t * instance, int enable);\r
  42 dsih_error_t mipi_dsih_dphy_ulps_clk_lane(dphy_t * instance, int enable);\r
  43 #else\r
  44 void mipi_dsih_dphy_ulps_data_lanes(dphy_t * instance, int enable);\r
  45 void mipi_dsih_dphy_ulps_clk_lane(dphy_t * instance, int enable);\r
  46 #endif\r
  47 uint32_t mipi_dsih_dphy_status(dphy_t * instance, uint16_t mask);\r
  48 /* end of obligatory functions*/\r
  49 void mipi_dsih_dphy_test_clock(dphy_t * instance, int value);\r
  50 void mipi_dsih_dphy_test_clear(dphy_t * instance, int value);\r
  51 void mipi_dsih_dphy_test_en(dphy_t * instance, uint8_t on_falling_edge);\r
  52 uint8_t mipi_dsih_dphy_test_data_out(dphy_t * instance);\r
  53 void mipi_dsih_dphy_test_data_in(dphy_t * instance, uint8_t test_data);\r
  54 \r
  55 void mipi_dsih_dphy_write(dphy_t * instance, uint8_t address, uint8_t * data, uint8_t data_length);\r
  56 \r
  57 void mipi_dsih_dphy_write_word(dphy_t * instance, uint32_t reg_address, uint32_t data);\r
  58 void mipi_dsih_dphy_write_part(dphy_t * instance, uint32_t reg_address, uint32_t data, uint8_t shift, uint8_t width);\r
  59 uint32_t mipi_dsih_dphy_read_word(dphy_t * instance, uint32_t reg_address);\r
  60 uint32_t mipi_dsih_dphy_read_part(dphy_t * instance, uint32_t reg_address, uint8_t shift, uint8_t width);\r
  61 #endif /* MIPI_DSIH_DPHY_H_ */\r