drivers/video/sprdfb/dsi_1_10a/mipi_dsih_hal.c

   1                                                                                                                                        \r
   2 #include "mipi_dsih_hal.h"                                                                                                             \r
   3                                                                                                                                        \r
   4 void mipi_dsih_write_word(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data)                                                 \r
   5 {                                                                                                                                      \r
   6                                                                                                                                        \r
   7     instance->core_write_function(instance->address, reg_address, data);                                                               \r
   8 }                                                                                                                                      \r
   9 void mipi_dsih_write_part(dsih_ctrl_t * instance, uint32_t reg_address, uint32_t data, uint8_t shift, uint8_t width)                   \r
  10 {                                                                                                                                      \r
  11     uint32_t mask = (1 << width) - 1;                                                                                                  \r
  12     uint32_t temp = mipi_dsih_read_word(instance, reg_address);                                                                        \r
  13                                                                                                                                        \r
  14     temp &= ~(mask << shift);                                                                                                          \r
  15     temp |= (data & mask) << shift;                                                                                                    \r
  16     mipi_dsih_write_word(instance, reg_address, temp);                                                                                 \r
  17 }                                                                                                                                      \r
  18 uint32_t mipi_dsih_read_word(dsih_ctrl_t * instance, uint32_t reg_address)                                                             \r
  19 {                                                                                                                                      \r
  20     return instance->core_read_function(instance->address, reg_address);                                                               \r
  21 }                                                                                                                                      \r
  22 uint32_t mipi_dsih_read_part(dsih_ctrl_t * instance, uint32_t reg_address, uint8_t shift, uint8_t width)                               \r
  23 {                                                                                                                                      \r
  24     return (mipi_dsih_read_word(instance, reg_address) >> shift) & ((1 << width) - 1);                                                 \r
  25 }                                                                                                                                      \r
  26 uint32_t mipi_dsih_hal_get_version(dsih_ctrl_t * instance)                                                                             \r
  27 {                                                                                                                                      \r
  28     return mipi_dsih_read_word(instance, R_DSI_HOST_VERSION);                                                                          \r
  29 }                                                                                                                                      \r
  30 void mipi_dsih_hal_power(dsih_ctrl_t * instance, int on)                                                                               \r
  31 {                                                                                                                                      \r
  32     mipi_dsih_write_part(instance, R_DSI_HOST_PWR_UP, on, 0, 1);                                                                       \r
  33 }                                                                                                                                      \r
  34 int mipi_dsih_hal_get_power(dsih_ctrl_t * instance)                                                                                    \r
  35 {                                                                                                                                      \r
  36     return (int)(mipi_dsih_read_word(instance, R_DSI_HOST_PWR_UP));                                                                    \r
  37 }                                                                                                                                      \r
  38 void mipi_dsih_hal_tx_escape_division(dsih_ctrl_t * instance, uint8_t tx_escape_division)                                              \r
  39 {                                                                                                                                      \r
  40     mipi_dsih_write_part(instance, R_DSI_HOST_CLK_MGR, tx_escape_division, 0, 8);                                                      \r
  41 }                                                                                                                                      \r
  42 void mipi_dsih_hal_dpi_video_vc(dsih_ctrl_t * instance, uint8_t vc)                                                                    \r
  43 {                                                                                                                                      \r
  44     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, (uint32_t)(vc), 0, 2);                                                          \r
  45 }                                                                                                                                      \r
  46 uint8_t mipi_dsih_hal_dpi_get_video_vc(dsih_ctrl_t * instance)                                                                         \r
  47 {                                                                                                                                      \r
  48     return mipi_dsih_read_part(instance, R_DSI_HOST_DPI_CFG, 0, 2);                                                                    \r
  49 }                                                                                                                                      \r
  50 dsih_error_t mipi_dsih_hal_dpi_color_coding(dsih_ctrl_t * instance, dsih_color_coding_t color_coding)                                  \r
  51 {                                                                                                                                      \r
  52     dsih_error_t err = OK;                                                                                                             \r
  53     if (color_coding > 7)                                                                                                              \r
  54     {                                                                                                                                  \r
  55         if (instance->log_error != 0)                                                                                                  \r
  56         {                                                                                                                              \r
  57             instance->log_error("invalid colour configuration");                                                                       \r
  58         }                                                                                                                              \r
  59         err = ERR_DSI_COLOR_CODING;                                                                                                    \r
  60     }                                                                                                                                  \r
  61     else                                                                                                                               \r
  62     {                                                                                                                                  \r
  63         mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, color_coding, 2, 3);                                                        \r
  64     }                                                                                                                                  \r
  65     return err;                                                                                                                        \r
  66 }                                                                                                                                      \r
  67 dsih_color_coding_t mipi_dsih_hal_dpi_get_color_coding(dsih_ctrl_t * instance)                                                         \r
  68 {                                                                                                                                      \r
  69     return (dsih_color_coding_t)(mipi_dsih_read_part(instance, R_DSI_HOST_DPI_CFG, 2, 3));                                             \r
  70 }                                                                                                                                      \r
  71 uint8_t mipi_dsih_hal_dpi_get_color_depth(dsih_ctrl_t * instance)                                                                      \r
  72 {                                                                                                                                      \r
  73     uint8_t color_depth = 0;                                                                                                           \r
  74     switch (mipi_dsih_read_part(instance, R_DSI_HOST_DPI_CFG, 2, 3))                                                                   \r
  75     {                                                                                                                                  \r
  76         case 0:                                                                                                                        \r
  77         case 1:                                                                                                                        \r
  78         case 2:                                                                                                                        \r
  79             color_depth = 16;                                                                                                          \r
  80             break;                                                                                                                     \r
  81         case 3:                                                                                                                        \r
  82         case 4:                                                                                                                        \r
  83             color_depth = 18;                                                                                                          \r
  84             break;                                                                                                                     \r
  85         default:                                                                                                                       \r
  86             color_depth = 24;                                                                                                          \r
  87             break;                                                                                                                     \r
  88     }                                                                                                                                  \r
  89     return color_depth;                                                                                                                \r
  90 }                                                                                                                                      \r
  91 uint8_t mipi_dsih_hal_dpi_get_color_config(dsih_ctrl_t * instance)                                                                     \r
  92 {                                                                                                                                      \r
  93     uint8_t color_config = 0;                                                                                                          \r
  94     switch (mipi_dsih_read_part(instance, R_DSI_HOST_DPI_CFG, 2, 3))                                                                   \r
  95     {                                                                                                                                  \r
  96         case 0:                                                                                                                        \r
  97             color_config = 1;    \r
  98             break;\r
  99         case 1:                                                                                                                        \r
 100             color_config = 2;                                                                                                          \r
 101             break;                                                                                                                     \r
 102         case 2:                                                                                                                        \r
 103             color_config = 3;                                                                                                          \r
 104             break;                                                                                                                     \r
 105         case 3:                                                                                                                        \r
 106             color_config = 1;                                                                                                          \r
 107             break;                                                                                                                     \r
 108         case 4:                                                                                                                        \r
 109             color_config = 2;                                                                                                          \r
 110             break;                                                                                                                     \r
 111         default:                                                                                                                       \r
 112             color_config = 0;                                                                                                          \r
 113             break;                                                                                                                     \r
 114     }                                                                                                                                  \r
 115     return color_config;                                                                                                               \r
 116 }                                                                                                                                      \r
 117 void mipi_dsih_hal_dpi_18_loosely_packet_en(dsih_ctrl_t * instance, int enable)                                                        \r
 118 {                                                                                                                                      \r
 119     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, enable, 10, 1);                                                                 \r
 120 }                                                                                                                                      \r
 121 void mipi_dsih_hal_dpi_color_mode_pol(dsih_ctrl_t * instance, int active_low)                                                          \r
 122 {                                                                                                                                      \r
 123     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, active_low, 9, 1);                                                              \r
 124 }                                                                                                                                      \r
 125 void mipi_dsih_hal_dpi_shut_down_pol(dsih_ctrl_t * instance, int active_low)                                                           \r
 126 {                                                                                                                                      \r
 127     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, active_low, 8, 1);                                                              \r
 128 }                                                                                                                                      \r
 129 void mipi_dsih_hal_dpi_hsync_pol(dsih_ctrl_t * instance, int active_low)                                                               \r
 130 {                                                                                                                                      \r
 131     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, active_low, 7, 1);                                                              \r
 132 }                                                                                                                                      \r
 133 void mipi_dsih_hal_dpi_vsync_pol(dsih_ctrl_t * instance, int active_low)                                                               \r
 134 {                                                                                                                                      \r
 135     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, active_low, 6, 1);                                                              \r
 136 }                                                                                                                                      \r
 137 void mipi_dsih_hal_dpi_dataen_pol(dsih_ctrl_t * instance, int active_low)                                                              \r
 138 {                                                                                                                                      \r
 139     mipi_dsih_write_part(instance, R_DSI_HOST_DPI_CFG, active_low, 5, 1);                                                              \r
 140 }                                                                                                                                      \r
 141 void mipi_dsih_hal_dpi_frame_ack_en(dsih_ctrl_t * instance, int enable)                                                                \r
 142 {                                                                                                                                      \r
 143     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 11, 1);                                                            \r
 144 }                                                                                                                                      \r
 145 void mipi_dsih_hal_dpi_null_packet_en(dsih_ctrl_t * instance, int enable)                                                              \r
 146 {                                                                                                                                      \r
 147     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 10, 1);                                                            \r
 148 }                                                                                                                                      \r
 149 void mipi_dsih_hal_dpi_multi_packet_en(dsih_ctrl_t * instance, int enable)                                                             \r
 150 {                                                                                                                                      \r
 151     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 9, 1);                                                             \r
 152 }                                                                                                                                      \r
 153 void mipi_dsih_hal_dpi_lp_during_hfp(dsih_ctrl_t * instance, int enable)                                                               \r
 154 {                                                                                                                                      \r
 155     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 8, 1);                                                             \r
 156 }                                                                                                                                      \r
 157 void mipi_dsih_hal_dpi_lp_during_hbp(dsih_ctrl_t * instance, int enable)                                                               \r
 158 {                                                                                                                                      \r
 159     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 7, 1);                                                             \r
 160 }                                                                                                                                      \r
 161 void mipi_dsih_hal_dpi_lp_during_vactive(dsih_ctrl_t * instance, int enable)                                                           \r
 162 {                                                                                                                                      \r
 163     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 6, 1);                                                             \r
 164 }                                                                                                                                      \r
 165 void mipi_dsih_hal_dpi_lp_during_vfp(dsih_ctrl_t * instance, int enable)                                                               \r
 166 {                                                                                                                                      \r
 167     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 5, 1);                                                             \r
 168 }                                                                                                                                      \r
 169 void mipi_dsih_hal_dpi_lp_during_vbp(dsih_ctrl_t * instance, int enable)                                                               \r
 170 {                                                                                                                                      \r
 171     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 4, 1);                                                             \r
 172 }                                                                                                                                      \r
 173 void mipi_dsih_hal_dpi_lp_during_vsync(dsih_ctrl_t * instance, int enable)                                                             \r
 174 {                                                                                                                                      \r
 175     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 3, 1);                                                             \r
 176 }                                                                                                                                      \r
 177 dsih_error_t mipi_dsih_hal_dpi_video_mode_type(dsih_ctrl_t * instance, dsih_video_mode_t type)                                         \r
 178 {                                                                                                                                      \r
 179     if (type < 3)                                                                                                                      \r
 180     {                                                                                                                                  \r
 181         mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, type, 1, 2);                                                           \r
 182         return OK;                                                                                                                     \r
 183     }                                                                                                                                  \r
 184     else                                                                                                                               \r
 185     {                                                                                                                                  \r
 186         if (instance->log_error != 0)                                                                                                  \r
 187         {                                                                                                                              \r
 188             instance->log_error("undefined type");                                                                                     \r
 189         }                                                                                                                              \r
 190         return ERR_DSI_OUT_OF_BOUND;                                                                                                   \r
 191     }                                                                                                                                  \r
 192 }                                                                                                                                      \r
 193 void mipi_dsih_hal_dpi_video_mode_en(dsih_ctrl_t * instance, int enable)                                                               \r
 194 {                                                                                                                                      \r
 195     mipi_dsih_write_part(instance, R_DSI_HOST_VID_MODE_CFG, enable, 0, 1);                                                             \r
 196 }                                                                                                                                      \r
 197 int mipi_dsih_hal_dpi_is_video_mode(dsih_ctrl_t * instance)                                                                            \r
 198 {                                                                                                                                      \r
 199     return mipi_dsih_read_part(instance, R_DSI_HOST_VID_MODE_CFG, 0, 1);                                                               \r
 200 }                                                                                                                                      \r
 201 dsih_error_t mipi_dsih_hal_dpi_null_packet_size(dsih_ctrl_t * instance, uint16_t size)                                                 \r
 202 {                                                                                                                                      \r
 203     if (size < 0x3ff) /* 10-bit field */                                                                                               \r
 204     {                                                                                                                                  \r
 205         mipi_dsih_write_part(instance, R_DSI_HOST_VID_PKT_CFG, size, 21, 10);                                                          \r
 206         return OK;                                                                                                                     \r
 207     }                                                                                                                                  \r
 208     else                                                                                                                               \r
 209     {                                                                                                                                  \r
 210         return ERR_DSI_OUT_OF_BOUND;                                                                                                   \r
 211     }                                                                                                                                  \r
 212 }                                                                                                                                      \r
 213 dsih_error_t mipi_dsih_hal_dpi_chunks_no(dsih_ctrl_t * instance, uint16_t no)                                                          \r
 214 {                                                                                                                                      \r
 215     if (no < 0x3ff)                                                                                                                    \r
 216     {                                                                                                                                  \r
 217         mipi_dsih_write_part(instance, R_DSI_HOST_VID_PKT_CFG, no, 11, 10);                                                            \r
 218         return OK;                                                                                                                     \r
 219     }                                                                                                                                  \r
 220     else                                                                                                                               \r
 221     {                                                                                                                                  \r
 222         return ERR_DSI_OUT_OF_BOUND;                                                                                                   \r
 223     }                                                                                                                                  \r
 224 }                                                                                                                                      \r
 225 dsih_error_t mipi_dsih_hal_dpi_video_packet_size(dsih_ctrl_t * instance, uint16_t size)                                                \r
 226 {                                                                                                                                      \r
 227     if (size < 0x7ff) /* 11-bit field */                                                                                               \r
 228     {                                                                                                                                  \r
 229         mipi_dsih_write_part(instance, R_DSI_HOST_VID_PKT_CFG, size, 0, 11);                                                           \r
 230         return OK;                                                                                                                     \r
 231     }                                                                                                                                  \r
 232     else                                                                                                                               \r
 233     {                                                                                                                                  \r
 234         return ERR_DSI_OUT_OF_BOUND;                                                                                                   \r
 235     }                                                                                                                                  \r
 236 }                                                                                                                                      \r
 237 void mipi_dsih_hal_tear_effect_ack_en(dsih_ctrl_t * instance, int enable)                                                              \r
 238 {                                                                                                                                      \r
 239     mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, enable, 14, 1);                                                            \r
 240 }                                                                                                                                      \r
 241 void mipi_dsih_hal_cmd_ack_en(dsih_ctrl_t * instance, int enable)                                                                      \r
 242 {                                                                                                                                      \r
 243     mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, enable, 13, 1);                                                            \r
 244 }                                                                                                                                      \r
 245 dsih_error_t mipi_dsih_hal_dcs_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp)                                        \r
 246 {                                                                                                                                      \r
 247     switch (no_of_param)                                                                                                               \r
 248     {                                                                                                                                  \r
 249         case 0:                                                                                                                        \r
 250             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 7, 1);                                                         \r
 251             break;                                                                                                                     \r
 252         case 1:                                                                                                                        \r
 253             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 8, 1);                                                         \r
 254             break;                                                                                                                     \r
 255         default:                                                                                                                       \r
 256             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 12, 1);                                                        \r
 257             break;                                                                                                                     \r
 258     }                                                                                                                                  \r
 259     return OK;                                                                                                                         \r
 260 }                                                                                                                                      \r
 261 dsih_error_t mipi_dsih_hal_dcs_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp)                                        \r
 262 {                                                                                                                                      \r
 263     dsih_error_t err = OK;                                                                                                             \r
 264     switch (no_of_param)                                                                                                               \r
 265     {                                                                                                                                  \r
 266         case 0:                                                                                                                        \r
 267             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 9, 1);                                                         \r
 268             break;                                                                                                                     \r
 269         default:                                                                                                                       \r
 270             if (instance->log_error != 0)                                                                                              \r
 271             {                                                                                                                          \r
 272                 instance->log_error("undefined DCS Read packet type");                                                                 \r
 273             }                                                                                                                          \r
 274             err = ERR_DSI_OUT_OF_BOUND;                                                                                                \r
 275             break;                                                                                                                     \r
 276     }                                                                                                                                  \r
 277     return err;                                                                                                                        \r
 278 }\r
 279 \r
 280 /*Jessica add begin: to support max read packet size command */\r
 281 dsih_error_t mipi_dsih_hal_max_rd_packet_size_type(dsih_ctrl_t * instance, int lp)\r
 282 {\r
 283     dsih_error_t err = OK;\r
 284     mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 10, 1);\r
 285     return err;\r
 286 }\r
 287 /*Jessica add end*/\r
 288 \r
 289 dsih_error_t mipi_dsih_hal_gen_wr_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp)                                        \r
 290 {                                                                                                                                      \r
 291     switch (no_of_param)                                                                                                               \r
 292     {                                                                                                                                  \r
 293         case 0:                                                                                                                        \r
 294             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 1, 1);                                                         \r
 295             break;                                                                                                                     \r
 296         case 1:                                                                                                                        \r
 297             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 2, 1);                                                         \r
 298             break;                                                                                                                     \r
 299         case 2:                                                                                                                        \r
 300             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 3, 1);                                                         \r
 301             break;                                                                                                                     \r
 302         default:                                                                                                                       \r
 303             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 11, 1);                                                        \r
 304             break;                                                                                                                     \r
 305     }                                                                                                                                  \r
 306     return OK;                                                                                                                         \r
 307 }                                                                                                                                      \r
 308 dsih_error_t mipi_dsih_hal_gen_rd_tx_type(dsih_ctrl_t * instance, unsigned no_of_param, int lp)                                        \r
 309 {                                                                                                                                      \r
 310     dsih_error_t err = OK;                                                                                                             \r
 311     switch (no_of_param)                                                                                                               \r
 312     {                                                                                                                                  \r
 313         case 0:                                                                                                                        \r
 314             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 4, 1);                                                         \r
 315             break;                                                                                                                     \r
 316         case 1:                                                                                                                        \r
 317             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 5, 1);                                                         \r
 318             break;                                                                                                                     \r
 319         case 2:                                                                                                                        \r
 320             mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 6, 1);                                                         \r
 321             break;                                                                                                                     \r
 322         default:                                                                                                                       \r
 323             if (instance->log_error != 0)                                                                                              \r
 324             {                                                                                                                          \r
 325                 instance->log_error("undefined Generic Read packet type");                                                             \r
 326             }                                                                                                                          \r
 327             err = ERR_DSI_OUT_OF_BOUND;                                                                                                \r
 328             break;                                                                                                                     \r
 329     }                                                                                                                                  \r
 330     return err;                                                                                                                        \r
 331 }                                                                                                                                      \r
 332 void mipi_dsih_hal_max_rd_size_tx_type(dsih_ctrl_t * instance, int lp)                                                                 \r
 333 {                                                                                                                                      \r
 334     mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, lp, 10, 1);                                                                \r
 335 }                                                                                                                                      \r
 336 void mipi_dsih_hal_gen_cmd_mode_en(dsih_ctrl_t * instance, int enable)                                                                 \r
 337 {                                                                                                                                      \r
 338     mipi_dsih_write_part(instance, R_DSI_HOST_CMD_MODE_CFG, enable, 0, 1);                                                             \r
 339 }                                                                                                                                      \r
 340 int mipi_dsih_hal_gen_is_cmd_mode(dsih_ctrl_t * instance)                                                                              \r
 341 {                                                                                                                                      \r
 342     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_MODE_CFG, 0, 1);                                                               \r
 343 }                                                                                                                                      \r
 344 void mipi_dsih_hal_dpi_hline(dsih_ctrl_t * instance, uint16_t time)                                                                    \r
 345 {                                                                                                                                      \r
 346     mipi_dsih_write_part(instance, R_DSI_HOST_TMR_LINE_CFG, time, 18, 14);                                                             \r
 347 }                                                                                                                                      \r
 348 void mipi_dsih_hal_dpi_hbp(dsih_ctrl_t * instance, uint16_t time)                                                                      \r
 349 {                                                                                                                                      \r
 350     mipi_dsih_write_part(instance, R_DSI_HOST_TMR_LINE_CFG, time, 9, 9);                                                               \r
 351 }                                                                                                                                      \r
 352 void mipi_dsih_hal_dpi_hsa(dsih_ctrl_t * instance, uint16_t time)                                                                      \r
 353 {                                                                                                                                      \r
 354     mipi_dsih_write_part(instance, R_DSI_HOST_TMR_LINE_CFG, time, 0, 9);                                                               \r
 355 }                                                                                                                                      \r
 356 void mipi_dsih_hal_dpi_vactive(dsih_ctrl_t * instance, uint16_t lines)                                                                 \r
 357 {                                                                                                                                      \r
 358     mipi_dsih_write_part(instance, R_DSI_HOST_VTIMING_CFG, lines, 16, 11);                                                             \r
 359 }                                                                                                                                      \r
 360 void mipi_dsih_hal_dpi_vfp(dsih_ctrl_t * instance, uint16_t lines)                                                                     \r
 361 {                                                                                                                                      \r
 362     mipi_dsih_write_part(instance, R_DSI_HOST_VTIMING_CFG, lines, 10, 6);                                                              \r
 363 }                                                                                                                                      \r
 364 void mipi_dsih_hal_dpi_vbp(dsih_ctrl_t * instance, uint16_t lines)                                                                     \r
 365 {                                                                                                                                      \r
 366     mipi_dsih_write_part(instance, R_DSI_HOST_VTIMING_CFG, lines, 4, 6);                                                               \r
 367 }                                                                                                                                      \r
 368 void mipi_dsih_hal_dpi_vsync(dsih_ctrl_t * instance, uint16_t lines)                                                                   \r
 369 {                                                                                                                                      \r
 370     mipi_dsih_write_part(instance, R_DSI_HOST_VTIMING_CFG, lines, 0, 4);                                                               \r
 371 }                                                                                                                                      \r
 372 void mipi_dsih_hal_timeout_clock_division(dsih_ctrl_t * instance, uint8_t byte_clk_division_factor)                                    \r
 373 {                                                                                                                                      \r
 374     mipi_dsih_write_part(instance, R_DSI_HOST_CLK_MGR, byte_clk_division_factor, 8, 8);                                                \r
 375 }                                                                                                                                      \r
 376 void mipi_dsih_hal_lp_rx_timeout(dsih_ctrl_t * instance, uint16_t count)                                                               \r
 377 {                                                                                                                                      \r
 378     mipi_dsih_write_part(instance, R_DSI_HOST_TO_CNT_CFG, count, 16, 16);                                                              \r
 379 }                                                                                                                                      \r
 380 void mipi_dsih_hal_hs_tx_timeout(dsih_ctrl_t * instance, uint16_t count)                                                               \r
 381 {                                                                                                                                      \r
 382     mipi_dsih_write_part(instance, R_DSI_HOST_TO_CNT_CFG, count, 0, 16);                                                               \r
 383 }                                                                                                                                      \r
 384 uint32_t mipi_dsih_hal_error_status_0(dsih_ctrl_t * instance, uint32_t mask)                                                           \r
 385 {                                                                                                                                      \r
 386     return (mipi_dsih_read_word(instance, R_DSI_HOST_ERROR_ST0) & mask);                                                               \r
 387 }                                                                                                                                      \r
 388 uint32_t mipi_dsih_hal_error_status_1(dsih_ctrl_t * instance, uint32_t mask)                                                           \r
 389 {                                                                                                                                      \r
 390     return (mipi_dsih_read_word(instance, R_DSI_HOST_ERROR_ST1) & mask);                                                               \r
 391 }                                                                                                                                      \r
 392 void mipi_dsih_hal_error_mask_0(dsih_ctrl_t * instance, uint32_t mask)                                                                 \r
 393 {                                                                                                                                      \r
 394     mipi_dsih_write_word(instance, R_DSI_HOST_ERROR_MSK0, mask);                                                                       \r
 395 }                                                                                                                                      \r
 396 uint32_t mipi_dsih_hal_get_error_mask_0(dsih_ctrl_t * instance, uint32_t mask)                                                         \r
 397 {                                                                                                                                      \r
 398     return (mipi_dsih_read_word(instance, R_DSI_HOST_ERROR_MSK0) & mask);                                                              \r
 399 }                                                                                                                                      \r
 400 void mipi_dsih_hal_error_mask_1(dsih_ctrl_t * instance, uint32_t mask)                                                                 \r
 401 {                                                                                                                                      \r
 402     mipi_dsih_write_word(instance, R_DSI_HOST_ERROR_MSK1, mask);                                                                       \r
 403 }                                                                                                                                      \r
 404 uint32_t mipi_dsih_hal_get_error_mask_1(dsih_ctrl_t * instance, uint32_t mask)                                                         \r
 405 {                                                                                                                                      \r
 406     return (mipi_dsih_read_word(instance, R_DSI_HOST_ERROR_MSK1) & mask);                                                              \r
 407 }                                                                                                                                      \r
 408 /* DBI NOT IMPLEMENTED */                                                                                                              \r
 409 void mipi_dsih_hal_dbi_out_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);                                  \r
 410 void mipi_dsih_hal_dbi_in_color_coding(dsih_ctrl_t * instance, uint8_t color_depth, uint8_t option);                                   \r
 411 void mipi_dsih_hal_dbi_lut_size(dsih_ctrl_t * instance, uint8_t size);                                                                 \r
 412 void mipi_dsih_hal_dbi_partitioning_en(dsih_ctrl_t * instance, int enable);                                                            \r
 413 void mipi_dsih_hal_dbi_dcs_vc(dsih_ctrl_t * instance, uint8_t vc);                                                                     \r
 414 void mipi_dsih_hal_dbi_max_cmd_size(dsih_ctrl_t * instance, uint16_t size);                                                            \r
 415 void mipi_dsih_hal_dbi_cmd_size(dsih_ctrl_t * instance, uint16_t size);                                                                \r
 416 void mipi_dsih_hal_dbi_max_cmd_size(dsih_ctrl_t * instance, uint16_t size);                                                            \r
 417 int mipi_dsih_hal_dbi_rd_cmd_busy(dsih_ctrl_t * instance);                                                                             \r
 418 int mipi_dsih_hal_dbi_read_fifo_full(dsih_ctrl_t * instance);                                                                          \r
 419 int mipi_dsih_hal_dbi_read_fifo_empty(dsih_ctrl_t * instance);                                                                         \r
 420 int mipi_dsih_hal_dbi_write_fifo_full(dsih_ctrl_t * instance);                                                                         \r
 421 int mipi_dsih_hal_dbi_write_fifo_empty(dsih_ctrl_t * instance);                                                                        \r
 422 int mipi_dsih_hal_dbi_cmd_fifo_full(dsih_ctrl_t * instance);                                                                           \r
 423 int mipi_dsih_hal_dbi_cmd_fifo_empty(dsih_ctrl_t * instance);                                                                          \r
 424                                                                                                                                        \r
 425 dsih_error_t mipi_dsih_hal_gen_packet_header(dsih_ctrl_t * instance, uint8_t vc, uint8_t packet_type, uint8_t ms_byte, uint8_t ls_byte)\r
 426 {                                                                                                                                      \r
 427     if (vc < 4)                                                                                                                        \r
 428     {                                                                                                                                  \r
 429         mipi_dsih_write_part(instance, R_DSI_HOST_GEN_HDR, (ms_byte <<  16) | (ls_byte << 8 ) | ((vc << 6) | packet_type), 0, 24);     \r
 430         return OK;                                                                                                                     \r
 431     }                                                                                                                                  \r
 432     return  ERR_DSI_OVERFLOW;                                                                                                          \r
 433 }                                                                                                                                      \r
 434 dsih_error_t mipi_dsih_hal_gen_packet_payload(dsih_ctrl_t * instance, uint32_t payload)                                                \r
 435 {                                                                                                                                      \r
 436     if (mipi_dsih_hal_gen_write_fifo_full(instance))                                                                                   \r
 437     {                                                                                                                                  \r
 438         return ERR_DSI_OVERFLOW;                                                                                                       \r
 439     }                                                                                                                                  \r
 440     mipi_dsih_write_word(instance, R_DSI_HOST_GEN_PLD_DATA, payload);                                                                  \r
 441     return OK;                                                                                                                         \r
 442                                                                                                                                        \r
 443 }                                                                                                                                      \r
 444 dsih_error_t  mipi_dsih_hal_gen_read_payload(dsih_ctrl_t * instance, uint32_t* payload)                                                \r
 445 {                                                                                                                                      \r
 446     *payload = mipi_dsih_read_word(instance, R_DSI_HOST_GEN_PLD_DATA);                                                                 \r
 447     return OK;                                                                                                                         \r
 448 }                                                                                                                                      \r
 449                                                                                                                                        \r
 450 void mipi_dsih_hal_gen_rd_vc(dsih_ctrl_t * instance, uint8_t vc)                                                                       \r
 451 {                                                                                                                                      \r
 452     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, vc, 5, 2);                                                                   \r
 453 }                                                                                                                                      \r
 454 void mipi_dsih_hal_gen_eotp_rx_en(dsih_ctrl_t * instance, int enable)                                                                  \r
 455 {                                                                                                                                      \r
 456     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, enable, 1, 1);                                                               \r
 457 }                                                                                                                                      \r
 458 void mipi_dsih_hal_gen_eotp_tx_en(dsih_ctrl_t * instance, int enable)                                                                  \r
 459 {                                                                                                                                      \r
 460     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, enable, 0, 1);                                                               \r
 461 }                                                                                                                                      \r
 462 void mipi_dsih_hal_bta_en(dsih_ctrl_t * instance, int enable)                                                                          \r
 463 {                                                                                                                                      \r
 464     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, enable, 2, 1);                                                               \r
 465 }                                                                                                                                      \r
 466 void mipi_dsih_hal_gen_ecc_rx_en(dsih_ctrl_t * instance, int enable)                                                                   \r
 467 {                                                                                                                                      \r
 468     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, enable, 3, 1);                                                               \r
 469 }                                                                                                                                      \r
 470 void mipi_dsih_hal_gen_crc_rx_en(dsih_ctrl_t * instance, int enable)                                                                   \r
 471 {                                                                                                                                      \r
 472     mipi_dsih_write_part(instance, R_DSI_HOST_PCKHDL_CFG, enable, 4, 1);                                                               \r
 473 }                                                                                                                                      \r
 474 int mipi_dsih_hal_gen_rd_cmd_busy(dsih_ctrl_t * instance)                                                                              \r
 475 {                                                                                                                                      \r
 476     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 6, 1);                                                             \r
 477 }                                                                                                                                      \r
 478 int mipi_dsih_hal_gen_read_fifo_full(dsih_ctrl_t * instance)                                                                           \r
 479 {                                                                                                                                      \r
 480     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 5, 1);                                                             \r
 481 }                                                                                                                                      \r
 482 int mipi_dsih_hal_gen_read_fifo_empty(dsih_ctrl_t * instance)                                                                          \r
 483 {                                                                                                                                      \r
 484     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 4, 1);                                                             \r
 485 }                                                                                                                                      \r
 486 int mipi_dsih_hal_gen_write_fifo_full(dsih_ctrl_t * instance)                                                                          \r
 487 {                                                                                                                                      \r
 488     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 3, 1);                                                             \r
 489 }                                                                                                                                      \r
 490 int mipi_dsih_hal_gen_write_fifo_empty(dsih_ctrl_t * instance)                                                                         \r
 491 {                                                                                                                                      \r
 492     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 2, 1);                                                             \r
 493 }                                                                                                                                      \r
 494 int mipi_dsih_hal_gen_cmd_fifo_full(dsih_ctrl_t * instance)                                                                            \r
 495 {                                                                                                                                      \r
 496     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 1, 1);                                                             \r
 497 }                                                                                                                                      \r
 498 int mipi_dsih_hal_gen_cmd_fifo_empty(dsih_ctrl_t * instance)                                                                           \r
 499 {                                                                                                                                      \r
 500     return mipi_dsih_read_part(instance, R_DSI_HOST_CMD_PKT_STATUS, 0, 1);                                                             \r
 501 }                                                                                                                                      \r
 502 /* only if DPI */                                                                                                                      \r
 503 dsih_error_t mipi_dsih_phy_hs2lp_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles)                                             \r
 504 {                                                                                                                                      \r
 505     //mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 20, 8);  \r
 506     mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 24, 8);\r
 507     return OK;                                                                                                                         \r
 508 }                                                                                                                                      \r
 509 dsih_error_t mipi_dsih_phy_lp2hs_config(dsih_ctrl_t * instance, uint8_t no_of_byte_cycles)                                             \r
 510 {                                                                                                                                      \r
 511     //mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 12, 8);   \r
 512     mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 16, 8); \r
 513     return OK;                                                                                                                         \r
 514 }                                                                                                                                      \r
 515 dsih_error_t mipi_dsih_phy_bta_time(dsih_ctrl_t * instance, uint16_t no_of_byte_cycles)                                                \r
 516 { \r
 517         /*Jessica modified: From ASIC, the second table in spec is correct, this 15 bits are max rd time*/\r
 518     if (no_of_byte_cycles < 0x8000) /* 15-bit field */\r
 519     {\r
 520         //mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 0, 12);\r
 521         mipi_dsih_write_part(instance, R_DSI_HOST_PHY_TMR_CFG, no_of_byte_cycles, 0, 15);\r
 522     }                                                                                                                                  \r
 523     else                                                                                                                               \r
 524     {                                                                                                                                  \r
 525         return ERR_DSI_OVERFLOW;                                                                                                       \r
 526     }                                                                                                                                  \r
 527     return OK;                                                                                                                         \r
 528 }                                                                                                                                      \r
 529 /* */