drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/mtd/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46
  47 #ifdef CONFIG_MTD_PARTITIONS
  48 #include <linux/mtd/partitions.h>
  49 #endif
  50
  51 #include <asm/io.h>
  52 #include <asm/errno.h>
  53
  54 /*
  55  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  56  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  57  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  58  * which is greater than (max NAND reset time / NAND status read time).
  59  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  60  */
  61 #ifndef CONFIG_SYS_NAND_RESET_CNT
  62 #define CONFIG_SYS_NAND_RESET_CNT 200000
  63 #endif
  64
  65 /* Define default oob placement schemes for large and small page devices */
  66 static struct nand_ecclayout nand_oob_8 = {
  67         .eccbytes = 3,
  68         .eccpos = {0, 1, 2},
  69         .oobfree = {
  70                 {.offset = 3,
  71                  .length = 2},
  72                 {.offset = 6,
  73                  .length = 2}}
  74 };
  75
  76 static struct nand_ecclayout nand_oob_16 = {
  77         .eccbytes = 6,
  78         .eccpos = {0, 1, 2, 3, 6, 7},
  79         .oobfree = {
  80                 {.offset = 8,
  81                  . length = 8}}
  82 };
  83
  84 static struct nand_ecclayout nand_oob_64 = {
  85         .eccbytes = 24,
  86         .eccpos = {
  87                    40, 41, 42, 43, 44, 45, 46, 47,
  88                    48, 49, 50, 51, 52, 53, 54, 55,
  89                    56, 57, 58, 59, 60, 61, 62, 63},
  90         .oobfree = {
  91                 {.offset = 2,
  92                  .length = 38}}
  93 };
  94
  95 static struct nand_ecclayout nand_oob_128 = {
  96         .eccbytes = 48,
  97         .eccpos = {
  98                     80,  81,  82,  83,  84,  85,  86,  87,
  99                     88,  89,  90,  91,  92,  93,  94,  95,
 100                     96,  97,  98,  99, 100, 101, 102, 103,
 101                    104, 105, 106, 107, 108, 109, 110, 111,
 102                    112, 113, 114, 115, 116, 117, 118, 119,
 103                    120, 121, 122, 123, 124, 125, 126, 127},
 104         .oobfree = {
 105                 {.offset = 2,
 106                  .length = 78}}
 107 };
 108
 109
 110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 111                            int new_state);
 112
 113 int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 114                              struct mtd_oob_ops *ops);
 115
 116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 117
 118 /**
 119  * nand_release_device - [GENERIC] release chip
 120  * @mtd:        MTD device structure
 121  *
 122  * Deselect, release chip lock and wake up anyone waiting on the device
 123  */
 124 static void nand_release_device (struct mtd_info *mtd)
 125 {
 126         struct nand_chip *this = mtd->priv;
 127         this->select_chip(mtd, -1);     /* De-select the NAND device */
 128 }
 129
 130 /**
 131  * nand_read_byte - [DEFAULT] read one byte from the chip
 132  * @mtd:        MTD device structure
 133  *
 134  * Default read function for 8bit buswith
 135  */
 136 static uint8_t nand_read_byte(struct mtd_info *mtd)
 137 {
 138         struct nand_chip *chip = mtd->priv;
 139         return readb(chip->IO_ADDR_R);
 140 }
 141
 142 /**
 143  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 144  * @mtd:        MTD device structure
 145  *
 146  * Default read function for 16bit buswith with
 147  * endianess conversion
 148  */
 149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152
 153 #ifdef CONFIG_MTD_NAND_SPRD
 154         return (uint8_t)readl(chip->IO_ADDR_R);
 155 #else
 156         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 157 #endif
 158 }
 159
 160 /**
 161  * nand_read_word - [DEFAULT] read one word from the chip
 162  * @mtd:        MTD device structure
 163  *
 164  * Default read function for 16bit buswith without
 165  * endianess conversion
 166  */
 167 static u16 nand_read_word(struct mtd_info *mtd)
 168 {
 169         struct nand_chip *chip = mtd->priv;
 170         return readw(chip->IO_ADDR_R);
 171 }
 172
 173 /**
 174  * nand_select_chip - [DEFAULT] control CE line
 175  * @mtd:        MTD device structure
 176  * @chipnr:     chipnumber to select, -1 for deselect
 177  *
 178  * Default select function for 1 chip devices.
 179  */
 180 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183
 184         switch (chipnr) {
 185         case -1:
 186                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 187                 break;
 188         case 0:
 189                 break;
 190
 191         default:
 192                 BUG();
 193         }
 194 }
 195
 196 /**
 197  * nand_write_buf - [DEFAULT] write buffer to chip
 198  * @mtd:        MTD device structure
 199  * @buf:        data buffer
 200  * @len:        number of bytes to write
 201  *
 202  * Default write function for 8bit buswith
 203  */
 204 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 205 {
 206         int i;
 207         struct nand_chip *chip = mtd->priv;
 208
 209 #ifdef CONFIG_MTD_NAND_SPRD
 210         memcpy(chip->IO_ADDR_W, buf, len);
 211 #else
 212         for (i = 0; i < len; i++)
 213                 writeb(buf[i], chip->IO_ADDR_W);
 214 #endif
 215 }
 216
 217 /**
 218  * nand_read_buf - [DEFAULT] read chip data into buffer
 219  * @mtd:        MTD device structure
 220  * @buf:        buffer to store date
 221  * @len:        number of bytes to read
 222  *
 223  * Default read function for 8bit buswith
 224  */
 225 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 226 {
 227         int i;
 228         struct nand_chip *chip = mtd->priv;
 229
 230 #ifdef CONFIG_MTD_NAND_SPRD
 231         memcpy(buf, chip->IO_ADDR_R, len);
 232 #else
 233         for (i = 0; i < len; i++)
 234                 buf[i] = readb(chip->IO_ADDR_R);
 235 #endif
 236 }
 237
 238 /**
 239  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 240  * @mtd:        MTD device structure
 241  * @buf:        buffer containing the data to compare
 242  * @len:        number of bytes to compare
 243  *
 244  * Default verify function for 8bit buswith
 245  */
 246 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 247 {
 248         int i;
 249         struct nand_chip *chip = mtd->priv;
 250
 251         for (i = 0; i < len; i++)
 252                 if (buf[i] != readb(chip->IO_ADDR_R))
 253                         return -EFAULT;
 254         return 0;
 255 }
 256
 257 /**
 258  * nand_write_buf16 - [DEFAULT] write buffer to chip
 259  * @mtd:        MTD device structure
 260  * @buf:        data buffer
 261  * @len:        number of bytes to write
 262  *
 263  * Default write function for 16bit buswith
 264  */
 265 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 266 {
 267         int i;
 268         struct nand_chip *chip = mtd->priv;
 269
 270 #ifdef CONFIG_MTD_NAND_SPRD
 271         memcpy(chip->IO_ADDR_W, buf, len);
 272 #else
 273         u16 *p = (u16 *) buf;
 274         len >>= 1;
 275
 276         for (i = 0; i < len; i++)
 277                 writew(p[i], chip->IO_ADDR_W);
 278 #endif
 279 }
 280
 281 /**
 282  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 283  * @mtd:        MTD device structure
 284  * @buf:        buffer to store date
 285  * @len:        number of bytes to read
 286  *
 287  * Default read function for 16bit buswith
 288  */
 289 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 290 {
 291         int i;
 292         struct nand_chip *chip = mtd->priv;
 293
 294 #ifdef CONFIG_MTD_NAND_SPRD
 295         memcpy(buf, chip->IO_ADDR_R, len);
 296 #else
 297         u16 *p = (u16 *) buf;
 298         len >>= 1;
 299
 300         for (i = 0; i < len; i++)
 301                 p[i] = readw(chip->IO_ADDR_R);
 302 #endif
 303 }
 304
 305 /**
 306  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 307  * @mtd:        MTD device structure
 308  * @buf:        buffer containing the data to compare
 309  * @len:        number of bytes to compare
 310  *
 311  * Default verify function for 16bit buswith
 312  */
 313 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 314 {
 315         int i;
 316         struct nand_chip *chip = mtd->priv;
 317         u16 *p = (u16 *) buf;
 318         len >>= 1;
 319
 320         for (i = 0; i < len; i++)
 321                 if (p[i] != readw((uint16_t *)chip->IO_ADDR_R + i))
 322                         return -EFAULT;
 323
 324         return 0;
 325 }
 326
 327 /**
 328  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 329  * @mtd:        MTD device structure
 330  * @ofs:        offset from device start
 331  * @getchip:    0, if the chip is already selected
 332  *
 333  * Check, if the block is bad.
 334  */
 335 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 336 {
 337         int page, chipnr, res = 0;
 338         struct nand_chip *chip = mtd->priv;
 339         u16 bad;
 340
 341         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 342
 343         if (getchip) {
 344                 chipnr = (int)(ofs >> chip->chip_shift);
 345
 346                 nand_get_device(chip, mtd, FL_READING);
 347
 348                 /* Select the NAND device */
 349                 chip->select_chip(mtd, chipnr);
 350         }
 351
 352         if (chip->options & NAND_BUSWIDTH_16) {
 353                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 354                               page);
 355                 bad = cpu_to_le16(chip->read_word(mtd));
 356                 if (chip->badblockpos & 0x1)
 357                         bad >>= 8;
 358                 if ((bad & 0xFF) != 0xff)
 359                         res = 1;
 360         } else {
 361                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 362                 if (chip->read_byte(mtd) != 0xff)
 363                         res = 1;
 364         }
 365
 366         if (getchip)
 367                 nand_release_device(mtd);
 368
 369         return res;
 370 }
 371
 372 /**
 373  * nand_default_block_markbad - [DEFAULT] mark a block bad
 374  * @mtd:        MTD device structure
 375  * @ofs:        offset from device start
 376  *
 377  * This is the default implementation, which can be overridden by
 378  * a hardware specific driver.
 379 */
 380 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 381 {
 382         struct nand_chip *chip = mtd->priv;
 383         uint8_t buf[2] = { 0x55, 0xaa };
 384         int block, ret;
 385 #ifndef CONFIG_MTD_NAND_SC8810
 386         mtd_oob_mode_t sprd_mode;
 387 #endif
 388         /* Get block number */
 389         block = (int)(ofs >> chip->bbt_erase_shift);
 390         if (chip->bbt)
 391                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 392
 393         /* Do we have a flash based bad block table ? */
 394         if (chip->options & NAND_USE_FLASH_BBT)
 395                 ret = nand_update_bbt(mtd, ofs);
 396         else {
 397                 /* We write two bytes, so we dont have to mess with 16 bit
 398                  * access
 399                  */
 400                 nand_get_device(chip, mtd, FL_WRITING);
 401                 ofs += mtd->oobsize;
 402                 chip->ops.len = chip->ops.ooblen = 2;
 403                 chip->ops.datbuf = NULL;
 404                 chip->ops.oobbuf = buf;
 405                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 406
 407 #ifndef CONFIG_MTD_NAND_SC8810
 408                 sprd_mode = chip->ops.mode;
 409                 if (chip->ops.mode == MTD_OOB_AUTO)
 410                         chip->ops.mode = MTD_OOB_RAW;
 411 #endif
 412                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 413
 414 #ifndef CONFIG_MTD_NAND_SC8810
 415                 chip->ops.mode = sprd_mode;
 416 #endif
 417                 nand_release_device(mtd);
 418         }
 419         if (!ret)
 420                 mtd->ecc_stats.badblocks++;
 421
 422         return ret;
 423 }
 424
 425 /**
 426  * nand_check_wp - [GENERIC] check if the chip is write protected
 427  * @mtd:        MTD device structure
 428  * Check, if the device is write protected
 429  *
 430  * The function expects, that the device is already selected
 431  */
 432 static int nand_check_wp(struct mtd_info *mtd)
 433 {
 434         struct nand_chip *chip = mtd->priv;
 435         /* Check the WP bit */
 436         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 437         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 438 }
 439
 440 /**
 441  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 442  * @mtd:        MTD device structure
 443  * @ofs:        offset from device start
 444  * @getchip:    0, if the chip is already selected
 445  * @allowbbt:   1, if its allowed to access the bbt area
 446  *
 447  * Check, if the block is bad. Either by reading the bad block table or
 448  * calling of the scan function.
 449  */
 450 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 451                                int allowbbt)
 452 {
 453         struct nand_chip *chip = mtd->priv;
 454
 455         if (!(chip->options & NAND_BBT_SCANNED)) {
 456                 chip->options |= NAND_BBT_SCANNED;
 457 #ifdef SPRD_EVM_TAG_ON
 458                 SPRD_EVM_TAG(8);
 459 #endif
 460                 chip->scan_bbt(mtd);
 461 #ifdef SPRD_EVM_TAG_ON
 462                 SPRD_EVM_TAG(9);
 463 #endif
 464         }
 465
 466         if (!chip->bbt)
 467                 return chip->block_bad(mtd, ofs, getchip);
 468
 469         /* Return info from the table */
 470         return nand_isbad_bbt(mtd, ofs, allowbbt);
 471 }
 472
 473 /*
 474  * Wait for the ready pin, after a command
 475  * The timeout is catched later.
 476  */
 477 void nand_wait_ready(struct mtd_info *mtd)
 478 {
 479         struct nand_chip *chip = mtd->priv;
 480         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 481
 482         reset_timer();
 483
 484         /* wait until command is processed or timeout occures */
 485         while (get_timer(0) < timeo) {
 486                 if (chip->dev_ready)
 487                         if (chip->dev_ready(mtd))
 488                                 break;
 489         }
 490 }
 491
 492 /**
 493  * nand_command - [DEFAULT] Send command to NAND device
 494  * @mtd:        MTD device structure
 495  * @command:    the command to be sent
 496  * @column:     the column address for this command, -1 if none
 497  * @page_addr:  the page address for this command, -1 if none
 498  *
 499  * Send command to NAND device. This function is used for small page
 500  * devices (256/512 Bytes per page)
 501  */
 502 static void nand_command(struct mtd_info *mtd, unsigned int command,
 503                          int column, int page_addr)
 504 {
 505         register struct nand_chip *chip = mtd->priv;
 506         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 507         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 508
 509         /*
 510          * Write out the command to the device.
 511          */
 512         if (command == NAND_CMD_SEQIN) {
 513                 int readcmd;
 514
 515                 if (column >= mtd->writesize) {
 516                         /* OOB area */
 517                         column -= mtd->writesize;
 518                         readcmd = NAND_CMD_READOOB;
 519                 } else if (column < 256) {
 520                         /* First 256 bytes --> READ0 */
 521                         readcmd = NAND_CMD_READ0;
 522                 } else {
 523                         column -= 256;
 524                         readcmd = NAND_CMD_READ1;
 525                 }
 526                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 527                 ctrl &= ~NAND_CTRL_CHANGE;
 528         }
 529         chip->cmd_ctrl(mtd, command, ctrl);
 530
 531         /*
 532          * Address cycle, when necessary
 533          */
 534         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 535         /* Serially input address */
 536         if (column != -1) {
 537                 /* Adjust columns for 16 bit buswidth */
 538                 if (chip->options & NAND_BUSWIDTH_16)
 539                         column >>= 1;
 540                 chip->cmd_ctrl(mtd, column, ctrl);
 541                 ctrl &= ~NAND_CTRL_CHANGE;
 542         }
 543         if (page_addr != -1) {
 544                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 545                 ctrl &= ~NAND_CTRL_CHANGE;
 546                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 547                 /* One more address cycle for devices > 32MiB */
 548                 if (chip->chipsize > (32 << 20))
 549                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 550         }
 551         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 552
 553         /*
 554          * program and erase have their own busy handlers
 555          * status and sequential in needs no delay
 556          */
 557         switch (command) {
 558
 559         case NAND_CMD_PAGEPROG:
 560         case NAND_CMD_ERASE1:
 561         case NAND_CMD_ERASE2:
 562         case NAND_CMD_SEQIN:
 563         case NAND_CMD_STATUS:
 564                 return;
 565
 566         case NAND_CMD_RESET:
 567                 if (chip->dev_ready)
 568                         break;
 569                 udelay(chip->chip_delay);
 570                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 571                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 572                 chip->cmd_ctrl(mtd,
 573                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 574                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 575                         (rst_sts_cnt--));
 576                 return;
 577
 578                 /* This applies to read commands */
 579         default:
 580                 /*
 581                  * If we don't have access to the busy pin, we apply the given
 582                  * command delay
 583                  */
 584                 if (!chip->dev_ready) {
 585                         udelay(chip->chip_delay);
 586                         return;
 587                 }
 588         }
 589         /* Apply this short delay always to ensure that we do wait tWB in
 590          * any case on any machine. */
 591         ndelay(100);
 592
 593         //nand_wait_ready(mtd);
 594 }
 595
 596 /**
 597  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 598  * @mtd:        MTD device structure
 599  * @command:    the command to be sent
 600  * @column:     the column address for this command, -1 if none
 601  * @page_addr:  the page address for this command, -1 if none
 602  *
 603  * Send command to NAND device. This is the version for the new large page
 604  * devices We dont have the separate regions as we have in the small page
 605  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 606  */
 607 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 608                             int column, int page_addr)
 609 {
 610         register struct nand_chip *chip = mtd->priv;
 611         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 612
 613         /* Emulate NAND_CMD_READOOB */
 614         if (command == NAND_CMD_READOOB) {
 615                 column += mtd->writesize;
 616                 command = NAND_CMD_READ0;
 617         }
 618
 619         /* Command latch cycle */
 620         chip->cmd_ctrl(mtd, command & 0xff,
 621                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 622
 623         if (column != -1 || page_addr != -1) {
 624                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 625
 626                 /* Serially input address */
 627                 if (column != -1) {
 628                         /* Adjust columns for 16 bit buswidth */
 629                         if (chip->options & NAND_BUSWIDTH_16)
 630                                 column >>= 1;
 631 #ifdef CONFIG_MTD_NAND_SPRD
 632                         chip->cmd_ctrl(mtd, column, ctrl);
 633 #else
 634                         chip->cmd_ctrl(mtd, column, ctrl);
 635                         ctrl &= ~NAND_CTRL_CHANGE;
 636                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 637 #endif
 638                 }
 639                 if (page_addr != -1) {
 640 #ifdef CONFIG_MTD_NAND_SPRD
 641                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 642 #else
 643                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 644                         chip->cmd_ctrl(mtd, page_addr >> 8,
 645                                        NAND_NCE | NAND_ALE);
 646                         /* One more address cycle for devices > 128MiB */
 647                         if (chip->chipsize > (128 << 20))
 648                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 649                                                NAND_NCE | NAND_ALE);
 650 #endif
 651                 }
 652         }
 653         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 654
 655         /*
 656          * program and erase have their own busy handlers
 657          * status, sequential in, and deplete1 need no delay
 658          */
 659         switch (command) {
 660
 661         case NAND_CMD_CACHEDPROG:
 662         case NAND_CMD_PAGEPROG:
 663         case NAND_CMD_ERASE1:
 664         case NAND_CMD_ERASE2:
 665         case NAND_CMD_SEQIN:
 666         case NAND_CMD_RNDIN:
 667         case NAND_CMD_STATUS:
 668         case NAND_CMD_DEPLETE1:
 669                 return;
 670
 671                 /*
 672                  * read error status commands require only a short delay
 673                  */
 674         case NAND_CMD_STATUS_ERROR:
 675         case NAND_CMD_STATUS_ERROR0:
 676         case NAND_CMD_STATUS_ERROR1:
 677         case NAND_CMD_STATUS_ERROR2:
 678         case NAND_CMD_STATUS_ERROR3:
 679                 udelay(chip->chip_delay);
 680                 return;
 681
 682         case NAND_CMD_RESET:
 683                 if (chip->dev_ready)
 684                         break;
 685                 udelay(chip->chip_delay);
 686                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 687                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 688                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 689                                NAND_NCE | NAND_CTRL_CHANGE);
 690                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 691                         (rst_sts_cnt--));
 692                 return;
 693
 694         case NAND_CMD_RNDOUT:
 695                 /* No ready / busy check necessary */
 696                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 697                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 698                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 699                                NAND_NCE | NAND_CTRL_CHANGE);
 700                 return;
 701
 702         case NAND_CMD_READ0:
 703                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 704                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 705                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 706                                NAND_NCE | NAND_CTRL_CHANGE);
 707
 708                 /* This applies to read commands */
 709         default:
 710                 /*
 711                  * If we don't have access to the busy pin, we apply the given
 712                  * command delay
 713                  */
 714                 if (!chip->dev_ready) {
 715                         udelay(chip->chip_delay);
 716                         return;
 717                 }
 718         }
 719
 720         /* Apply this short delay always to ensure that we do wait tWB in
 721          * any case on any machine. */
 722         ndelay(100);
 723
 724         nand_wait_ready(mtd);
 725 }
 726
 727 /**
 728  * nand_get_device - [GENERIC] Get chip for selected access
 729  * @chip:       the nand chip descriptor
 730  * @mtd:        MTD device structure
 731  * @new_state:  the state which is requested
 732  *
 733  * Get the device and lock it for exclusive access
 734  */
 735 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 736 {
 737         this->state = new_state;
 738         return 0;
 739 }
 740
 741 /**
 742  * nand_wait - [DEFAULT]  wait until the command is done
 743  * @mtd:        MTD device structure
 744  * @chip:       NAND chip structure
 745  *
 746  * Wait for command done. This applies to erase and program only
 747  * Erase can take up to 400ms and program up to 20ms according to
 748  * general NAND and SmartMedia specs
 749  */
 750 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 751 {
 752         unsigned long   timeo;
 753         int state = this->state;
 754
 755         if (state == FL_ERASING)
 756                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 757         else
 758                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 759
 760         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 761                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 762         else
 763                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 764
 765         reset_timer();
 766
 767         while (1) {
 768                 if (get_timer(0) > timeo) {
 769                         printf("Timeout!");
 770                         return 0x01;
 771                 }
 772
 773                 if (this->dev_ready) {
 774                         if (this->dev_ready(mtd))
 775                                 break;
 776                 } else {
 777                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 778                                 break;
 779                 }
 780         }
 781 #ifdef PPCHAMELON_NAND_TIMER_HACK
 782         reset_timer();
 783         while (get_timer(0) < 10);
 784 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 785
 786         return this->read_byte(mtd);
 787 }
 788
 789 /**
 790  * nand_read_page_raw - [Intern] read raw page data without ecc
 791  * @mtd:        mtd info structure
 792  * @chip:       nand chip info structure
 793  * @buf:        buffer to store read data
 794  * @page:       page number to read
 795  *
 796  * Not for syndrome calculating ecc controllers, which use a special oob layout
 797  */
 798 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 799                               uint8_t *buf, int page)
 800 {
 801         uint8_t ecc_calc[128];
 802         chip->ecc.hwctl(mtd, NAND_ECC_READ);
 803         chip->read_buf(mtd, buf, mtd->writesize);
 804         chip->ecc.calculate(mtd, NULL, ecc_calc);
 805         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 806         return 0;
 807 }
 808
 809 /**
 810  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 811  * @mtd:        mtd info structure
 812  * @chip:       nand chip info structure
 813  * @buf:        buffer to store read data
 814  * @page:       page number to read
 815  *
 816  * We need a special oob layout and handling even when OOB isn't used.
 817  */
 818 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 819                               uint8_t *buf, int page)
 820 {
 821         int eccsize = chip->ecc.size;
 822         int eccbytes = chip->ecc.bytes;
 823         uint8_t *oob = chip->oob_poi;
 824         int steps, size;
 825
 826         for (steps = chip->ecc.steps; steps > 0; steps--) {
 827                 chip->read_buf(mtd, buf, eccsize);
 828                 buf += eccsize;
 829
 830                 if (chip->ecc.prepad) {
 831                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 832                         oob += chip->ecc.prepad;
 833                 }
 834
 835                 chip->read_buf(mtd, oob, eccbytes);
 836                 oob += eccbytes;
 837
 838                 if (chip->ecc.postpad) {
 839                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 840                         oob += chip->ecc.postpad;
 841                 }
 842         }
 843
 844         size = mtd->oobsize - (oob - chip->oob_poi);
 845         if (size)
 846                 chip->read_buf(mtd, oob, size);
 847
 848         return 0;
 849 }
 850
 851 /**
 852  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 853  * @mtd:        mtd info structure
 854  * @chip:       nand chip info structure
 855  * @buf:        buffer to store read data
 856  * @page:       page number to read
 857  */
 858 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 859                                 uint8_t *buf, int page)
 860 {
 861         int i, eccsize = chip->ecc.size;
 862         int eccbytes = chip->ecc.bytes;
 863         int eccsteps = chip->ecc.steps;
 864         uint8_t *p = buf;
 865         uint8_t *ecc_calc = chip->buffers->ecccalc;
 866         uint8_t *ecc_code = chip->buffers->ecccode;
 867         uint32_t *eccpos = chip->ecc.layout->eccpos;
 868
 869         chip->ecc.read_page_raw(mtd, chip, buf, page);
 870
 871         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 872                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 873
 874         for (i = 0; i < chip->ecc.total; i++)
 875                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 876
 877         eccsteps = chip->ecc.steps;
 878         p = buf;
 879
 880         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 881                 int stat;
 882
 883                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 884                 if (stat < 0)
 885                         mtd->ecc_stats.failed++;
 886                 else
 887                         mtd->ecc_stats.corrected += stat;
 888         }
 889         return 0;
 890 }
 891
 892 /**
 893  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 894  * @mtd:        mtd info structure
 895  * @chip:       nand chip info structure
 896  * @data_offs:  offset of requested data within the page
 897  * @readlen:    data length
 898  * @bufpoi:     buffer to store read data
 899  */
 900 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 901 {
 902         int start_step, end_step, num_steps;
 903         uint32_t *eccpos = chip->ecc.layout->eccpos;
 904         uint8_t *p;
 905         int data_col_addr, i, gaps = 0;
 906         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 907         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 908
 909         /* Column address wihin the page aligned to ECC size (256bytes). */
 910         start_step = data_offs / chip->ecc.size;
 911         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 912         num_steps = end_step - start_step + 1;
 913
 914         /* Data size aligned to ECC ecc.size*/
 915         datafrag_len = num_steps * chip->ecc.size;
 916         eccfrag_len = num_steps * chip->ecc.bytes;
 917
 918         data_col_addr = start_step * chip->ecc.size;
 919         /* If we read not a page aligned data */
 920         if (data_col_addr != 0)
 921                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 922
 923         p = bufpoi + data_col_addr;
 924         chip->read_buf(mtd, p, datafrag_len);
 925
 926         /* Calculate  ECC */
 927         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 928                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 929
 930         /* The performance is faster if to position offsets
 931            according to ecc.pos. Let make sure here that
 932            there are no gaps in ecc positions */
 933         for (i = 0; i < eccfrag_len - 1; i++) {
 934                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 935                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 936                         gaps = 1;
 937                         break;
 938                 }
 939         }
 940         if (gaps) {
 941                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 942                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 943         } else {
 944                 /* send the command to read the particular ecc bytes */
 945                 /* take care about buswidth alignment in read_buf */
 946                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 947                 aligned_len = eccfrag_len;
 948                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 949                         aligned_len++;
 950                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 951                         aligned_len++;
 952
 953                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 954                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 955         }
 956
 957         for (i = 0; i < eccfrag_len; i++)
 958                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 959
 960         p = bufpoi + data_col_addr;
 961         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 962                 int stat;
 963
 964                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 965                 if (stat == -1)
 966                         mtd->ecc_stats.failed++;
 967                 else
 968                         mtd->ecc_stats.corrected += stat;
 969         }
 970         return 0;
 971 }
 972
 973 /**
 974  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 975  * @mtd:        mtd info structure
 976  * @chip:       nand chip info structure
 977  * @buf:        buffer to store read data
 978  * @page:       page number to read
 979  *
 980  * Not for syndrome calculating ecc controllers which need a special oob layout
 981  */
 982 static int is_nand_spl_read = 0;
 983 #define CONFIG_SYS_SPL_ECC_POS          8
 984 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 985                                 uint8_t *buf, int page)
 986 {
 987         int i, eccsize = chip->ecc.size;
 988         int eccbytes = chip->ecc.bytes;
 989         int eccsteps = chip->ecc.steps;
 990         uint8_t *p = buf;
 991         uint8_t *ecc_calc = chip->buffers->ecccalc;
 992         uint8_t *ecc_code = chip->buffers->ecccode;
 993         uint32_t *eccpos = chip->ecc.layout->eccpos;
 994         uint8_t tmplayout[64];
 995
 996         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 997                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 998                 chip->read_buf(mtd, p, eccsize);
 999                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1000         }
1001         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1002
1003 #ifdef NAND_DEBUG
1004         printf("nand_read_page_hwecc next\n");
1005         for(i=0;i<64;i++){
1006                 printf("%x ", chip->oob_poi[i]);
1007                 if(i!=0 && i%8==7)
1008                   printf("\n");
1009         }
1010 #endif
1011
1012         if (is_nand_spl_read){
1013                 int eccbytes = chip->ecc.bytes;
1014                 int spare_per_sct = mtd->oobsize / chip->ecc.steps;
1015                 for (i = 0; i < chip->ecc.steps; i ++){
1016                         memcpy(&(ecc_code[i*eccbytes]), &(chip->oob_poi[i * spare_per_sct + CONFIG_SYS_SPL_ECC_POS]), eccbytes);
1017                 }
1018         }else{
1019         for (i = 0; i < chip->ecc.total; i++)
1020                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1021         }
1022
1023         eccsteps = chip->ecc.steps;
1024         p = buf;
1025
1026         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1027                 int stat;
1028
1029                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1030                 if (stat < 0){
1031                         mtd->ecc_stats.failed++;
1032                         printk("%s: ecc correct error %d times\n",__FUNCTION__, mtd->ecc_stats.failed);
1033 #if 0
1034         printk("\nthe all data   page = %d\n", page);
1035         for(i = 0; i < 2048; i++) {
1036                 printk("%02x ", *(p + i));
1037                 if(i % 16 == 15)
1038                   printk("\n");
1039         }
1040
1041         printk("\nthe read ecc\n");
1042         for(i = 0; i < 16; i ++) {
1043                         printk("%02x ", ecc_code[i]/**(read_ecc + i)*/);
1044                         if(i % 4 == 3)
1045                                 printk("\n");
1046         }
1047
1048         printk("\nthe calc ecc\n");
1049         for(i = 0; i < 16; i ++) {
1050                         printk("%02x ", ecc_calc[i]/**(calc_ecc + i)*/);
1051                         if(i % 4 == 3)
1052                                 printk("\n");
1053         }
1054 #endif
1055                 }
1056                 else
1057                         mtd->ecc_stats.corrected += stat;
1058         }
1059         return 0;
1060 }
1061
1062 /**
1063  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1064  * @mtd:        mtd info structure
1065  * @chip:       nand chip info structure
1066  * @buf:        buffer to store read data
1067  * @page:       page number to read
1068  *
1069  * Hardware ECC for large page chips, require OOB to be read first.
1070  * For this ECC mode, the write_page method is re-used from ECC_HW.
1071  * These methods read/write ECC from the OOB area, unlike the
1072  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1073  * "infix ECC" scheme and reads/writes ECC from the data area, by
1074  * overwriting the NAND manufacturer bad block markings.
1075  */
1076 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1077         struct nand_chip *chip, uint8_t *buf, int page)
1078 {
1079         int i, eccsize = chip->ecc.size;
1080         int eccbytes = chip->ecc.bytes;
1081         int eccsteps = chip->ecc.steps;
1082         uint8_t *p = buf;
1083         uint8_t *ecc_code = chip->buffers->ecccode;
1084         uint32_t *eccpos = chip->ecc.layout->eccpos;
1085         uint8_t *ecc_calc = chip->buffers->ecccalc;
1086
1087         /* Read the OOB area first */
1088         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1089         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1090         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1091
1092         for (i = 0; i < chip->ecc.total; i++)
1093                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1094
1095         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1096                 int stat;
1097
1098                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1099                 chip->read_buf(mtd, p, eccsize);
1100                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1101
1102                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1103                 if (stat < 0)
1104                         mtd->ecc_stats.failed++;
1105                 else
1106                         mtd->ecc_stats.corrected += stat;
1107         }
1108         return 0;
1109 }
1110
1111 /**
1112  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1113  * @mtd:        mtd info structure
1114  * @chip:       nand chip info structure
1115  * @buf:        buffer to store read data
1116  * @page:       page number to read
1117  *
1118  * The hw generator calculates the error syndrome automatically. Therefor
1119  * we need a special oob layout and handling.
1120  */
1121 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1122                                    uint8_t *buf, int page)
1123 {
1124         int i, eccsize = chip->ecc.size;
1125         int eccbytes = chip->ecc.bytes;
1126         int eccsteps = chip->ecc.steps;
1127         uint8_t *p = buf;
1128         uint8_t *oob = chip->oob_poi;
1129
1130         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1131                 int stat;
1132
1133                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1134                 chip->read_buf(mtd, p, eccsize);
1135
1136                 if (chip->ecc.prepad) {
1137                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1138                         oob += chip->ecc.prepad;
1139                 }
1140
1141                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1142                 chip->read_buf(mtd, oob, eccbytes);
1143                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1144
1145                 if (stat < 0)
1146                         mtd->ecc_stats.failed++;
1147                 else
1148                         mtd->ecc_stats.corrected += stat;
1149
1150                 oob += eccbytes;
1151
1152                 if (chip->ecc.postpad) {
1153                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1154                         oob += chip->ecc.postpad;
1155                 }
1156         }
1157
1158         /* Calculate remaining oob bytes */
1159         i = mtd->oobsize - (oob - chip->oob_poi);
1160         if (i)
1161                 chip->read_buf(mtd, oob, i);
1162
1163         return 0;
1164 }
1165
1166 /**
1167  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1168  * @chip:       nand chip structure
1169  * @oob:        oob destination address
1170  * @ops:        oob ops structure
1171  * @len:        size of oob to transfer
1172  */
1173 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1174                                   struct mtd_oob_ops *ops, size_t len)
1175 {
1176         switch(ops->mode) {
1177
1178         case MTD_OOB_PLACE:
1179         case MTD_OOB_RAW:
1180                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1181                 return oob + len;
1182
1183         case MTD_OOB_AUTO: {
1184                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1185                 uint32_t boffs = 0, roffs = ops->ooboffs;
1186                 size_t bytes = 0;
1187
1188                 for(; free->length && len; free++, len -= bytes) {
1189                         /* Read request not from offset 0 ? */
1190                         if (unlikely(roffs)) {
1191                                 if (roffs >= free->length) {
1192                                         roffs -= free->length;
1193                                         continue;
1194                                 }
1195                                 boffs = free->offset + roffs;
1196                                 bytes = min_t(size_t, len,
1197                                               (free->length - roffs));
1198                                 roffs = 0;
1199                         } else {
1200                                 bytes = min_t(size_t, len, free->length);
1201                                 boffs = free->offset;
1202                         }
1203                         memcpy(oob, chip->oob_poi + boffs, bytes);
1204                         oob += bytes;
1205                 }
1206                 return oob;
1207         }
1208         default:
1209                 BUG();
1210         }
1211         return NULL;
1212 }
1213
1214 /**
1215  * nand_do_read_ops - [Internal] Read data with ECC
1216  *
1217  * @mtd:        MTD device structure
1218  * @from:       offset to read from
1219  * @ops:        oob ops structure
1220  *
1221  * Internal function. Called with chip held.
1222  */
1223 int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1224                             struct mtd_oob_ops *ops)
1225 {
1226         int chipnr, page, realpage, col, bytes, aligned;
1227         struct nand_chip *chip = mtd->priv;
1228         struct mtd_ecc_stats stats;
1229         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1230         int sndcmd = 1;
1231         int ret = 0;
1232         uint32_t readlen = ops->len;
1233         uint32_t oobreadlen = ops->ooblen;
1234         uint8_t *bufpoi, *oob, *buf;
1235
1236         stats = mtd->ecc_stats;
1237
1238         chipnr = (int)(from >> chip->chip_shift);
1239         chip->select_chip(mtd, chipnr);
1240
1241         realpage = (int)(from >> chip->page_shift);
1242         page = realpage & chip->pagemask;
1243
1244         col = (int)(from & (mtd->writesize - 1));
1245
1246         buf = ops->datbuf;
1247         oob = ops->oobbuf;
1248
1249         while(1) {
1250                 bytes = min(mtd->writesize - col, readlen);
1251                 aligned = (bytes == mtd->writesize);
1252
1253                 /* Is the current page in the buffer ? */
1254                 if (realpage != chip->pagebuf || oob) {
1255                         bufpoi = aligned ? buf : chip->buffers->databuf;
1256
1257                         if (likely(sndcmd)) {
1258                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1259                                 sndcmd = 0;
1260                         }
1261
1262                         if(page <= (0xc000 >> chip->page_shift)) {
1263                                 is_nand_spl_read = 1;
1264                         }else{
1265                                 is_nand_spl_read = 0;
1266                         }
1267                         /* Now read the page into the buffer */
1268                         if (unlikely(ops->mode == MTD_OOB_RAW))
1269                                 ret = chip->ecc.read_page_raw(mtd, chip,
1270                                                 bufpoi, page);
1271                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1272                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1273                         else
1274                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1275                                                 page);
1276                         if (ret < 0)
1277                                 break;
1278
1279                         /* Transfer not aligned data */
1280                         if (!aligned) {
1281                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1282                                         chip->pagebuf = realpage;
1283                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1284                         }
1285
1286                         buf += bytes;
1287
1288                         if (unlikely(oob)) {
1289                                 /* Raw mode does data:oob:data:oob */
1290                                 if (ops->mode != MTD_OOB_RAW) {
1291                                         int toread = min(oobreadlen,
1292                                                 chip->ecc.layout->oobavail);
1293                                         if (toread) {
1294                                                 oob = nand_transfer_oob(chip,
1295                                                         oob, ops, toread);
1296                                                 oobreadlen -= toread;
1297                                         }
1298                                 } else
1299                                         buf = nand_transfer_oob(chip,
1300                                                 buf, ops, mtd->oobsize);
1301                         }
1302
1303                         if (!(chip->options & NAND_NO_READRDY)) {
1304                                 /*
1305                                  * Apply delay or wait for ready/busy pin. Do
1306                                  * this before the AUTOINCR check, so no
1307                                  * problems arise if a chip which does auto
1308                                  * increment is marked as NOAUTOINCR by the
1309                                  * board driver.
1310                                  */
1311                                 if (!chip->dev_ready)
1312                                         udelay(chip->chip_delay);
1313                                 else
1314                                         nand_wait_ready(mtd);
1315                         }
1316                 } else {
1317                         memcpy(buf, chip->buffers->databuf + col, bytes);
1318                         buf += bytes;
1319                 }
1320
1321                 readlen -= bytes;
1322
1323                 if (!readlen)
1324                         break;
1325
1326                 /* For subsequent reads align to page boundary. */
1327                 col = 0;
1328                 /* Increment page address */
1329                 realpage++;
1330
1331                 page = realpage & chip->pagemask;
1332                 /* Check, if we cross a chip boundary */
1333                 if (!page) {
1334                         chipnr++;
1335                         chip->select_chip(mtd, -1);
1336                         chip->select_chip(mtd, chipnr);
1337                 }
1338
1339                 /* Check, if the chip supports auto page increment
1340                  * or if we have hit a block boundary.
1341                  */
1342                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1343                         sndcmd = 1;
1344         }
1345
1346         ops->retlen = ops->len - (size_t) readlen;
1347         if (oob)
1348                 ops->oobretlen = ops->ooblen - oobreadlen;
1349
1350         if (ret)
1351                 return ret;
1352
1353         if (mtd->ecc_stats.failed - stats.failed)
1354                 return -EBADMSG;
1355
1356         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1357 }
1358
1359 /**
1360  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1361  * @mtd:        MTD device structure
1362  * @from:       offset to read from
1363  * @len:        number of bytes to read
1364  * @retlen:     pointer to variable to store the number of read bytes
1365  * @buf:        the databuffer to put data
1366  *
1367  * Get hold of the chip and call nand_do_read
1368  */
1369 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1370                      size_t *retlen, uint8_t *buf)
1371 {
1372         struct nand_chip *chip = mtd->priv;
1373         int ret;
1374
1375         /* Do not allow reads past end of device */
1376         if ((from + len) > mtd->size)
1377                 return -EINVAL;
1378         if (!len)
1379                 return 0;
1380
1381         nand_get_device(chip, mtd, FL_READING);
1382
1383         chip->ops.len = len;
1384         chip->ops.datbuf = buf;
1385         chip->ops.oobbuf = NULL;
1386
1387         ret = nand_do_read_ops(mtd, from, &chip->ops);
1388
1389         *retlen = chip->ops.retlen;
1390
1391         nand_release_device(mtd);
1392
1393         return ret;
1394 }
1395
1396 /**
1397  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1398  * @mtd:        mtd info structure
1399  * @chip:       nand chip info structure
1400  * @page:       page number to read
1401  * @sndcmd:     flag whether to issue read command or not
1402  */
1403 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1404                              int page, int sndcmd)
1405 {
1406         if (sndcmd) {
1407                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1408                 sndcmd = 0;
1409         }
1410         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1411         return sndcmd;
1412 }
1413
1414 /**
1415  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1416  *                          with syndromes
1417  * @mtd:        mtd info structure
1418  * @chip:       nand chip info structure
1419  * @page:       page number to read
1420  * @sndcmd:     flag whether to issue read command or not
1421  */
1422 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1423                                   int page, int sndcmd)
1424 {
1425         uint8_t *buf = chip->oob_poi;
1426         int length = mtd->oobsize;
1427         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1428         int eccsize = chip->ecc.size;
1429         uint8_t *bufpoi = buf;
1430         int i, toread, sndrnd = 0, pos;
1431
1432         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1433         for (i = 0; i < chip->ecc.steps; i++) {
1434                 if (sndrnd) {
1435                         pos = eccsize + i * (eccsize + chunk);
1436                         if (mtd->writesize > 512)
1437                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1438                         else
1439                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1440                 } else
1441                         sndrnd = 1;
1442                 toread = min_t(int, length, chunk);
1443                 chip->read_buf(mtd, bufpoi, toread);
1444                 bufpoi += toread;
1445                 length -= toread;
1446         }
1447         if (length > 0)
1448                 chip->read_buf(mtd, bufpoi, length);
1449
1450         return 1;
1451 }
1452
1453 /**
1454  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1455  * @mtd:        mtd info structure
1456  * @chip:       nand chip info structure
1457  * @page:       page number to write
1458  */
1459 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1460                               int page)
1461 {
1462         int status = 0;
1463         const uint8_t *buf = chip->oob_poi;
1464         int length = mtd->oobsize;
1465
1466         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1467         chip->write_buf(mtd, buf, length);
1468         /* Send command to program the OOB data */
1469         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1470
1471         status = chip->waitfunc(mtd, chip);
1472
1473         return status & NAND_STATUS_FAIL ? -EIO : 0;
1474 }
1475
1476 /**
1477  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1478  *                           with syndrome - only for large page flash !
1479  * @mtd:        mtd info structure
1480  * @chip:       nand chip info structure
1481  * @page:       page number to write
1482  */
1483 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1484                                    struct nand_chip *chip, int page)
1485 {
1486         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1487         int eccsize = chip->ecc.size, length = mtd->oobsize;
1488         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1489         const uint8_t *bufpoi = chip->oob_poi;
1490
1491         /*
1492          * data-ecc-data-ecc ... ecc-oob
1493          * or
1494          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1495          */
1496         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1497                 pos = steps * (eccsize + chunk);
1498                 steps = 0;
1499         } else
1500                 pos = eccsize;
1501
1502         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1503         for (i = 0; i < steps; i++) {
1504                 if (sndcmd) {
1505                         if (mtd->writesize <= 512) {
1506                                 uint32_t fill = 0xFFFFFFFF;
1507
1508                                 len = eccsize;
1509                                 while (len > 0) {
1510                                         int num = min_t(int, len, 4);
1511                                         chip->write_buf(mtd, (uint8_t *)&fill,
1512                                                         num);
1513                                         len -= num;
1514                                 }
1515                         } else {
1516                                 pos = eccsize + i * (eccsize + chunk);
1517                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1518                         }
1519                 } else
1520                         sndcmd = 1;
1521                 len = min_t(int, length, chunk);
1522                 chip->write_buf(mtd, bufpoi, len);
1523                 bufpoi += len;
1524                 length -= len;
1525         }
1526         if (length > 0)
1527                 chip->write_buf(mtd, bufpoi, length);
1528
1529         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1530         status = chip->waitfunc(mtd, chip);
1531
1532         return status & NAND_STATUS_FAIL ? -EIO : 0;
1533 }
1534
1535 /**
1536  * nand_do_read_oob - [Intern] NAND read out-of-band
1537  * @mtd:        MTD device structure
1538  * @from:       offset to read from
1539  * @ops:        oob operations description structure
1540  *
1541  * NAND read out-of-band data from the spare area
1542  */
1543 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1544                             struct mtd_oob_ops *ops)
1545 {
1546         int page, realpage, chipnr, sndcmd = 1;
1547         struct nand_chip *chip = mtd->priv;
1548         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1549         int readlen = ops->ooblen;
1550         int len;
1551         uint8_t *buf = ops->oobbuf;
1552
1553         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1554                   (unsigned long long)from, readlen);
1555
1556         if (ops->mode == MTD_OOB_AUTO)
1557                 len = chip->ecc.layout->oobavail;
1558         else
1559                 len = mtd->oobsize;
1560
1561         if (unlikely(ops->ooboffs >= len)) {
1562                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1563                           "Attempt to start read outside oob\n");
1564                 return -EINVAL;
1565         }
1566
1567         /* Do not allow reads past end of device */
1568         if (unlikely(from >= mtd->size ||
1569                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1570                                         (from >> chip->page_shift)) * len)) {
1571                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1572                           "Attempt read beyond end of device\n");
1573                 return -EINVAL;
1574         }
1575
1576         chipnr = (int)(from >> chip->chip_shift);
1577         chip->select_chip(mtd, chipnr);
1578
1579         /* Shift to get page */
1580         realpage = (int)(from >> chip->page_shift);
1581         page = realpage & chip->pagemask;
1582
1583         while(1) {
1584                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1585
1586                 len = min(len, readlen);
1587                 buf = nand_transfer_oob(chip, buf, ops, len);
1588
1589                 if (!(chip->options & NAND_NO_READRDY)) {
1590                         /*
1591                          * Apply delay or wait for ready/busy pin. Do this
1592                          * before the AUTOINCR check, so no problems arise if a
1593                          * chip which does auto increment is marked as
1594                          * NOAUTOINCR by the board driver.
1595                          */
1596                         if (!chip->dev_ready)
1597                                 udelay(chip->chip_delay);
1598                         else
1599                                 nand_wait_ready(mtd);
1600                 }
1601
1602                 readlen -= len;
1603                 if (!readlen)
1604                         break;
1605
1606                 /* Increment page address */
1607                 realpage++;
1608
1609                 page = realpage & chip->pagemask;
1610                 /* Check, if we cross a chip boundary */
1611                 if (!page) {
1612                         chipnr++;
1613                         chip->select_chip(mtd, -1);
1614                         chip->select_chip(mtd, chipnr);
1615                 }
1616
1617                 /* Check, if the chip supports auto page increment
1618                  * or if we have hit a block boundary.
1619                  */
1620                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1621                         sndcmd = 1;
1622         }
1623
1624         ops->oobretlen = ops->ooblen;
1625         return 0;
1626 }
1627
1628 /**
1629  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1630  * @mtd:        MTD device structure
1631  * @from:       offset to read from
1632  * @ops:        oob operation description structure
1633  *
1634  * NAND read data and/or out-of-band data
1635  */
1636 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1637                          struct mtd_oob_ops *ops)
1638 {
1639         struct nand_chip *chip = mtd->priv;
1640         int ret = -ENOTSUPP;
1641
1642         ops->retlen = 0;
1643
1644         /* Do not allow reads past end of device */
1645         if (ops->datbuf && (from + ops->len) > mtd->size) {
1646                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1647                           "Attempt read beyond end of device\n");
1648                 return -EINVAL;
1649         }
1650
1651         nand_get_device(chip, mtd, FL_READING);
1652
1653         switch(ops->mode) {
1654         case MTD_OOB_PLACE:
1655         case MTD_OOB_AUTO:
1656         case MTD_OOB_RAW:
1657                 break;
1658
1659         default:
1660                 goto out;
1661         }
1662
1663         if (!ops->datbuf)
1664                 ret = nand_do_read_oob(mtd, from, ops);
1665         else
1666                 ret = nand_do_read_ops(mtd, from, ops);
1667
1668  out:
1669         nand_release_device(mtd);
1670         return ret;
1671 }
1672
1673
1674 /**
1675  * nand_write_page_raw - [Intern] raw page write function
1676  * @mtd:        mtd info structure
1677  * @chip:       nand chip info structure
1678  * @buf:        data buffer
1679  *
1680  * Not for syndrome calculating ecc controllers, which use a special oob layout
1681  */
1682 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1683                                 const uint8_t *buf)
1684 {
1685         chip->write_buf(mtd, buf, mtd->writesize);
1686         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1687 }
1688
1689 /**
1690  * nand_write_page_raw_syndrome - [Intern] raw page write function
1691  * @mtd:        mtd info structure
1692  * @chip:       nand chip info structure
1693  * @buf:        data buffer
1694  *
1695  * We need a special oob layout and handling even when ECC isn't checked.
1696  */
1697 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1698                                 const uint8_t *buf)
1699 {
1700         int eccsize = chip->ecc.size;
1701         int eccbytes = chip->ecc.bytes;
1702         uint8_t *oob = chip->oob_poi;
1703         int steps, size;
1704
1705         for (steps = chip->ecc.steps; steps > 0; steps--) {
1706                 chip->write_buf(mtd, buf, eccsize);
1707                 buf += eccsize;
1708
1709                 if (chip->ecc.prepad) {
1710                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1711                         oob += chip->ecc.prepad;
1712                 }
1713
1714                 chip->read_buf(mtd, oob, eccbytes);
1715                 oob += eccbytes;
1716
1717                 if (chip->ecc.postpad) {
1718                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1719                         oob += chip->ecc.postpad;
1720                 }
1721         }
1722
1723         size = mtd->oobsize - (oob - chip->oob_poi);
1724         if (size)
1725                 chip->write_buf(mtd, oob, size);
1726 }
1727 /**
1728  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1729  * @mtd:        mtd info structure
1730  * @chip:       nand chip info structure
1731  * @buf:        data buffer
1732  */
1733 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1734                                   const uint8_t *buf)
1735 {
1736         int i, eccsize = chip->ecc.size;
1737         int eccbytes = chip->ecc.bytes;
1738         int eccsteps = chip->ecc.steps;
1739         uint8_t *ecc_calc = chip->buffers->ecccalc;
1740         const uint8_t *p = buf;
1741         uint32_t *eccpos = chip->ecc.layout->eccpos;
1742
1743         /* Software ecc calculation */
1744         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1745                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1746
1747         for (i = 0; i < chip->ecc.total; i++)
1748                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1749
1750         chip->ecc.write_page_raw(mtd, chip, buf);
1751 }
1752
1753 /**
1754  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1755  * @mtd:        mtd info structure
1756  * @chip:       nand chip info structure
1757  * @buf:        data buffer
1758  */
1759 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1760                                   const uint8_t *buf)
1761 {
1762         int i, eccsize = chip->ecc.size;
1763         int eccbytes = chip->ecc.bytes;
1764         int eccsteps = chip->ecc.steps;
1765         uint8_t *ecc_calc = chip->buffers->ecccalc;
1766         const uint8_t *p = buf;
1767         uint32_t *eccpos = chip->ecc.layout->eccpos;
1768         uint8_t ecclayouttemp;
1769
1770         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1771                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1772                 chip->write_buf(mtd, p, eccsize);
1773                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1774         }
1775
1776         for (i = 0; i < chip->ecc.total; i++)
1777                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1778
1779         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1780 #ifdef CONFIG_MTD_NAND_SPRD
1781         chip->nfc_wr_oob(mtd);
1782 #endif
1783 }
1784
1785 /**
1786  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1787  * @mtd:        mtd info structure
1788  * @chip:       nand chip info structure
1789  * @buf:        data buffer
1790  *
1791  * The hw generator calculates the error syndrome automatically. Therefor
1792  * we need a special oob layout and handling.
1793  */
1794 static void nand_write_page_syndrome(struct mtd_info *mtd,
1795                                     struct nand_chip *chip, const uint8_t *buf)
1796 {
1797         int i, eccsize = chip->ecc.size;
1798         int eccbytes = chip->ecc.bytes;
1799         int eccsteps = chip->ecc.steps;
1800         const uint8_t *p = buf;
1801         uint8_t *oob = chip->oob_poi;
1802
1803         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1804
1805                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1806                 chip->write_buf(mtd, p, eccsize);
1807
1808                 if (chip->ecc.prepad) {
1809                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1810                         oob += chip->ecc.prepad;
1811                 }
1812
1813                 chip->ecc.calculate(mtd, p, oob);
1814                 chip->write_buf(mtd, oob, eccbytes);
1815                 oob += eccbytes;
1816
1817                 if (chip->ecc.postpad) {
1818                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1819                         oob += chip->ecc.postpad;
1820                 }
1821         }
1822
1823         /* Calculate remaining oob bytes */
1824         i = mtd->oobsize - (oob - chip->oob_poi);
1825         if (i)
1826                 chip->write_buf(mtd, oob, i);
1827 }
1828
1829 /**
1830  * nand_write_page - [REPLACEABLE] write one page
1831  * @mtd:        MTD device structure
1832  * @chip:       NAND chip descriptor
1833  * @buf:        the data to write
1834  * @page:       page number to write
1835  * @cached:     cached programming
1836  * @raw:        use _raw version of write_page
1837  */
1838 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1839                            const uint8_t *buf, int page, int cached, int raw)
1840 {
1841         int status;
1842
1843         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1844         if (unlikely(raw))
1845                 chip->ecc.write_page_raw(mtd, chip, buf);
1846         else
1847                 chip->ecc.write_page(mtd, chip, buf);
1848         /*
1849          * Cached progamming disabled for now, Not sure if its worth the
1850          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1851          */
1852         cached = 0;
1853
1854         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1855
1856                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1857                 status = chip->waitfunc(mtd, chip);
1858                 /*
1859                  * See if operation failed and additional status checks are
1860                  * available
1861                  */
1862                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1863                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1864                                                page);
1865
1866                 if (status & NAND_STATUS_FAIL)
1867                         return -EIO;
1868         } else {
1869                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1870                 status = chip->waitfunc(mtd, chip);
1871         }
1872
1873 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1874         /* Send command to read back the data */
1875         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1876
1877         if (chip->verify_buf(mtd, buf, mtd->writesize))
1878                 return -EIO;
1879 #endif
1880         return 0;
1881 }
1882
1883 /**
1884  * nand_fill_oob - [Internal] Transfer client buffer to oob
1885  * @chip:       nand chip structure
1886  * @oob:        oob data buffer
1887  * @ops:        oob ops structure
1888  */
1889 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1890                                   struct mtd_oob_ops *ops)
1891 {
1892         size_t len = ops->ooblen;
1893
1894         switch(ops->mode) {
1895
1896         case MTD_OOB_PLACE:
1897         case MTD_OOB_RAW:
1898                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1899                 return oob + len;
1900
1901         case MTD_OOB_AUTO: {
1902                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1903                 uint32_t boffs = 0, woffs = ops->ooboffs;
1904                 size_t bytes = 0;
1905
1906                 for(; free->length && len; free++, len -= bytes) {
1907                         /* Write request not from offset 0 ? */
1908                         if (unlikely(woffs)) {
1909                                 if (woffs >= free->length) {
1910                                         woffs -= free->length;
1911                                         continue;
1912                                 }
1913                                 boffs = free->offset + woffs;
1914                                 bytes = min_t(size_t, len,
1915                                               (free->length - woffs));
1916                                 woffs = 0;
1917                         } else {
1918                                 bytes = min_t(size_t, len, free->length);
1919                                 boffs = free->offset;
1920                         }
1921                         memcpy(chip->oob_poi + boffs, oob, bytes);
1922                         oob += bytes;
1923                 }
1924                 return oob;
1925         }
1926         default:
1927                 BUG();
1928         }
1929         return NULL;
1930 }
1931
1932 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1933
1934 /**
1935  * nand_do_write_ops - [Internal] NAND write with ECC
1936  * @mtd:        MTD device structure
1937  * @to:         offset to write to
1938  * @ops:        oob operations description structure
1939  *
1940  * NAND write with ECC
1941  */
1942 int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1943                              struct mtd_oob_ops *ops)
1944 {
1945         int chipnr, realpage, page, blockmask, column;
1946         struct nand_chip *chip = mtd->priv;
1947         uint32_t writelen = ops->len;
1948         uint8_t *oob = ops->oobbuf;
1949         uint8_t *buf = ops->datbuf;
1950         int ret, subpage;
1951
1952         ops->retlen = 0;
1953         if (!writelen)
1954                 return 0;
1955
1956         column = to & (mtd->writesize - 1);
1957         subpage = column || (writelen & (mtd->writesize - 1));
1958
1959         if (subpage && oob)
1960                 return -EINVAL;
1961
1962         chipnr = (int)(to >> chip->chip_shift);
1963         chip->select_chip(mtd, chipnr);
1964
1965         /* Check, if it is write protected */
1966         if (nand_check_wp(mtd)) {
1967                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1968                 return -EIO;
1969         }
1970
1971         realpage = (int)(to >> chip->page_shift);
1972         page = realpage & chip->pagemask;
1973         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1974
1975         /* Invalidate the page cache, when we write to the cached page */
1976         if (to <= (chip->pagebuf << chip->page_shift) &&
1977             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1978                 chip->pagebuf = -1;
1979
1980         /* If we're not given explicit OOB data, let it be 0xFF */
1981         if (likely(!oob))
1982                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1983
1984         while(1) {
1985                 int bytes = mtd->writesize;
1986                 int cached = writelen > bytes && page != blockmask;
1987                 uint8_t *wbuf = buf;
1988
1989                 /* Partial page write ? */
1990                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1991                         cached = 0;
1992                         bytes = min_t(int, bytes - column, (int) writelen);
1993                         chip->pagebuf = -1;
1994                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1995                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1996                         wbuf = chip->buffers->databuf;
1997                 }
1998
1999                 if (unlikely(oob)){
2000                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2001                         oob = nand_fill_oob(chip, oob, ops);
2002                 }
2003
2004                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2005                                        (ops->mode == MTD_OOB_RAW));
2006                 if (ret)
2007                         break;
2008
2009                 writelen -= bytes;
2010                 if (!writelen)
2011                         break;
2012
2013                 column = 0;
2014                 buf += bytes;
2015                 realpage++;
2016
2017                 page = realpage & chip->pagemask;
2018                 /* Check, if we cross a chip boundary */
2019                 if (!page) {
2020                         chipnr++;
2021                         chip->select_chip(mtd, -1);
2022                         chip->select_chip(mtd, chipnr);
2023                 }
2024         }
2025
2026         ops->retlen = ops->len - writelen;
2027         if (unlikely(oob))
2028                 ops->oobretlen = ops->ooblen;
2029         return ret;
2030 }
2031
2032 /**
2033  * nand_write - [MTD Interface] NAND write with ECC
2034  * @mtd:        MTD device structure
2035  * @to:         offset to write to
2036  * @len:        number of bytes to write
2037  * @retlen:     pointer to variable to store the number of written bytes
2038  * @buf:        the data to write
2039  *
2040  * NAND write with ECC
2041  */
2042 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2043                           size_t *retlen, const uint8_t *buf)
2044 {
2045         struct nand_chip *chip = mtd->priv;
2046         int ret;
2047
2048         /* Do not allow reads past end of device */
2049         if ((to + len) > mtd->size)
2050                 return -EINVAL;
2051         if (!len)
2052                 return 0;
2053
2054         nand_get_device(chip, mtd, FL_WRITING);
2055
2056         chip->ops.len = len;
2057         chip->ops.datbuf = (uint8_t *)buf;
2058         chip->ops.oobbuf = NULL;
2059
2060         ret = nand_do_write_ops(mtd, to, &chip->ops);
2061
2062         *retlen = chip->ops.retlen;
2063
2064         nand_release_device(mtd);
2065
2066         return ret;
2067 }
2068
2069 /**
2070  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2071  * @mtd:        MTD device structure
2072  * @to:         offset to write to
2073  * @ops:        oob operation description structure
2074  *
2075  * NAND write out-of-band
2076  */
2077 int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2078                              struct mtd_oob_ops *ops)
2079 {
2080         int chipnr, page, status, len;
2081         struct nand_chip *chip = mtd->priv;
2082
2083         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2084                   (unsigned int)to, (int)ops->ooblen);
2085
2086         if (ops->mode == MTD_OOB_AUTO)
2087                 len = chip->ecc.layout->oobavail;
2088         else
2089                 len = mtd->oobsize;
2090
2091         /* Do not allow write past end of page */
2092         if ((ops->ooboffs + ops->ooblen) > len) {
2093                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2094                           "Attempt to write past end of page\n");
2095                 return -EINVAL;
2096         }
2097
2098         if (unlikely(ops->ooboffs >= len)) {
2099                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2100                           "Attempt to start write outside oob\n");
2101                 return -EINVAL;
2102         }
2103
2104         /* Do not allow reads past end of device */
2105         if (unlikely(to >= mtd->size ||
2106                      ops->ooboffs + ops->ooblen >
2107                         ((mtd->size >> chip->page_shift) -
2108                          (to >> chip->page_shift)) * len)) {
2109                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2110                           "Attempt write beyond end of device\n");
2111                 return -EINVAL;
2112         }
2113
2114         chipnr = (int)(to >> chip->chip_shift);
2115         chip->select_chip(mtd, chipnr);
2116
2117         /* Shift to get page */
2118         page = (int)(to >> chip->page_shift);
2119
2120         /*
2121          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2122          * of my DiskOnChip 2000 test units) will clear the whole data page too
2123          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2124          * it in the doc2000 driver in August 1999.  dwmw2.
2125          */
2126         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2127
2128         /* Check, if it is write protected */
2129         if (nand_check_wp(mtd))
2130                 return -EROFS;
2131
2132         /* Invalidate the page cache, if we write to the cached page */
2133         if (page == chip->pagebuf)
2134                 chip->pagebuf = -1;
2135
2136         memset(chip->oob_poi, 0xff, mtd->oobsize);
2137         nand_fill_oob(chip, ops->oobbuf, ops);
2138         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2139         memset(chip->oob_poi, 0xff, mtd->oobsize);
2140
2141         if (status)
2142                 return status;
2143
2144         ops->oobretlen = ops->ooblen;
2145
2146         return 0;
2147 }
2148
2149 /**
2150  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2151  * @mtd:        MTD device structure
2152  * @to:         offset to write to
2153  * @ops:        oob operation description structure
2154  */
2155 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2156                           struct mtd_oob_ops *ops)
2157 {
2158         struct nand_chip *chip = mtd->priv;
2159         int ret = -ENOTSUPP;
2160
2161         ops->retlen = 0;
2162
2163         /* Do not allow writes past end of device */
2164         if (ops->datbuf && (to + ops->len) > mtd->size) {
2165                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2166                           "Attempt read beyond end of device\n");
2167                 return -EINVAL;
2168         }
2169
2170         nand_get_device(chip, mtd, FL_WRITING);
2171
2172         switch(ops->mode) {
2173         case MTD_OOB_PLACE:
2174         case MTD_OOB_AUTO:
2175         case MTD_OOB_RAW:
2176                 break;
2177
2178         default:
2179                 goto out;
2180         }
2181
2182         if (!ops->datbuf)
2183                 ret = nand_do_write_oob(mtd, to, ops);
2184         else
2185                 ret = nand_do_write_ops(mtd, to, ops);
2186
2187  out:
2188         nand_release_device(mtd);
2189         return ret;
2190 }
2191
2192 /**
2193  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2194  * @mtd:        MTD device structure
2195  * @page:       the page address of the block which will be erased
2196  *
2197  * Standard erase command for NAND chips
2198  */
2199 static void single_erase_cmd(struct mtd_info *mtd, int page)
2200 {
2201         struct nand_chip *chip = mtd->priv;
2202         /* Send commands to erase a block */
2203         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2204         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2205 }
2206
2207 /**
2208  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2209  * @mtd:        MTD device structure
2210  * @page:       the page address of the block which will be erased
2211  *
2212  * AND multi block erase command function
2213  * Erase 4 consecutive blocks
2214  */
2215 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2216 {
2217         struct nand_chip *chip = mtd->priv;
2218         /* Send commands to erase a block */
2219         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2220         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2221         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2222         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2223         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2224 }
2225
2226 /**
2227  * nand_erase - [MTD Interface] erase block(s)
2228  * @mtd:        MTD device structure
2229  * @instr:      erase instruction
2230  *
2231  * Erase one ore more blocks
2232  */
2233 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2234 {
2235         return nand_erase_nand(mtd, instr, 0);
2236 }
2237
2238 #define BBT_PAGE_MASK   0xffffff3f
2239 /**
2240  * nand_erase_nand - [Internal] erase block(s)
2241  * @mtd:        MTD device structure
2242  * @instr:      erase instruction
2243  * @allowbbt:   allow erasing the bbt area
2244  *
2245  * Erase one ore more blocks
2246  */
2247 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2248                     int allowbbt)
2249 {
2250         int page, status, pages_per_block, ret, chipnr;
2251         struct nand_chip *chip = mtd->priv;
2252         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2253         unsigned int bbt_masked_page = 0xffffffff;
2254         loff_t len;
2255
2256         MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2257                  "len = %llu\n", (unsigned long long) instr->addr,
2258                  (unsigned long long) instr->len);
2259
2260         /* Start address must align on block boundary */
2261         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2262                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2263                 return -EINVAL;
2264         }
2265
2266         /* Length must align on block boundary */
2267         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2268                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2269                           "nand_erase: Length not block aligned\n");
2270                 return -EINVAL;
2271         }
2272
2273         /* Do not allow erase past end of device */
2274         if ((instr->len + instr->addr) > mtd->size) {
2275                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2276                           "nand_erase: Erase past end of device\n");
2277                 return -EINVAL;
2278         }
2279
2280         instr->fail_addr = 0xffffffff;
2281
2282         /* Grab the lock and see if the device is available */
2283         nand_get_device(chip, mtd, FL_ERASING);
2284
2285         /* Shift to get first page */
2286         page = (int)(instr->addr >> chip->page_shift);
2287         chipnr = (int)(instr->addr >> chip->chip_shift);
2288
2289         /* Calculate pages in each block */
2290         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2291
2292         /* Select the NAND device */
2293         chip->select_chip(mtd, chipnr);
2294
2295         /* Check, if it is write protected */
2296         if (nand_check_wp(mtd)) {
2297                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2298                           "nand_erase: Device is write protected!!!\n");
2299                 instr->state = MTD_ERASE_FAILED;
2300                 goto erase_exit;
2301         }
2302
2303         /*
2304          * If BBT requires refresh, set the BBT page mask to see if the BBT
2305          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2306          * can not be matched. This is also done when the bbt is actually
2307          * erased to avoid recusrsive updates
2308          */
2309         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2310                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2311
2312         /* Loop through the pages */
2313         len = instr->len;
2314
2315         instr->state = MTD_ERASING;
2316
2317         while (len) {
2318                 /*
2319                  * heck if we have a bad block, we do not erase bad blocks !
2320                  */
2321                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2322                                         chip->page_shift, 0, allowbbt)) {
2323                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2324                                "bad block at page 0x%08x\n", page);
2325                         instr->state = MTD_ERASE_FAILED;
2326                         goto erase_exit;
2327                 }
2328
2329                 /*
2330                  * Invalidate the page cache, if we erase the block which
2331                  * contains the current cached page
2332                  */
2333                 if (page <= chip->pagebuf && chip->pagebuf <
2334                     (page + pages_per_block))
2335                         chip->pagebuf = -1;
2336
2337                 chip->erase_cmd(mtd, page & chip->pagemask);
2338
2339                 status = chip->waitfunc(mtd, chip);
2340
2341                 /*
2342                  * See if operation failed and additional status checks are
2343                  * available
2344                  */
2345                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2346                         status = chip->errstat(mtd, chip, FL_ERASING,
2347                                                status, page);
2348
2349                 /* See if block erase succeeded */
2350                 if (status & NAND_STATUS_FAIL) {
2351                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2352                                   "Failed erase, page 0x%08x\n", page);
2353                         instr->state = MTD_ERASE_FAILED;
2354                         instr->fail_addr = ((loff_t)page << chip->page_shift);
2355                         goto erase_exit;
2356                 }
2357
2358                 /*
2359                  * If BBT requires refresh, set the BBT rewrite flag to the
2360                  * page being erased
2361                  */
2362                 if (bbt_masked_page != 0xffffffff &&
2363                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2364                         rewrite_bbt[chipnr] =
2365                                 ((loff_t)page << chip->page_shift);
2366
2367                 /* Increment page address and decrement length */
2368                 len -= (1 << chip->phys_erase_shift);
2369                 page += pages_per_block;
2370
2371                 /* Check, if we cross a chip boundary */
2372                 if (len && !(page & chip->pagemask)) {
2373                         chipnr++;
2374                         chip->select_chip(mtd, -1);
2375                         chip->select_chip(mtd, chipnr);
2376
2377                         /*
2378                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2379                          * page mask to see if this BBT should be rewritten
2380                          */
2381                         if (bbt_masked_page != 0xffffffff &&
2382                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2383                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2384                                         BBT_PAGE_MASK;
2385                 }
2386         }
2387         instr->state = MTD_ERASE_DONE;
2388
2389  erase_exit:
2390
2391         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2392
2393         /* Deselect and wake up anyone waiting on the device */
2394         nand_release_device(mtd);
2395
2396         /* Do call back function */
2397         if (!ret)
2398                 mtd_erase_callback(instr);
2399
2400         /*
2401          * If BBT requires refresh and erase was successful, rewrite any
2402          * selected bad block tables
2403          */
2404         if (bbt_masked_page == 0xffffffff || ret)
2405                 return ret;
2406
2407         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2408                 if (!rewrite_bbt[chipnr])
2409                         continue;
2410                 /* update the BBT for chip */
2411                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2412                           "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2413                           chip->bbt_td->pages[chipnr]);
2414                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2415         }
2416
2417         /* Return more or less happy */
2418         return ret;
2419 }
2420
2421 /**
2422  * nand_sync - [MTD Interface] sync
2423  * @mtd:        MTD device structure
2424  *
2425  * Sync is actually a wait for chip ready function
2426  */
2427 static void nand_sync(struct mtd_info *mtd)
2428 {
2429         struct nand_chip *chip = mtd->priv;
2430
2431         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2432
2433         /* Grab the lock and see if the device is available */
2434         nand_get_device(chip, mtd, FL_SYNCING);
2435         /* Release it and go back */
2436         nand_release_device(mtd);
2437 }
2438
2439 /**
2440  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2441  * @mtd:        MTD device structure
2442  * @offs:       offset relative to mtd start
2443  */
2444 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2445 {
2446         /* Check for invalid offset */
2447         if (offs > mtd->size)
2448                 return -EINVAL;
2449
2450         return nand_block_checkbad(mtd, offs, 1, 0);
2451 }
2452
2453 /**
2454  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2455  * @mtd:        MTD device structure
2456  * @ofs:        offset relative to mtd start
2457  */
2458 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2459 {
2460         struct nand_chip *chip = mtd->priv;
2461         int ret;
2462
2463         if ((ret = nand_block_isbad(mtd, ofs))) {
2464                 /* If it was bad already, return success and do nothing. */
2465                 if (ret > 0)
2466                         return 0;
2467                 return ret;
2468         }
2469
2470         return chip->block_markbad(mtd, ofs);
2471 }
2472
2473 /*
2474  * Set default functions
2475  */
2476 static void nand_set_defaults(struct nand_chip *chip, int busw)
2477 {
2478         /* check for proper chip_delay setup, set 20us if not */
2479         if (!chip->chip_delay)
2480                 chip->chip_delay = 20;
2481
2482         /* check, if a user supplied command function given */
2483         if (chip->cmdfunc == NULL)
2484                 chip->cmdfunc = nand_command;
2485
2486         /* check, if a user supplied wait function given */
2487         if (chip->waitfunc == NULL)
2488                 chip->waitfunc = nand_wait;
2489
2490         if (!chip->select_chip)
2491                 chip->select_chip = nand_select_chip;
2492         if (!chip->read_byte)
2493                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2494         if (!chip->read_word)
2495                 chip->read_word = nand_read_word;
2496         if (!chip->block_bad)
2497                 chip->block_bad = nand_block_bad;
2498         if (!chip->block_markbad)
2499                 chip->block_markbad = nand_default_block_markbad;
2500         if (!chip->write_buf)
2501                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2502         if (!chip->read_buf)
2503                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2504         if (!chip->verify_buf)
2505                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2506         if (!chip->scan_bbt)
2507                 chip->scan_bbt = nand_default_bbt;
2508         if (!chip->controller)
2509                 chip->controller = &chip->hwcontrol;
2510 }
2511
2512 /*
2513  * Get the flash and manufacturer id and lookup if the type is supported
2514  */
2515 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2516                                                   struct nand_chip *chip,
2517                                                   int busw, int *maf_id)
2518 {
2519         struct nand_flash_dev *type = NULL;
2520         int i, dev_id, maf_idx;
2521         int tmp_id, tmp_manf;
2522 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER)|| defined(CONFIG_SC8830) || defined(CONFIG_SC9630)
2523         u8 id_data[8];
2524 #endif
2525
2526 #ifdef CONFIG_MTD_NAND_SPRD
2527         unsigned long flash_id = 0;
2528 #endif
2529         /* Select the device */
2530         chip->select_chip(mtd, 0);
2531
2532 #if 1
2533         /*
2534          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2535          * after power-up
2536          */
2537         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2538 #endif
2539
2540         /* Send the command for reading device ID */
2541 #ifdef CONFIG_MTD_NAND_SPRD
2542         chip->cmdfunc(mtd, NAND_CMD_READID, -1, -1);
2543         flash_id = chip->nfc_readid(mtd);
2544
2545         /*Read manufacturer and device IDs */
2546         *maf_id = flash_id & 0xff;
2547         dev_id = (flash_id >> 8)&0xff;
2548 #else
2549         chip->cmdfunc(mtd, NAND_CMD_READID, 0x0, -1);
2550 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER) || defined(CONFIG_SC8830) ||   defined(CONFIG_SC9630)
2551         for (i = 0; i < 5; i++)
2552                 id_data[i] = chip->read_byte(mtd);
2553         /* Read manufacturer and device IDs */
2554         *maf_id = id_data[0];
2555         dev_id = id_data[1];
2556 #else
2557
2558         /* Read manufacturer and device IDs */
2559         *maf_id = chip->read_byte(mtd);
2560         dev_id = chip->read_byte(mtd);
2561 #endif
2562 #endif
2563
2564         /* Try again to make sure, as some systems the bus-hold or other
2565          * interface concerns can cause random data which looks like a
2566          * possibly credible NAND flash to appear. If the two results do
2567          * not match, ignore the device completely.
2568          */
2569
2570 #ifdef CONFIG_MTD_NAND_SPRD
2571         chip->cmdfunc(mtd, NAND_CMD_READID, -1, -1);
2572         flash_id = chip->nfc_readid(mtd);
2573
2574         /* Read manufacturer and device IDs*/
2575         tmp_manf = flash_id & 0xff;
2576         tmp_id = (flash_id >> 8) & 0xff;
2577 #else
2578         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2579
2580         /* Read manufacturer and device IDs */
2581
2582         tmp_manf = chip->read_byte(mtd);
2583         tmp_id = chip->read_byte(mtd);
2584 #endif
2585
2586         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2587                 printk(KERN_INFO "%s: second ID read did not match "
2588                        "%02x,%02x against %02x,%02x\n", __func__,
2589                        *maf_id, dev_id, tmp_manf, tmp_id);
2590                 return ERR_PTR(-ENODEV);
2591         }
2592 #if 1
2593         /* Lookup the flash id */
2594         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2595                 if (dev_id == nand_flash_ids[i].id) {
2596                         type =  &nand_flash_ids[i];
2597                         break;
2598                 }
2599         }
2600
2601         if (!type) {
2602                 /* supress warning if there is no nand */
2603                 if (*maf_id != 0x00 && *maf_id != 0xff &&
2604                     dev_id  != 0x00 && dev_id  != 0xff)
2605                         printk(KERN_INFO "%s: unknown NAND device: "
2606                                 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2607                                 __func__, *maf_id, dev_id);
2608                 return ERR_PTR(-ENODEV);
2609         }
2610
2611         if (!mtd->name)
2612                 mtd->name = type->name;
2613
2614         chip->chipsize = (uint64_t)type->chipsize << 20;
2615
2616         /* Newer devices have all the information in additional id bytes */
2617         if (!type->pagesize) {
2618                 int extid;
2619 #ifdef CONFIG_MTD_NAND_SPRD
2620                 /* The 3rd id byte holds MLC / multichip data */
2621                 chip->cellinfo = (flash_id >> 16) & 0xff;
2622                 /* The 4th id byte is the important one */
2623                 extid = (flash_id >> 24) & 0xff;
2624 #else
2625                 /* The 3rd id byte holds MLC / multichip data */
2626                 chip->cellinfo = chip->read_byte(mtd);
2627                 /* The 4th id byte is the important one */
2628                 extid = chip->read_byte(mtd);
2629 #endif
2630                 /* Calc pagesize */
2631                 mtd->writesize = 1024 << (extid & 0x3);
2632                 extid >>= 2;
2633                 /* Calc oobsize */
2634                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2635                 extid >>= 2;
2636                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2637                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2638                 extid >>= 2;
2639                 /* Get buswidth information */
2640                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2641
2642         } else {
2643                 /*
2644                  * Old devices have chip data hardcoded in the device id table
2645                  */
2646                 mtd->erasesize = type->erasesize;
2647                 mtd->writesize = type->pagesize;
2648                 mtd->oobsize = mtd->writesize / 32;
2649                 busw = type->options & NAND_BUSWIDTH_16;
2650         }
2651
2652         /* Try to identify manufacturer */
2653         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2654                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2655                         break;
2656         }
2657
2658         /*
2659          * Check, if buswidth is correct. Hardware drivers should set
2660          * chip correct !
2661          */
2662         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2663                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2664                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2665                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2666                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2667                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2668                        busw ? 16 : 8);
2669                 return ERR_PTR(-EINVAL);
2670         }
2671
2672         /* Calculate the address shift from the page size */
2673         chip->page_shift = ffs(mtd->writesize) - 1;
2674         /* Convert chipsize to number of pages per chip -1. */
2675         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2676
2677         chip->bbt_erase_shift = chip->phys_erase_shift =
2678                 ffs(mtd->erasesize) - 1;
2679         if (chip->chipsize & 0xffffffff)
2680                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2681         else
2682                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2683
2684         /* Set the bad block position */
2685         chip->badblockpos = mtd->writesize > 512 ?
2686                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2687
2688         /* Get chip options, preserve non chip based options */
2689         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2690         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2691
2692         /*
2693          * Set chip as a default. Board drivers can override it, if necessary
2694          */
2695         chip->options |= NAND_NO_AUTOINCR;
2696
2697         /* Check if chip is a not a samsung device. Do not clear the
2698          * options for chips which are not having an extended id.
2699          */
2700         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2701                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2702
2703         /* Check for AND chips with 4 page planes */
2704         if (chip->options & NAND_4PAGE_ARRAY)
2705                 chip->erase_cmd = multi_erase_cmd;
2706         else
2707                 chip->erase_cmd = single_erase_cmd;
2708
2709         /* Do not replace user supplied command function ! */
2710         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2711                 chip->cmdfunc = nand_command_lp;
2712
2713         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2714                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2715                   nand_manuf_ids[maf_idx].name, type->name);
2716 #endif
2717
2718 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER)|| defined(CONFIG_SC8830) || defined(CONFIG_SC9630)
2719         extern void nand_hardware_config(struct mtd_info *mtd, struct nand_chip*, u8[5]);
2720         nand_hardware_config(mtd, chip, id_data);
2721 #endif
2722
2723         return type;
2724 }
2725
2726 /**
2727  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2728  * @mtd:             MTD device structure
2729  * @maxchips:        Number of chips to scan for
2730  *
2731  * This is the first phase of the normal nand_scan() function. It
2732  * reads the flash ID and sets up MTD fields accordingly.
2733  *
2734  * The mtd->owner field must be set to the module of the caller.
2735  */
2736 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2737 {
2738         int i, busw, nand_maf_id;
2739         struct nand_chip *chip = mtd->priv;
2740         struct nand_flash_dev *type;
2741
2742         /* Get buswidth to select the correct functions */
2743         busw = chip->options & NAND_BUSWIDTH_16;
2744         /* Set the default functions */
2745         nand_set_defaults(chip, busw);
2746
2747         /* Read the flash type */
2748         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2749 #if 0
2750         i=0xfffffff;
2751         while(i--);
2752 #endif
2753         if (IS_ERR(type)) {
2754 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2755                 printk(KERN_WARNING "No NAND device found!!!\n");
2756 #endif
2757                 chip->select_chip(mtd, -1);
2758                 return PTR_ERR(type);
2759         }
2760
2761         /* Check for a chip array */
2762         for (i = 1; i < maxchips; i++) {
2763                 chip->select_chip(mtd, i);
2764                 /* See comment in nand_get_flash_type for reset */
2765                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2766                 /* Send the command for reading device ID */
2767                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2768                 /* Read manufacturer and device IDs */
2769                 if (nand_maf_id != chip->read_byte(mtd) ||
2770                     type->id != chip->read_byte(mtd))
2771                         break;
2772         }
2773 #ifdef DEBUG
2774         if (i > 1)
2775                 printk(KERN_INFO "%d NAND chips detected\n", i);
2776 #endif
2777
2778         /* Store the number of chips and calc total size for mtd */
2779         chip->numchips = i;
2780         mtd->size = i * chip->chipsize;
2781
2782         return 0;
2783 }
2784
2785
2786 /**
2787  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2788  * @mtd:            MTD device structure
2789  *
2790  * This is the second phase of the normal nand_scan() function. It
2791  * fills out all the uninitialized function pointers with the defaults
2792  * and scans for a bad block table if appropriate.
2793  */
2794 int nand_scan_tail(struct mtd_info *mtd)
2795 {
2796         int i;
2797         struct nand_chip *chip = mtd->priv;
2798
2799         if (!(chip->options & NAND_OWN_BUFFERS))
2800                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2801         if (!chip->buffers) {
2802                 return -ENOMEM;
2803         }
2804         /* Set the internal oob buffer location, just after the page data */
2805         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2806
2807         /*
2808          * If no default placement scheme is given, select an appropriate one
2809          */
2810         if (!chip->ecc.layout) {
2811                 switch (mtd->oobsize) {
2812                 case 8:
2813                         chip->ecc.layout = &nand_oob_8;
2814                         break;
2815                 case 16:
2816                         chip->ecc.layout = &nand_oob_16;
2817                         break;
2818                 case 64:
2819                         chip->ecc.layout = &nand_oob_64;
2820                         break;
2821                 case 128:
2822                         chip->ecc.layout = &nand_oob_128;
2823                         break;
2824                 default:
2825                         printf("No oob scheme defined for "
2826                                "oobsize %d\n", mtd->oobsize);
2827                 }
2828         }
2829
2830         if (!chip->write_page)
2831                 chip->write_page = nand_write_page;
2832
2833         /*
2834          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2835          * selected and we have 256 byte pagesize fallback to software ECC
2836          */
2837
2838         switch (chip->ecc.mode) {
2839         case NAND_ECC_HW_OOB_FIRST:
2840                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2841                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2842                      !chip->ecc.hwctl) {
2843                         printk(KERN_WARNING "No ECC functions supplied, "
2844                                "Hardware ECC not possible\n");
2845                         BUG();
2846                 }
2847                 if (!chip->ecc.read_page)
2848                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2849
2850         case NAND_ECC_HW:
2851                 /* Use standard hwecc read page function ? */
2852                 if (!chip->ecc.read_page)
2853                         chip->ecc.read_page = nand_read_page_hwecc;
2854                 if (!chip->ecc.write_page)
2855                         chip->ecc.write_page = nand_write_page_hwecc;
2856                 if (!chip->ecc.read_page_raw)
2857                         chip->ecc.read_page_raw = nand_read_page_raw;
2858                 if (!chip->ecc.write_page_raw)
2859                         chip->ecc.write_page_raw = nand_write_page_raw;
2860                 if (!chip->ecc.read_oob)
2861                         chip->ecc.read_oob = nand_read_oob_std;
2862                 if (!chip->ecc.write_oob)
2863                         chip->ecc.write_oob = nand_write_oob_std;
2864
2865         case NAND_ECC_HW_SYNDROME:
2866                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2867                      !chip->ecc.hwctl) &&
2868                     (!chip->ecc.read_page ||
2869                      chip->ecc.read_page == nand_read_page_hwecc ||
2870                      !chip->ecc.write_page ||
2871                      chip->ecc.write_page == nand_write_page_hwecc)) {
2872                         printk(KERN_WARNING "No ECC functions supplied, "
2873                                "Hardware ECC not possible\n");
2874                         BUG();
2875                 }
2876                 /* Use standard syndrome read/write page function ? */
2877                 if (!chip->ecc.read_page)
2878                         chip->ecc.read_page = nand_read_page_syndrome;
2879                 if (!chip->ecc.write_page)
2880                         chip->ecc.write_page = nand_write_page_syndrome;
2881                 if (!chip->ecc.read_page_raw)
2882                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2883                 if (!chip->ecc.write_page_raw)
2884                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2885                 if (!chip->ecc.read_oob)
2886                         chip->ecc.read_oob = nand_read_oob_syndrome;
2887                 if (!chip->ecc.write_oob)
2888                         chip->ecc.write_oob = nand_write_oob_syndrome;
2889
2890                 if (mtd->writesize >= chip->ecc.size)
2891                         break;
2892                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2893                        "%d byte page size, fallback to SW ECC\n",
2894                        chip->ecc.size, mtd->writesize);
2895                 chip->ecc.mode = NAND_ECC_SOFT;
2896
2897         case NAND_ECC_SOFT:
2898                 chip->ecc.calculate = nand_calculate_ecc;
2899                 chip->ecc.correct = nand_correct_data;
2900                 chip->ecc.read_page = nand_read_page_swecc;
2901                 chip->ecc.read_subpage = nand_read_subpage;
2902                 chip->ecc.write_page = nand_write_page_swecc;
2903                 chip->ecc.read_page_raw = nand_read_page_raw;
2904                 chip->ecc.write_page_raw = nand_write_page_raw;
2905                 chip->ecc.read_oob = nand_read_oob_std;
2906                 chip->ecc.write_oob = nand_write_oob_std;
2907                 chip->ecc.size = 256;
2908                 chip->ecc.bytes = 3;
2909                 break;
2910
2911         case NAND_ECC_NONE:
2912                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2913                        "This is not recommended !!\n");
2914                 chip->ecc.read_page = nand_read_page_raw;
2915                 chip->ecc.write_page = nand_write_page_raw;
2916                 chip->ecc.read_oob = nand_read_oob_std;
2917                 chip->ecc.read_page_raw = nand_read_page_raw;
2918                 chip->ecc.write_page_raw = nand_write_page_raw;
2919                 chip->ecc.write_oob = nand_write_oob_std;
2920                 chip->ecc.size = mtd->writesize;
2921                 chip->ecc.bytes = 0;
2922                 break;
2923
2924         default:
2925                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2926                        chip->ecc.mode);
2927                 BUG();
2928         }
2929
2930         /*
2931          * The number of bytes available for a client to place data into
2932          * the out of band area
2933          */
2934         chip->ecc.layout->oobavail = 0;
2935         for (i = 0; chip->ecc.layout->oobfree[i].length
2936                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2937                 chip->ecc.layout->oobavail +=
2938                         chip->ecc.layout->oobfree[i].length;
2939         mtd->oobavail = chip->ecc.layout->oobavail;
2940
2941         /*
2942          * Set the number of read / write steps for one page depending on ECC
2943          * mode
2944          */
2945         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2946         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2947                 printk(KERN_WARNING "Invalid ecc parameters\n");
2948                 BUG();
2949         }
2950         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2951
2952         /*
2953          * Allow subpage writes up to ecc.steps. Not possible for MLC
2954          * FLASH.
2955          */
2956         chip->options |= NAND_NO_SUBPAGE_WRITE;
2957         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2958             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2959                 switch(chip->ecc.steps) {
2960                 case 2:
2961                         mtd->subpage_sft = 1;
2962                         break;
2963                 case 4:
2964                 case 8:
2965                 case 16:
2966                         mtd->subpage_sft = 2;
2967                         break;
2968                 }
2969         }
2970         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2971
2972         /* Initialize state */
2973         chip->state = FL_READY;
2974
2975         /* De-select the device */
2976         chip->select_chip(mtd, -1);
2977
2978         /* Invalidate the pagebuffer reference */
2979         chip->pagebuf = -1;
2980
2981         /* Fill in remaining MTD driver data */
2982         mtd->type = MTD_NANDFLASH;
2983         mtd->flags = MTD_CAP_NANDFLASH;
2984         mtd->erase = nand_erase;
2985         mtd->point = NULL;
2986         mtd->unpoint = NULL;
2987         mtd->read = nand_read;
2988         mtd->write = nand_write;
2989         mtd->read_oob = nand_read_oob;
2990         mtd->write_oob = nand_write_oob;
2991         mtd->sync = nand_sync;
2992         mtd->lock = NULL;
2993         mtd->unlock = NULL;
2994         mtd->block_isbad = nand_block_isbad;
2995         mtd->block_markbad = nand_block_markbad;
2996
2997         /* propagate ecc.layout to mtd_info */
2998         mtd->ecclayout = chip->ecc.layout;
2999
3000         /* Check, if we should skip the bad block table scan */
3001         if (chip->options & NAND_SKIP_BBTSCAN)
3002                 chip->options |= NAND_BBT_SCANNED;
3003
3004         return 0;
3005 }
3006
3007 /**
3008  * nand_scan - [NAND Interface] Scan for the NAND device
3009  * @mtd:        MTD device structure
3010  * @maxchips:   Number of chips to scan for
3011  *
3012  * This fills out all the uninitialized function pointers
3013  * with the defaults.
3014  * The flash ID is read and the mtd/chip structures are
3015  * filled with the appropriate values.
3016  * The mtd->owner field must be set to the module of the caller
3017  *
3018  */
3019 int nand_scan(struct mtd_info *mtd, int maxchips)
3020 {
3021         int ret;
3022
3023         ret = nand_scan_ident(mtd, maxchips);
3024         if (!ret)
3025                 ret = nand_scan_tail(mtd);
3026         return ret;
3027 }
3028
3029 /**
3030  * nand_release - [NAND Interface] Free resources held by the NAND device
3031  * @mtd:        MTD device structure
3032 */
3033 void nand_release(struct mtd_info *mtd)
3034 {
3035         struct nand_chip *chip = mtd->priv;
3036
3037 #ifdef CONFIG_MTD_PARTITIONS
3038         /* Deregister partitions */
3039         del_mtd_partitions(mtd);
3040 #endif
3041
3042         /* Free bad block table memory */
3043         kfree(chip->bbt);
3044         if (!(chip->options & NAND_OWN_BUFFERS))
3045                 kfree(chip->buffers);
3046 }