board/spreadtrum/tshark2j2_3g/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27 void init_ldo_sleep_gr(void)
  28 {
  29         unsigned int reg_val;
  30 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
  31         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  32                 BITS_PWR_WR_PROT_VALUE(0x6e7f) |
  33                 0
  34         );
  35
  36         while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) != BIT_PWR_WR_PROT);
  37
  38         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  39                 //BIT_LDO_EMM_PD |
  40                 BIT_DCDC_TOPCLK6M_PD |
  41                 //BIT_DCDC_RF_PD |
  42                 //BIT_DCDC_GEN_PD |
  43                 //BIT_DCDC_MEM_PD |
  44                 //BIT_DCDC_ARM_PD |
  45                 //BIT_DCDC_CORE_PD |
  46                 //BIT_LDO_RF0_PD |
  47                 //BIT_LDO_EMMCCORE_PD |
  48                 //BIT_LDO_GEN1_PD |
  49                 //BIT_LDO_DCXO_PD |
  50                 //BIT_LDO_GEN0_PD |
  51                 //BIT_LDO_VDD25_PD |
  52                 //BIT_LDO_VDD28_PD |
  53                 //BIT_LDO_VDD18_PD |
  54                 //BIT_BG_PD |
  55                 0
  56         );
  57         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  58                 BITS_PWR_WR_PROT_VALUE(0x0000) |
  59                 0
  60         );
  61
  62         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  63                 BIT_LDO_LPREF_PD_SW |
  64                 BIT_DCDC_WPA_PD |
  65                 BIT_DCDC_CON_PD |
  66                 BIT_LDO_WIFIPA_PD |
  67                 BIT_LDO_SDCORE_PD |
  68                 BIT_LDO_USB_PD |
  69                 BIT_LDO_CAMMOT_PD |
  70                 BIT_LDO_CAMIO_PD |
  71                 BIT_LDO_CAMD_PD |
  72                 BIT_LDO_CAMA_PD |
  73                 BIT_LDO_SIM2_PD |
  74                 BIT_LDO_SIM1_PD |
  75                 BIT_LDO_SIM0_PD |
  76                 //BIT_LDO_SDIO_PD |
  77                 0
  78         );
  79
  80         reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD1);
  81         reg_val|= (1 << 11);
  82         ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD1,reg_val);
  83
  84         reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD2);
  85         reg_val|= (1 << 7);
  86         ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD2,reg_val);
  87
  88       //vddrf 1.5 -> 1.8v for 3532 bug fix
  89         ANA_REG_SET(ANA_REG_GLB_DCDC_RF_ADI, 0x120);
  90
  91         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  92                 BIT_SLP_IO_EN |
  93                 BIT_SLP_DCDCRF_PD_EN |
  94                 BIT_SLP_DCDCCON_PD_EN |
  95                 //BIT_SLP_DCDCGEN_PD_EN |
  96                 //BIT_SLP_DCDCWPA_PD_EN |
  97                 BIT_SLP_DCDCARM_PD_EN |
  98                 BIT_SLP_LDOVDD25_PD_EN |
  99                 BIT_SLP_LDORF0_PD_EN |
 100                 BIT_SLP_LDOEMMCCORE_PD_EN |
 101                 BIT_SLP_LDOGEN0_PD_EN |
 102                 BIT_SLP_LDODCXO_PD_EN |
 103                 BIT_SLP_LDOGEN1_PD_EN |
 104                 BIT_SLP_LDOWIFIPA_PD_EN |
 105                 //BIT_SLP_LDOVDD28_PD_EN |
 106                 //BIT_SLP_LDOVDD18_PD_EN |
 107                 0
 108         );
 109         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
 110                 BIT_SLP_LDO_PD_EN |
 111                 BIT_SLP_LDOLPREF_PD_EN |
 112                 BIT_SLP_LDOSDCORE_PD_EN |
 113                 BIT_SLP_LDOUSB_PD_EN |
 114                 BIT_SLP_LDOCAMMOT_PD_EN |
 115                 BIT_SLP_LDOCAMIO_PD_EN |
 116                 //BIT_SLP_LDOCAMD_PD_EN |
 117                 BIT_SLP_LDOCAMA_PD_EN |
 118                 //BIT_SLP_LDOSIM2_PD_EN |
 119                 //BIT_SLP_LDOSIM1_PD_EN |
 120                 //BIT_SLP_LDOSIM0_PD_EN |
 121                 BIT_SLP_LDOSDIO_PD_EN |
 122                 0
 123         );
 124         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 125                 //BIT_SLP_DCDCRF_LP_EN |
 126                 //BIT_SLP_DCDCCON_LP_EN |
 127                 BIT_SLP_DCDCCORE_LP_EN |
 128                 BIT_SLP_DCDCMEM_LP_EN |
 129                 //BIT_SLP_DCDCARM_LP_EN |
 130                 BIT_SLP_DCDCGEN_LP_EN |
 131                 //BIT_SLP_DCDCWPA_LP_EN |
 132                 //BIT_SLP_LDORF0_LP_EN |
 133                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 134                 //BIT_SLP_LDOGEN0_LP_EN |
 135                 //BIT_SLP_LDODCXO_LP_EN |
 136                 //BIT_SLP_LDOGEN1_LP_EN |
 137                 //BIT_SLP_LDOWIFIPA_LP_EN |
 138                 //BIT_SLP_LDOVDD28_LP_EN |
 139                 //BIT_SLP_LDOVDD18_LP_EN |
 140                 0
 141         );
 142         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 143                 //BIT_SLP_BG_LP_EN |
 144                 //BIT_LDOVDD25_LP_EN_SW |
 145                 //BIT_LDOSDCORE_LP_EN_SW |
 146                 //BIT_LDOUSB_LP_EN_SW |
 147                 //BIT_SLP_LDOVDD25_LP_EN |
 148                 //BIT_SLP_LDOSDCORE_LP_EN |
 149                 //BIT_SLP_LDOUSB_LP_EN |
 150                 //BIT_SLP_LDOCAMMOT_LP_EN |
 151                 //BIT_SLP_LDOCAMIO_LP_EN |
 152                 //BIT_SLP_LDOCAMD_LP_EN |
 153                 //BIT_SLP_LDOCAMA_LP_EN |
 154                 //BIT_SLP_LDOSIM2_LP_EN |
 155                 //BIT_SLP_LDOSIM1_LP_EN |
 156                 //BIT_SLP_LDOSIM0_LP_EN |
 157                 //BIT_SLP_LDOSDIO_LP_EN |
 158                 0
 159         );
 160         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 161                 //BIT_LDOCAMIO_LP_EN_SW |
 162                 //BIT_LDOCAMMOT_LP_EN_SW |
 163                 //BIT_LDOCAMD_LP_EN_SW |
 164                 //BIT_LDOCAMA_LP_EN_SW |
 165                 //BIT_LDOSIM2_LP_EN_SW |
 166                 //BIT_LDOSIM1_LP_EN_SW |
 167                 //BIT_LDOSIM0_LP_EN_SW |
 168                 //BIT_LDOSDIO_LP_EN_SW |
 169                 //BIT_LDORF0_LP_EN_SW |
 170                 //BIT_LDOEMMCCORE_LP_EN_SW |
 171                 //BIT_LDOGEN0_LP_EN_SW |
 172                 //BIT_LDODCXO_LP_EN_SW |
 173                 //BIT_LDOGEN1_LP_EN_SW |
 174                 //BIT_LDOWIFIPA_LP_EN_SW |
 175                 //BIT_LDOVDD28_LP_EN_SW |
 176                 //BIT_LDOVDD18_LP_EN_SW |
 177                 0
 178         );
 179         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 180                 BIT_SLP_XTLBUF_PD_EN |
 181                 BIT_XTL_EN |
 182                 BITS_XTL_WAIT(0x32) |
 183                 0
 184         );
 185
 186         /****************************************
 187         *   Following is CP LDO Sleep Control  *
 188         ****************************************/
 189         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 190                 BIT_LDO_XTL_EN |
 191                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 192                 //BIT_LDO_GEN0_XTL1_EN |
 193                 BIT_LDO_GEN0_XTL0_EN |
 194                 BIT_LDO_GEN1_EXT_XTL0_EN |
 195                 BIT_LDO_GEN1_XTL1_EN |
 196                 BIT_LDO_GEN1_XTL0_EN |
 197                 BIT_LDO_DCXO_EXT_XTL0_EN |
 198                 BIT_LDO_DCXO_XTL1_EN |
 199                 BIT_LDO_DCXO_XTL0_EN |
 200                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 201                 //BIT_LDO_VDD18_XTL1_EN |
 202                 //BIT_LDO_VDD18_XTL0_EN |
 203                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 204                 //BIT_LDO_VDD28_XTL1_EN |
 205                 //BIT_LDO_VDD28_XTL0_EN |
 206                 0
 207         );
 208         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 209                 BIT_LDO_RF0_EXT_XTL0_EN |
 210                 BIT_LDO_RF0_XTL1_EN |
 211                 BIT_LDO_RF0_XTL0_EN |
 212                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 213                 //BIT_LDO_WIFIPA_XTL1_EN |
 214                 //BIT_LDO_WIFIPA_XTL0_EN |
 215                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 216                 //BIT_LDO_SIM2_XTL1_EN |
 217                 //BIT_LDO_SIM2_XTL0_EN |
 218                 //BIT_LDO_SIM1_EXT_XTL0_EN |
 219                 //BIT_LDO_SIM1_XTL1_EN |
 220                 //BIT_LDO_SIM1_XTL0_EN |
 221                 //BIT_LDO_SIM0_EXT_XTL0_EN |
 222                 //BIT_LDO_SIM0_XTL1_EN |
 223                 //BIT_LDO_SIM0_XTL0_EN |
 224                 0
 225         );
 226         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 227                 BIT_LDO_VDD25_EXT_XTL0_EN |
 228                 BIT_LDO_VDD25_XTL1_EN |
 229                 BIT_LDO_VDD25_XTL0_EN |
 230                 BIT_DCDC_RF_EXT_XTL0_EN |
 231                 BIT_DCDC_RF_XTL1_EN |
 232                 BIT_DCDC_RF_XTL0_EN |
 233                 BIT_XO_EXT_XTL0_EN |
 234                 BIT_XO_XTL1_EN |
 235                 BIT_XO_XTL0_EN |
 236                 BIT_BG_EXT_XTL0_EN |
 237                 BIT_BG_XTL1_EN |
 238                 BIT_BG_XTL0_EN |
 239                 0
 240         );
 241         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 242                 BIT_DCDC_CON_EXT_XTL0_EN |
 243                 BIT_DCDC_CON_XTL1_EN |
 244                 BIT_DCDC_CON_XTL0_EN |
 245                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 246                 BIT_DCDC_WPA_XTL1_EN |
 247                 //BIT_DCDC_WPA_XTL0_EN |
 248                 BIT_DCDC_MEM_EXT_XTL0_EN |
 249                 BIT_DCDC_MEM_XTL1_EN |
 250                 BIT_DCDC_MEM_XTL0_EN |
 251                 BIT_DCDC_GEN_EXT_XTL0_EN |
 252                 BIT_DCDC_GEN_XTL1_EN |
 253                 BIT_DCDC_GEN_XTL0_EN |
 254                 BIT_DCDC_CORE_EXT_XTL0_EN |
 255                 BIT_DCDC_CORE_XTL1_EN |
 256                 BIT_DCDC_CORE_XTL0_EN |
 257                 0
 258         );
 259
 260         //bit4-5: 0x10. quick dischrg
 261         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_DISCHRG);
 262         reg_val |= (0x1 << 5);
 263         reg_val &= 0xFFFFFFEF;
 264         ANA_REG_SET(ANA_REG_GLB_DCDC_DISCHRG, reg_val);
 265
 266 #else
 267         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
 268                 //BIT_LDO_AVDD18_PD_RTCCLR |
 269                 BIT_DCDC_OTP_PD_RTCCLR |
 270                 //BIT_DCDC_WRF_PD_RTCCLR |
 271                 BIT_DCDC_GEN_PD_RTCCLR |
 272                 BIT_DCDC_MEM_PD_RTCCLR |
 273                 BIT_DCDC_ARM_PD_RTCCLR |
 274                 BIT_DCDC_CORE_PD_RTCCLR|
 275                 BIT_LDO_EMMCCORE_PD_RTCCLR |
 276                 BIT_LDO_EMMCIO_PD_RTCCLR |
 277                 BIT_LDO_RF2_PD_RTCCLR |
 278                 //BIT_LDO_RF1_PD_RTCCLR |
 279                 BIT_LDO_RF0_PD_RTCCLR |
 280                 BIT_LDO_VDD25_PD_RTCCLR |
 281                 BIT_LDO_VDD28_PD_RTCCLR |
 282                 BIT_LDO_VDD18_PD_RTCCLR |
 283                 BIT_BG_PD_RTCCLR |
 284                 0
 285         );
 286
 287         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
 288                 BIT_LDO_AVDD18_PD_RTCSET |
 289                 //BIT_DCDC_OTP_PD_RTCSET |
 290                 BIT_DCDC_WRF_PD_RTCSET |
 291                 //BIT_DCDC_GEN_PD_RTCSET |
 292                 //BIT_DCDC_MEM_PD_RTCSET |
 293                 //BIT_DCDC_ARM_PD_RTCSET |
 294                 //BIT_DCDC_CORE_PD_RTCSET|
 295                 //BIT_LDO_EMMCCORE_PD_RTCSET |
 296                 //BIT_LDO_EMMCIO_PD_RTCSET |
 297                 //BIT_LDO_RF2_PD_RTCSET |
 298                 BIT_LDO_RF1_PD_RTCSET |
 299                 //BIT_LDO_RF0_PD_RTCSET |
 300                 //BIT_LDO_VDD25_PD_RTCSET |
 301                 //BIT_LDO_VDD28_PD_RTCSET |
 302                 //BIT_LDO_VDD18_PD_RTCSET |
 303                 //BIT_BG_PD_RTCSET |
 304                 0
 305         );
 306
 307         /**********************************************
 308          *   Following is AP LDO A DIE Sleep Control  *
 309          *********************************************/
 310         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
 311                 BIT_SLP_IO_EN |
 312                 BIT_SLP_DCDC_OTP_PD_EN |
 313                 //BIT_SLP_DCDCGEN_PD_EN |
 314                 //BIT_SLP_DCDCWPA_PD_EN |
 315                 //BIT_SLP_DCDCWRF_PD_EN |
 316                 BIT_SLP_DCDCARM_PD_EN |
 317                 BIT_SLP_LDOEMMCCORE_PD_EN |
 318                 BIT_SLP_LDOEMMCIO_PD_EN |
 319                 BIT_SLP_LDORF2_PD_EN |
 320                 //BIT_SLP_LDORF1_PD_EN |
 321                 BIT_SLP_LDORF0_PD_EN |
 322                 BIT_SLP_LDOVDD25_PD_EN |
 323                 //BIT_SLP_LDOVDD28_PD_EN |
 324                 //BIT_SLP_LDOVDD18_PD_EN |
 325                 0
 326         );
 327
 328         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
 329                 BIT_SLP_LDO_PD_EN |
 330                 BIT_SLP_LDOLPREF_PD_EN |
 331                 BIT_SLP_LDOCLSG_PD_EN |
 332                 BIT_SLP_LDOUSB_PD_EN |
 333                 BIT_SLP_LDOCAMMOT_PD_EN |
 334                 BIT_SLP_LDOCAMIO_PD_EN |
 335                 BIT_SLP_LDOCAMD_PD_EN |
 336                 BIT_SLP_LDOCAMA_PD_EN |
 337                 //BIT_SLP_LDOSIM2_PD_EN |
 338                 //BIT_SLP_LDOSIM1_PD_EN |
 339                 //BIT_SLP_LDOSIM0_PD_EN |
 340                 BIT_SLP_LDOSD_PD_EN |
 341                 BIT_SLP_LDOAVDD18_PD_EN |
 342                 0
 343         );
 344
 345         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
 346                 //BIT_SLP_DCDC_BG_LP_EN |
 347                 //BIT_SLP_DCDCCORE_LP_EN |
 348                 //BIT_SLP_DCDCMEM_LP_EN |
 349                 //BIT_SLP_DCDCARM_LP_EN |
 350                 //BIT_SLP_DCDCGEN_LP_EN |
 351                 //BIT_SLP_DCDCWPA_LP_EN |
 352                 //BIT_SLP_DCDCWRF_LP_EN |
 353                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 354                 //BIT_SLP_LDOEMMCIO_LP_EN |
 355                 //BIT_SLP_LDORF2_LP_EN |
 356                 //BIT_SLP_LDORF1_LP_EN |
 357                 //BIT_SLP_LDORF0_LP_EN |
 358                 0
 359         );
 360
 361         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
 362                 //BIT_SLP_BG_LP_EN |
 363                 //BIT_SLP_LDOVDD25_LP_EN |
 364                 //BIT_SLP_LDOVDD28_LP_EN |
 365                 //BIT_SLP_LDOVDD18_LP_EN |
 366                 //BIT_SLP_LDOCLSG_LP_EN |
 367                 //BIT_SLP_LDOUSB_LP_EN |
 368                 //BIT_SLP_LDOCAMMOT_LP_EN |
 369                 //BIT_SLP_LDOCAMIO_LP_EN |
 370                 //BIT_SLP_LDOCAMD_LP_EN |
 371                 //BIT_SLP_LDOCAMA_LP_EN |
 372                 //BIT_SLP_LDOSIM2_LP_EN |
 373                 //BIT_SLP_LDOSIM1_LP_EN |
 374                 //BIT_SLP_LDOSIM0_LP_EN |
 375                 //BIT_SLP_LDOSD_LP_EN |
 376                 //BIT_SLP_LDOAVDD18_LP_EN |
 377                 0
 378         );
 379
 380         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 381                 BIT_SLP_XTLBUF_PD_EN |
 382                 BIT_XTL_EN |
 383                 BITS_XTL_WAIT(0x32)|
 384                 0
 385         );
 386
 387         ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
 388                 BIT_DDR2_BUF_PD_HW |
 389                 BITS_DDR2_BUF_S_DS(0x0) |
 390                 BITS_DDR2_BUF_CHNS_DS(0x0) |
 391                 //BIT_DDR2_BUF_PD |
 392                 BITS_DDR2_BUF_S(0x3) |
 393                 BITS_DDR2_BUF_CHNS(0x0) |
 394                 0
 395         );
 396
 397         /****************************************
 398         *   Following is CP LDO Sleep Control  *
 399         ****************************************/
 400
 401         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 402                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 403                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 404                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 405                 //BIT_LDO_VDD18_XTL2_EN     |
 406                 //BIT_LDO_VDD18_XTL1_EN     |
 407                 //BIT_LDO_VDD18_XTL0_EN     |
 408                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 409                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 410                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 411                 //BIT_LDO_VDD28_XTL2_EN     |
 412                 //BIT_LDO_VDD28_XTL1_EN     |
 413                 //BIT_LDO_VDD28_XTL0_EN     |
 414                 0
 415         );
 416
 417         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 418                 BIT_LDO_XTL_EN |
 419                 //BIT_LDO_RF1_EXT_XTL2_EN |
 420                 //BIT_LDO_RF1_EXT_XTL1_EN |
 421                 //BIT_LDO_RF1_EXT_XTL0_EN |
 422                 //BIT_LDO_RF1_XTL2_EN |
 423                 //BIT_LDO_RF1_XTL1_EN |
 424                 //BIT_LDO_RF1_XTL0_EN |
 425                 //BIT_LDO_RF0_EXT_XTL2_EN |
 426                 //BIT_LDO_RF0_EXT_XTL1_EN |
 427                 //BIT_LDO_RF0_EXT_XTL0_EN |
 428                 BIT_LDO_RF0_XTL2_EN |
 429                 BIT_LDO_RF0_XTL1_EN |
 430                 BIT_LDO_RF0_XTL0_EN |
 431                 0
 432         );
 433
 434         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 435                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 436                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 437                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 438                 BIT_LDO_VDD25_XTL2_EN |
 439                 BIT_LDO_VDD25_XTL1_EN |
 440                 BIT_LDO_VDD25_XTL0_EN |
 441                 //BIT_LDO_RF2_EXT_XTL2_EN |
 442                 //BIT_LDO_RF2_EXT_XTL1_EN |
 443                 //BIT_LDO_RF2_EXT_XTL0_EN |
 444                 BIT_LDO_RF2_XTL2_EN |
 445                 BIT_LDO_RF2_XTL1_EN |
 446                 BIT_LDO_RF2_XTL0_EN |
 447                 0
 448         );
 449
 450         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 451                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 452                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 453                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 454                 //BIT_LDO_AVDD18_XTL2_EN |
 455                 //BIT_LDO_AVDD18_XTL1_EN |
 456                 //BIT_LDO_AVDD18_XTL0_EN |
 457                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 458                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 459                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 460                 //BIT_LDO_SIM2_XTL2_EN |
 461                 //BIT_LDO_SIM2_XTL1_EN |
 462                 //BIT_LDO_SIM2_XTL0_EN |
 463                 0
 464         );
 465
 466         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 467                 //BIT_DCDC_BG_EXT_XTL2_EN |
 468                 //BIT_DCDC_BG_EXT_XTL1_EN |
 469                 //BIT_DCDC_BG_EXT_XTL0_EN |
 470                 BIT_DCDC_BG_XTL2_EN |
 471                 BIT_DCDC_BG_XTL1_EN |
 472                 BIT_DCDC_BG_XTL0_EN |
 473                 //BIT_BG_EXT_XTL2_EN |
 474                 //BIT_BG_EXT_XTL1_EN |
 475                 //BIT_BG_EXT_XTL0_EN |
 476                 //BIT_BG_XTL2_EN |
 477                 //BIT_BG_XTL1_EN |
 478                 //BIT_BG_XTL0_EN |
 479                 0
 480         );
 481
 482         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 483                 //BIT_DCDC_WRF_XTL2_EN |
 484                 //BIT_DCDC_WRF_XTL1_EN |
 485                 //BIT_DCDC_WRF_XTL0_EN |
 486                 BIT_DCDC_WPA_XTL2_EN |
 487                 //BIT_DCDC_WPA_XTL1_EN |
 488                 //BIT_DCDC_WPA_XTL0_EN |
 489                 BIT_DCDC_MEM_XTL2_EN |
 490                 BIT_DCDC_MEM_XTL1_EN |
 491                 BIT_DCDC_MEM_XTL0_EN |
 492                 BIT_DCDC_GEN_XTL2_EN |
 493                 BIT_DCDC_GEN_XTL1_EN |
 494                 BIT_DCDC_GEN_XTL0_EN |
 495                 BIT_DCDC_CORE_XTL2_EN |
 496                 BIT_DCDC_CORE_XTL1_EN |
 497                 BIT_DCDC_CORE_XTL0_EN |
 498                 0
 499         );
 500
 501         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 502                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 503                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 504                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 505                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 506                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 507                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 508                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 509                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 510                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 511                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 512                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 513                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 514                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 515                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 516                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 517                 0
 518         );
 519
 520 #endif
 521         /************************************************
 522         *   Following is AP/CP LDO D DIE Sleep Control   *
 523         *************************************************/
 524
 525         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 526                 BIT_XTL0_AP_SEL |
 527                 BIT_XTL0_CP0_SEL |
 528                 BIT_XTL0_CP1_SEL |
 529                 BIT_XTL0_CP2_SEL |
 530                 0
 531         );
 532
 533         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 534                 BIT_XTL1_AP_SEL |
 535                 BIT_XTL1_CP0_SEL |
 536                 BIT_XTL1_CP1_SEL |
 537                 BIT_XTL1_CP2_SEL |
 538                 0
 539         );
 540
 541         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 542                 //BIT_XTL2_AP_SEL |
 543                 //BIT_XTL2_CP0_SEL |
 544                 //BIT_XTL2_CP1_SEL |
 545                 BIT_XTL2_CP2_SEL |
 546                 0
 547         );
 548
 549         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 550                 BIT_XTLBUF0_CP2_SEL |
 551                 BIT_XTLBUF0_CP1_SEL |
 552                 BIT_XTLBUF0_CP0_SEL |
 553                 BIT_XTLBUF0_AP_SEL  |
 554                 0
 555         );
 556
 557         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 558                 BIT_XTLBUF1_CP2_SEL |
 559                 BIT_XTLBUF1_CP1_SEL |
 560                 BIT_XTLBUF1_CP0_SEL |
 561                 BIT_XTLBUF1_AP_SEL  |
 562                 0
 563         );
 564
 565         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 566                 //BIT_MPLL_REF_SEL |
 567                 //BIT_MPLL_CP2_SEL |
 568                 //BIT_MPLL_CP1_SEL |
 569                 //BIT_MPLL_CP0_SEL |
 570                 BIT_MPLL_AP_SEL  |
 571                 0
 572         );
 573
 574         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 575                 //BIT_DPLL_REF_SEL |
 576                 BIT_DPLL_CP2_SEL |
 577                 BIT_DPLL_CP1_SEL |
 578                 BIT_DPLL_CP0_SEL |
 579                 BIT_DPLL_AP_SEL  |
 580                 0
 581         );
 582         /*caution tdpll & wpll sel config in spl*/
 583         reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 584         reg_val &= ~0xF;
 585         reg_val |= (
 586                    BIT_TDPLL_CP2_SEL|
 587                    BIT_TDPLL_CP1_SEL|
 588                    BIT_TDPLL_CP0_SEL|
 589                    BIT_TDPLL_AP_SEL |
 590                    0);
 591         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
 592
 593         reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
 594         reg_val &= ~0xF;
 595         reg_val |= (
 596                    //BIT_WPLL_CP2_SEL|
 597                    //BIT_WPLL_CP1_SEL|
 598                    BIT_WPLL_CP0_SEL|
 599                    //BIT_WPLL_AP_SEL |
 600                    0);
 601         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
 602
 603         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 604                 //BIT_CPLL_REF_SEL |
 605                 BIT_CPLL_CP2_SEL |
 606                 //BIT_CPLL_CP1_SEL |
 607                 //BIT_CPLL_CP0_SEL |
 608                 //BIT_CPLL_AP_SEL  |
 609                 0
 610         );
 611
 612         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 613                 BIT_WIFIPLL1_REF_SEL |
 614                 BIT_WIFIPLL1_CP2_SEL |
 615                 //BIT_WIFIPLL1_CP1_SEL |
 616                 //BIT_WIFIPLL1_CP0_SEL |
 617                 //BIT_WIFIPLL1_AP_SEL |
 618                 0
 619         );
 620
 621         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 622                 BIT_WIFIPLL2_REF_SEL |
 623                 BIT_WIFIPLL2_CP2_SEL |
 624                 //BIT_WIFIPLL2_CP1_SEL |
 625                 //BIT_WIFIPLL2_CP0_SEL |
 626                 //BIT_WIFIPLL2_AP_SEL |
 627                 0
 628         );
 629
 630         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 631                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 632                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 633                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 634                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 635                 0
 636         );
 637
 638         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 639                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 640                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 641                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 642                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 643                 0
 644         );
 645
 646         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 647                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 648                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 649                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 650                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 651                 0
 652         );
 653
 654         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 655                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 656                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 657                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 658                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 659                 0
 660         );
 661
 662         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 663                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 664                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 665                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 666                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 667                 0
 668         );
 669
 670         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 671                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 672                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 673                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 674                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 675                 0
 676         );
 677
 678         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 679                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 680                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 681                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 682                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 683                 0
 684         );
 685
 686         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 687                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 688                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 689                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 690                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 691                 0
 692         );
 693
 694         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 695                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 696                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 697                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 698                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 699                 0
 700         );
 701
 702         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
 703                 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN        |
 704                 BITS_PD_DDR_PUBL_PWR_ON_DLY(8)          |
 705                 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0)      |
 706                 BITS_PD_DDR_PUBL_ISO_ON_DLY(6)          |
 707                 0
 708         );
 709
 710         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
 711                 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN         |
 712                 BITS_PD_DDR_PHY_PWR_ON_DLY(8)           |
 713                 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0)       |
 714                 BITS_PD_DDR_PHY_ISO_ON_DLY(6)           |
 715                 0
 716         );
 717
 718         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 719                 BITS_XTL1_WAIT_CNT(0x73)                |
 720                 BITS_XTL0_WAIT_CNT(0x73)                |
 721                 0
 722         );
 723
 724         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 725                 BITS_XTLBUF1_WAIT_CNT(7)                |
 726                 BITS_XTLBUF0_WAIT_CNT(7)                |
 727                 0
 728         );
 729
 730         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 731                 BITS_WPLL_WAIT_CNT(7)                   |
 732                 BITS_TDPLL_WAIT_CNT(7)                  |
 733                 BITS_DPLL_WAIT_CNT(7)                   |
 734                 BITS_MPLL_WAIT_CNT(7)                   |
 735                 0
 736         );
 737
 738         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 739                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 740                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 741                 BITS_CPLL_WAIT_CNT(7)                   |
 742                 0
 743         );
 744
 745         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 746                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 747                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 748                 0
 749         );
 750
 751         CHIP_REG_SET(REG_PMU_APB_PD_CODEC_TOP_CFG,
 752                 BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN            |
 753                 BITS_PD_CODEC_TOP_PWR_ON_DLY(8)            |
 754                 BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(0)        |
 755                 BITS_PD_CODEC_TOP_ISO_ON_DLY(4)            |
 756                 0
 757         );
 758
 759         /*chip service package init*/
 760         CSP_Init(0);
 761 }