board/spreadtrum/tizen_tm1/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27 void init_ldo_sleep_gr(void)
  28 {
  29         unsigned int reg_val;
  30 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
  31         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  32                 BITS_PWR_WR_PROT_VALUE(0x6e7f) |
  33                 0
  34         );
  35
  36         while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) != BIT_PWR_WR_PROT);
  37
  38         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  39                 //BIT_LDO_EMM_PD |
  40                 //BIT_DCDC_TOPCLK6M_PD |
  41                 //BIT_DCDC_RF_PD |
  42                 //BIT_DCDC_GEN_PD |
  43                 //BIT_DCDC_MEM_PD |
  44                 //BIT_DCDC_ARM_PD |
  45                 //BIT_DCDC_CORE_PD |
  46                 //BIT_LDO_RF0_PD |
  47                 //BIT_LDO_EMMCCORE_PD |
  48                 //BIT_LDO_GEN1_PD |
  49                 //BIT_LDO_DCXO_PD |
  50                 //BIT_LDO_GEN0_PD |
  51                 //BIT_LDO_VDD25_PD |
  52                 //BIT_LDO_VDD28_PD |
  53                 //BIT_LDO_VDD18_PD |
  54                 //BIT_BG_PD |
  55                 0
  56         );
  57
  58         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  59                 BITS_PWR_WR_PROT_VALUE(0x0000) |
  60                 0
  61         );
  62
  63         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  64                 BIT_LDO_LPREF_PD_SW |
  65                 BIT_DCDC_WPA_PD |
  66                 BIT_DCDC_CON_PD |
  67                 BIT_LDO_WIFIPA_PD |
  68                 BIT_LDO_SDCORE_PD |
  69                 BIT_LDO_USB_PD |
  70                 BIT_LDO_CAMMOT_PD |
  71                 BIT_LDO_CAMIO_PD |
  72                 BIT_LDO_CAMD_PD |
  73                 BIT_LDO_CAMA_PD |
  74                 BIT_LDO_SIM2_PD |
  75                 BIT_LDO_SIM1_PD |
  76                 BIT_LDO_SIM0_PD |
  77                 BIT_LDO_SDIO_PD |
  78                 0
  79         );
  80
  81         reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD1);
  82         reg_val|= (1 << 11);
  83         ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD1,reg_val);
  84
  85         reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD2);
  86         reg_val|= (1 << 7);
  87         ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD2,reg_val);
  88
  89       //vddrf 1.5 -> 1.8v for 3532 bug fix
  90         ANA_REG_SET(ANA_REG_GLB_DCDC_RF_ADI, 0x180);
  91
  92         //vddsdio 3.3v
  93         ANA_REG_SET(ANA_REG_GLB_LDO_V_CTRL4, 0x3CD2);
  94
  95         /* 850/900 swtich module, need open kpled. */
  96         ANA_REG_SET(ANA_REG_GLB_KPLED_CTRL, 0xCA0);
  97
  98         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  99                 BIT_SLP_IO_EN |
 100                 BIT_SLP_DCDCRF_PD_EN |
 101                 BIT_SLP_DCDCCON_PD_EN |
 102                 //BIT_SLP_DCDCGEN_PD_EN |
 103                 //BIT_SLP_DCDCWPA_PD_EN |
 104                 BIT_SLP_DCDCARM_PD_EN |
 105                 BIT_SLP_LDOVDD25_PD_EN |
 106                 BIT_SLP_LDORF0_PD_EN |
 107                 BIT_SLP_LDOEMMCCORE_PD_EN |
 108                 BIT_SLP_LDOGEN0_PD_EN |
 109                 BIT_SLP_LDODCXO_PD_EN |
 110                 BIT_SLP_LDOGEN1_PD_EN |
 111                 BIT_SLP_LDOWIFIPA_PD_EN |
 112                 //BIT_SLP_LDOVDD28_PD_EN |
 113                 //BIT_SLP_LDOVDD18_PD_EN |
 114                 0
 115         );
 116         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
 117                 BIT_SLP_LDO_PD_EN |
 118                 BIT_SLP_LDOLPREF_PD_EN |
 119                 BIT_SLP_LDOSDCORE_PD_EN |
 120                 BIT_SLP_LDOUSB_PD_EN |
 121                 BIT_SLP_LDOCAMMOT_PD_EN |
 122                 //BIT_SLP_LDOCAMIO_PD_EN |
 123                 BIT_SLP_LDOCAMD_PD_EN |
 124                 BIT_SLP_LDOCAMA_PD_EN |
 125                 //BIT_SLP_LDOSIM2_PD_EN |
 126                 //BIT_SLP_LDOSIM1_PD_EN |
 127                 //BIT_SLP_LDOSIM0_PD_EN |
 128                 BIT_SLP_LDOSDIO_PD_EN |
 129                 0
 130         );
 131         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 132                 //BIT_SLP_DCDCRF_LP_EN |
 133                 //BIT_SLP_DCDCCON_LP_EN |
 134                 BIT_SLP_DCDCCORE_LP_EN |
 135                 BIT_SLP_DCDCMEM_LP_EN |
 136                 //BIT_SLP_DCDCARM_LP_EN |
 137                 BIT_SLP_DCDCGEN_LP_EN |
 138                 //BIT_SLP_DCDCWPA_LP_EN |
 139                 //BIT_SLP_LDORF0_LP_EN |
 140                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 141                 //BIT_SLP_LDOGEN0_LP_EN |
 142                 //BIT_SLP_LDODCXO_LP_EN |
 143                 //BIT_SLP_LDOGEN1_LP_EN |
 144                 //BIT_SLP_LDOWIFIPA_LP_EN |
 145                 //BIT_SLP_LDOVDD28_LP_EN |
 146                 //BIT_SLP_LDOVDD18_LP_EN |
 147                 0
 148         );
 149         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 150                 //BIT_SLP_BG_LP_EN |
 151                 //BIT_LDOVDD25_LP_EN_SW |
 152                 //BIT_LDOSDCORE_LP_EN_SW |
 153                 //BIT_LDOUSB_LP_EN_SW |
 154                 //BIT_SLP_LDOVDD25_LP_EN |
 155                 //BIT_SLP_LDOSDCORE_LP_EN |
 156                 //BIT_SLP_LDOUSB_LP_EN |
 157                 //BIT_SLP_LDOCAMMOT_LP_EN |
 158                 //BIT_SLP_LDOCAMIO_LP_EN |
 159                 //BIT_SLP_LDOCAMD_LP_EN |
 160                 //BIT_SLP_LDOCAMA_LP_EN |
 161                 //BIT_SLP_LDOSIM2_LP_EN |
 162                 //BIT_SLP_LDOSIM1_LP_EN |
 163                 //BIT_SLP_LDOSIM0_LP_EN |
 164                 //BIT_SLP_LDOSDIO_LP_EN |
 165                 0
 166         );
 167         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 168                 //BIT_LDOCAMIO_LP_EN_SW |
 169                 //BIT_LDOCAMMOT_LP_EN_SW |
 170                 //BIT_LDOCAMD_LP_EN_SW |
 171                 //BIT_LDOCAMA_LP_EN_SW |
 172                 //BIT_LDOSIM2_LP_EN_SW |
 173                 //BIT_LDOSIM1_LP_EN_SW |
 174                 //BIT_LDOSIM0_LP_EN_SW |
 175                 //BIT_LDOSDIO_LP_EN_SW |
 176                 //BIT_LDORF0_LP_EN_SW |
 177                 //BIT_LDOEMMCCORE_LP_EN_SW |
 178                 //BIT_LDOGEN0_LP_EN_SW |
 179                 //BIT_LDODCXO_LP_EN_SW |
 180                 //BIT_LDOGEN1_LP_EN_SW |
 181                 //BIT_LDOWIFIPA_LP_EN_SW |
 182                 //BIT_LDOVDD28_LP_EN_SW |
 183                 //BIT_LDOVDD18_LP_EN_SW |
 184                 0
 185         );
 186         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 187                 BIT_SLP_XTLBUF_PD_EN |
 188                 BIT_XTL_EN |
 189                 BITS_XTL_WAIT(0x32) |
 190                 0
 191         );
 192
 193         /****************************************
 194         *   Following is CP LDO Sleep Control  *
 195         ****************************************/
 196         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 197                 BIT_LDO_XTL_EN |
 198                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 199                 //BIT_LDO_GEN0_XTL1_EN |
 200                 BIT_LDO_GEN0_XTL0_EN |
 201                 BIT_LDO_GEN1_EXT_XTL0_EN |
 202                 BIT_LDO_GEN1_XTL1_EN |
 203                 BIT_LDO_GEN1_XTL0_EN |
 204                 BIT_LDO_DCXO_EXT_XTL0_EN |
 205                 BIT_LDO_DCXO_XTL1_EN |
 206                 BIT_LDO_DCXO_XTL0_EN |
 207                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 208                 //BIT_LDO_VDD18_XTL1_EN |
 209                 //BIT_LDO_VDD18_XTL0_EN |
 210                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 211                 //BIT_LDO_VDD28_XTL1_EN |
 212                 //BIT_LDO_VDD28_XTL0_EN |
 213                 0
 214         );
 215         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 216                 BIT_LDO_RF0_EXT_XTL0_EN |
 217                 BIT_LDO_RF0_XTL1_EN |
 218                 BIT_LDO_RF0_XTL0_EN |
 219                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 220                 //BIT_LDO_WIFIPA_XTL1_EN |
 221                 //BIT_LDO_WIFIPA_XTL0_EN |
 222                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 223                 //BIT_LDO_SIM2_XTL1_EN |
 224                 //BIT_LDO_SIM2_XTL0_EN |
 225                 //BIT_LDO_SIM1_EXT_XTL0_EN |
 226                 //BIT_LDO_SIM1_XTL1_EN |
 227                 //BIT_LDO_SIM1_XTL0_EN |
 228                 //BIT_LDO_SIM0_EXT_XTL0_EN |
 229                 //BIT_LDO_SIM0_XTL1_EN |
 230                 //BIT_LDO_SIM0_XTL0_EN |
 231                 0
 232         );
 233         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 234                 BIT_LDO_VDD25_EXT_XTL0_EN |
 235                 BIT_LDO_VDD25_XTL1_EN |
 236                 BIT_LDO_VDD25_XTL0_EN |
 237                 BIT_DCDC_RF_EXT_XTL0_EN |
 238                 BIT_DCDC_RF_XTL1_EN |
 239                 BIT_DCDC_RF_XTL0_EN |
 240                 BIT_XO_EXT_XTL0_EN |
 241                 BIT_XO_XTL1_EN |
 242                 BIT_XO_XTL0_EN |
 243                 BIT_BG_EXT_XTL0_EN |
 244                 BIT_BG_XTL1_EN |
 245                 BIT_BG_XTL0_EN |
 246                 0
 247         );
 248         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 249                 BIT_DCDC_CON_EXT_XTL0_EN |
 250                 BIT_DCDC_CON_XTL1_EN |
 251                 BIT_DCDC_CON_XTL0_EN |
 252                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 253                 BIT_DCDC_WPA_XTL1_EN |
 254                 //BIT_DCDC_WPA_XTL0_EN |
 255                 BIT_DCDC_MEM_EXT_XTL0_EN |
 256                 BIT_DCDC_MEM_XTL1_EN |
 257                 BIT_DCDC_MEM_XTL0_EN |
 258                 BIT_DCDC_GEN_EXT_XTL0_EN |
 259                 BIT_DCDC_GEN_XTL1_EN |
 260                 BIT_DCDC_GEN_XTL0_EN |
 261                 BIT_DCDC_CORE_EXT_XTL0_EN |
 262                 BIT_DCDC_CORE_XTL1_EN |
 263                 BIT_DCDC_CORE_XTL0_EN |
 264                 0
 265         );
 266
 267         //bit4-5: 0x10. quick dischrg
 268         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_DISCHRG);
 269         reg_val |= (0x1 << 5);
 270         reg_val &= 0xFFFFFFEF;
 271         ANA_REG_SET(ANA_REG_GLB_DCDC_DISCHRG, reg_val);
 272
 273 #else
 274         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
 275                 //BIT_LDO_AVDD18_PD_RTCCLR |
 276                 BIT_DCDC_OTP_PD_RTCCLR |
 277                 //BIT_DCDC_WRF_PD_RTCCLR |
 278                 BIT_DCDC_GEN_PD_RTCCLR |
 279                 BIT_DCDC_MEM_PD_RTCCLR |
 280                 BIT_DCDC_ARM_PD_RTCCLR |
 281                 BIT_DCDC_CORE_PD_RTCCLR|
 282                 BIT_LDO_EMMCCORE_PD_RTCCLR |
 283                 BIT_LDO_EMMCIO_PD_RTCCLR |
 284                 BIT_LDO_RF2_PD_RTCCLR |
 285                 //BIT_LDO_RF1_PD_RTCCLR |
 286                 BIT_LDO_RF0_PD_RTCCLR |
 287                 BIT_LDO_VDD25_PD_RTCCLR |
 288                 BIT_LDO_VDD28_PD_RTCCLR |
 289                 BIT_LDO_VDD18_PD_RTCCLR |
 290                 BIT_BG_PD_RTCCLR |
 291                 0
 292         );
 293
 294         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
 295                 BIT_LDO_AVDD18_PD_RTCSET |
 296                 //BIT_DCDC_OTP_PD_RTCSET |
 297                 BIT_DCDC_WRF_PD_RTCSET |
 298                 //BIT_DCDC_GEN_PD_RTCSET |
 299                 //BIT_DCDC_MEM_PD_RTCSET |
 300                 //BIT_DCDC_ARM_PD_RTCSET |
 301                 //BIT_DCDC_CORE_PD_RTCSET|
 302                 //BIT_LDO_EMMCCORE_PD_RTCSET |
 303                 //BIT_LDO_EMMCIO_PD_RTCSET |
 304                 //BIT_LDO_RF2_PD_RTCSET |
 305                 BIT_LDO_RF1_PD_RTCSET |
 306                 //BIT_LDO_RF0_PD_RTCSET |
 307                 //BIT_LDO_VDD25_PD_RTCSET |
 308                 //BIT_LDO_VDD28_PD_RTCSET |
 309                 //BIT_LDO_VDD18_PD_RTCSET |
 310                 //BIT_BG_PD_RTCSET |
 311                 0
 312         );
 313
 314         /**********************************************
 315          *   Following is AP LDO A DIE Sleep Control  *
 316          *********************************************/
 317         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
 318                 BIT_SLP_IO_EN |
 319                 BIT_SLP_DCDC_OTP_PD_EN |
 320                 //BIT_SLP_DCDCGEN_PD_EN |
 321                 //BIT_SLP_DCDCWPA_PD_EN |
 322                 //BIT_SLP_DCDCWRF_PD_EN |
 323                 BIT_SLP_DCDCARM_PD_EN |
 324                 BIT_SLP_LDOEMMCCORE_PD_EN |
 325                 BIT_SLP_LDOEMMCIO_PD_EN |
 326                 BIT_SLP_LDORF2_PD_EN |
 327                 //BIT_SLP_LDORF1_PD_EN |
 328                 BIT_SLP_LDORF0_PD_EN |
 329                 BIT_SLP_LDOVDD25_PD_EN |
 330                 //BIT_SLP_LDOVDD28_PD_EN |
 331                 //BIT_SLP_LDOVDD18_PD_EN |
 332                 0
 333         );
 334
 335         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
 336                 BIT_SLP_LDO_PD_EN |
 337                 BIT_SLP_LDOLPREF_PD_EN |
 338                 BIT_SLP_LDOCLSG_PD_EN |
 339                 BIT_SLP_LDOUSB_PD_EN |
 340                 BIT_SLP_LDOCAMMOT_PD_EN |
 341                 BIT_SLP_LDOCAMIO_PD_EN |
 342                 //BIT_SLP_LDOCAMD_PD_EN |
 343                 BIT_SLP_LDOCAMA_PD_EN |
 344                 //BIT_SLP_LDOSIM2_PD_EN |
 345                 //BIT_SLP_LDOSIM1_PD_EN |
 346                 //BIT_SLP_LDOSIM0_PD_EN |
 347                 BIT_SLP_LDOSD_PD_EN |
 348                 BIT_SLP_LDOAVDD18_PD_EN |
 349                 0
 350         );
 351
 352         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
 353                 //BIT_SLP_DCDC_BG_LP_EN |
 354                 //BIT_SLP_DCDCCORE_LP_EN |
 355                 //BIT_SLP_DCDCMEM_LP_EN |
 356                 //BIT_SLP_DCDCARM_LP_EN |
 357                 //BIT_SLP_DCDCGEN_LP_EN |
 358                 //BIT_SLP_DCDCWPA_LP_EN |
 359                 //BIT_SLP_DCDCWRF_LP_EN |
 360                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 361                 //BIT_SLP_LDOEMMCIO_LP_EN |
 362                 //BIT_SLP_LDORF2_LP_EN |
 363                 //BIT_SLP_LDORF1_LP_EN |
 364                 //BIT_SLP_LDORF0_LP_EN |
 365                 0
 366         );
 367
 368         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
 369                 //BIT_SLP_BG_LP_EN |
 370                 //BIT_SLP_LDOVDD25_LP_EN |
 371                 //BIT_SLP_LDOVDD28_LP_EN |
 372                 //BIT_SLP_LDOVDD18_LP_EN |
 373                 //BIT_SLP_LDOCLSG_LP_EN |
 374                 //BIT_SLP_LDOUSB_LP_EN |
 375                 //BIT_SLP_LDOCAMMOT_LP_EN |
 376                 //BIT_SLP_LDOCAMIO_LP_EN |
 377                 //BIT_SLP_LDOCAMD_LP_EN |
 378                 //BIT_SLP_LDOCAMA_LP_EN |
 379                 //BIT_SLP_LDOSIM2_LP_EN |
 380                 //BIT_SLP_LDOSIM1_LP_EN |
 381                 //BIT_SLP_LDOSIM0_LP_EN |
 382                 //BIT_SLP_LDOSD_LP_EN |
 383                 //BIT_SLP_LDOAVDD18_LP_EN |
 384                 0
 385         );
 386
 387         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 388                 BIT_SLP_XTLBUF_PD_EN |
 389                 BIT_XTL_EN |
 390                 BITS_XTL_WAIT(0x32)|
 391                 0
 392         );
 393
 394         ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
 395                 BIT_DDR2_BUF_PD_HW |
 396                 BITS_DDR2_BUF_S_DS(0x0) |
 397                 BITS_DDR2_BUF_CHNS_DS(0x0) |
 398                 //BIT_DDR2_BUF_PD |
 399                 BITS_DDR2_BUF_S(0x3) |
 400                 BITS_DDR2_BUF_CHNS(0x0) |
 401                 0
 402         );
 403
 404         /****************************************
 405         *   Following is CP LDO Sleep Control  *
 406         ****************************************/
 407
 408         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 409                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 410                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 411                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 412                 //BIT_LDO_VDD18_XTL2_EN     |
 413                 //BIT_LDO_VDD18_XTL1_EN     |
 414                 //BIT_LDO_VDD18_XTL0_EN     |
 415                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 416                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 417                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 418                 //BIT_LDO_VDD28_XTL2_EN     |
 419                 //BIT_LDO_VDD28_XTL1_EN     |
 420                 //BIT_LDO_VDD28_XTL0_EN     |
 421                 0
 422         );
 423
 424         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 425                 BIT_LDO_XTL_EN |
 426                 //BIT_LDO_RF1_EXT_XTL2_EN |
 427                 //BIT_LDO_RF1_EXT_XTL1_EN |
 428                 //BIT_LDO_RF1_EXT_XTL0_EN |
 429                 //BIT_LDO_RF1_XTL2_EN |
 430                 //BIT_LDO_RF1_XTL1_EN |
 431                 //BIT_LDO_RF1_XTL0_EN |
 432                 //BIT_LDO_RF0_EXT_XTL2_EN |
 433                 //BIT_LDO_RF0_EXT_XTL1_EN |
 434                 //BIT_LDO_RF0_EXT_XTL0_EN |
 435                 BIT_LDO_RF0_XTL2_EN |
 436                 BIT_LDO_RF0_XTL1_EN |
 437                 BIT_LDO_RF0_XTL0_EN |
 438                 0
 439         );
 440
 441         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 442                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 443                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 444                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 445                 BIT_LDO_VDD25_XTL2_EN |
 446                 BIT_LDO_VDD25_XTL1_EN |
 447                 BIT_LDO_VDD25_XTL0_EN |
 448                 //BIT_LDO_RF2_EXT_XTL2_EN |
 449                 //BIT_LDO_RF2_EXT_XTL1_EN |
 450                 //BIT_LDO_RF2_EXT_XTL0_EN |
 451                 BIT_LDO_RF2_XTL2_EN |
 452                 BIT_LDO_RF2_XTL1_EN |
 453                 BIT_LDO_RF2_XTL0_EN |
 454                 0
 455         );
 456
 457         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 458                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 459                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 460                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 461                 //BIT_LDO_AVDD18_XTL2_EN |
 462                 //BIT_LDO_AVDD18_XTL1_EN |
 463                 //BIT_LDO_AVDD18_XTL0_EN |
 464                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 465                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 466                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 467                 //BIT_LDO_SIM2_XTL2_EN |
 468                 //BIT_LDO_SIM2_XTL1_EN |
 469                 //BIT_LDO_SIM2_XTL0_EN |
 470                 0
 471         );
 472
 473         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 474                 //BIT_DCDC_BG_EXT_XTL2_EN |
 475                 //BIT_DCDC_BG_EXT_XTL1_EN |
 476                 //BIT_DCDC_BG_EXT_XTL0_EN |
 477                 BIT_DCDC_BG_XTL2_EN |
 478                 BIT_DCDC_BG_XTL1_EN |
 479                 BIT_DCDC_BG_XTL0_EN |
 480                 //BIT_BG_EXT_XTL2_EN |
 481                 //BIT_BG_EXT_XTL1_EN |
 482                 //BIT_BG_EXT_XTL0_EN |
 483                 //BIT_BG_XTL2_EN |
 484                 //BIT_BG_XTL1_EN |
 485                 //BIT_BG_XTL0_EN |
 486                 0
 487         );
 488
 489         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 490                 //BIT_DCDC_WRF_XTL2_EN |
 491                 //BIT_DCDC_WRF_XTL1_EN |
 492                 //BIT_DCDC_WRF_XTL0_EN |
 493                 BIT_DCDC_WPA_XTL2_EN |
 494                 //BIT_DCDC_WPA_XTL1_EN |
 495                 //BIT_DCDC_WPA_XTL0_EN |
 496                 BIT_DCDC_MEM_XTL2_EN |
 497                 BIT_DCDC_MEM_XTL1_EN |
 498                 BIT_DCDC_MEM_XTL0_EN |
 499                 BIT_DCDC_GEN_XTL2_EN |
 500                 BIT_DCDC_GEN_XTL1_EN |
 501                 BIT_DCDC_GEN_XTL0_EN |
 502                 BIT_DCDC_CORE_XTL2_EN |
 503                 BIT_DCDC_CORE_XTL1_EN |
 504                 BIT_DCDC_CORE_XTL0_EN |
 505                 0
 506         );
 507
 508         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 509                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 510                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 511                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 512                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 513                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 514                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 515                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 516                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 517                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 518                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 519                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 520                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 521                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 522                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 523                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 524                 0
 525         );
 526
 527 #endif
 528         /************************************************
 529         *   Following is AP/CP LDO D DIE Sleep Control   *
 530         *************************************************/
 531
 532
 533         /* Bug 364866_IQ imbalance patch */
 534         reg_val = CHIP_REG_GET(REG_AON_APB_BB_BG_CTRL);
 535         reg_val &= ~(0xF << 16);
 536         reg_val |= (0x4 << 16);
 537         CHIP_REG_SET(REG_AON_APB_BB_BG_CTRL,reg_val);
 538
 539         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 540                 BIT_XTL0_AP_SEL |
 541                 BIT_XTL0_CP0_SEL |
 542                 BIT_XTL0_CP1_SEL |
 543                 BIT_XTL0_CP2_SEL |
 544                 0
 545         );
 546
 547         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 548                 BIT_XTL1_AP_SEL |
 549                 BIT_XTL1_CP0_SEL |
 550                 BIT_XTL1_CP1_SEL |
 551                 BIT_XTL1_CP2_SEL |
 552                 0
 553         );
 554
 555         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 556                 //BIT_XTL2_AP_SEL |
 557                 //BIT_XTL2_CP0_SEL |
 558                 //BIT_XTL2_CP1_SEL |
 559                 BIT_XTL2_CP2_SEL |
 560                 0
 561         );
 562
 563         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 564                 BIT_XTLBUF0_CP2_SEL |
 565                 BIT_XTLBUF0_CP1_SEL |
 566                 BIT_XTLBUF0_CP0_SEL |
 567                 BIT_XTLBUF0_AP_SEL  |
 568                 0
 569         );
 570
 571         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 572                 BIT_XTLBUF1_CP2_SEL |
 573                 BIT_XTLBUF1_CP1_SEL |
 574                 BIT_XTLBUF1_CP0_SEL |
 575                 BIT_XTLBUF1_AP_SEL  |
 576                 0
 577         );
 578
 579         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 580                 //BIT_MPLL_REF_SEL |
 581                 //BIT_MPLL_CP2_SEL |
 582                 //BIT_MPLL_CP1_SEL |
 583                 //BIT_MPLL_CP0_SEL |
 584                 BIT_MPLL_AP_SEL  |
 585                 0
 586         );
 587
 588         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 589                 //BIT_DPLL_REF_SEL |
 590                 BIT_DPLL_CP2_SEL |
 591                 BIT_DPLL_CP1_SEL |
 592                 BIT_DPLL_CP0_SEL |
 593                 BIT_DPLL_AP_SEL  |
 594                 0
 595         );
 596         /*caution tdpll & wpll sel config in spl*/
 597         reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 598         reg_val &= ~0xF;
 599         reg_val |= (
 600                    BIT_TDPLL_CP2_SEL|
 601                    BIT_TDPLL_CP1_SEL|
 602                    BIT_TDPLL_CP0_SEL|
 603                    BIT_TDPLL_AP_SEL |
 604                    0);
 605         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
 606
 607         reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
 608         reg_val &= ~0xF;
 609         reg_val |= (
 610                    //BIT_WPLL_CP2_SEL|
 611                    //BIT_WPLL_CP1_SEL|
 612                    BIT_WPLL_CP0_SEL|
 613                    BIT_WPLL_AP_SEL |
 614                    0);
 615         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
 616
 617         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 618                 //BIT_CPLL_REF_SEL |
 619                 BIT_CPLL_CP2_SEL |
 620                 //BIT_CPLL_CP1_SEL |
 621                 //BIT_CPLL_CP0_SEL |
 622                 BIT_CPLL_AP_SEL  |
 623                 0
 624         );
 625
 626         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 627                 BIT_WIFIPLL1_REF_SEL |
 628                 BIT_WIFIPLL1_CP2_SEL |
 629                 //BIT_WIFIPLL1_CP1_SEL |
 630                 //BIT_WIFIPLL1_CP0_SEL |
 631                 //BIT_WIFIPLL1_AP_SEL |
 632                 0
 633         );
 634
 635         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 636                 BIT_WIFIPLL2_REF_SEL |
 637                 BIT_WIFIPLL2_CP2_SEL |
 638                 //BIT_WIFIPLL2_CP1_SEL |
 639                 //BIT_WIFIPLL2_CP0_SEL |
 640                 //BIT_WIFIPLL2_AP_SEL |
 641                 0
 642         );
 643
 644         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 645                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 646                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 647                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 648                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 649                 0
 650         );
 651
 652         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 653                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 654                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 655                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 656                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 657                 0
 658         );
 659
 660         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 661                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 662                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 663                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 664                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 665                 0
 666         );
 667
 668         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 669                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 670                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 671                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 672                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 673                 0
 674         );
 675
 676         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 677                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 678                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 679                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 680                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 681                 0
 682         );
 683
 684         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 685                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 686                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 687                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 688                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 689                 0
 690         );
 691
 692         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 693                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 694                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 695                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 696                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 697                 0
 698         );
 699
 700         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 701                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 702                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 703                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 704                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 705                 0
 706         );
 707
 708         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 709                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 710                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 711                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 712                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 713                 0
 714         );
 715
 716         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
 717                 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN        |
 718                 BITS_PD_DDR_PUBL_PWR_ON_DLY(8)          |
 719                 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0)      |
 720                 BITS_PD_DDR_PUBL_ISO_ON_DLY(6)          |
 721                 0
 722         );
 723
 724         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
 725                 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN         |
 726                 BITS_PD_DDR_PHY_PWR_ON_DLY(8)           |
 727                 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0)       |
 728                 BITS_PD_DDR_PHY_ISO_ON_DLY(6)           |
 729                 0
 730         );
 731
 732         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 733                 BITS_XTL1_WAIT_CNT(0x73)                |
 734                 BITS_XTL0_WAIT_CNT(0x73)                |
 735                 0
 736         );
 737
 738         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 739                 BITS_XTLBUF1_WAIT_CNT(7)                |
 740                 BITS_XTLBUF0_WAIT_CNT(7)                |
 741                 0
 742         );
 743
 744         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 745                 BITS_WPLL_WAIT_CNT(7)                   |
 746                 BITS_TDPLL_WAIT_CNT(7)                  |
 747                 BITS_DPLL_WAIT_CNT(7)                   |
 748                 BITS_MPLL_WAIT_CNT(7)                   |
 749                 0
 750         );
 751
 752         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 753                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 754                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 755                 BITS_CPLL_WAIT_CNT(7)                   |
 756                 0
 757         );
 758
 759         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 760                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 761                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 762                 0
 763         );
 764
 765         CHIP_REG_SET(REG_PMU_APB_PD_CODEC_TOP_CFG,
 766                 BIT_PD_CODEC_TOP_FORCE_SHUTDOWN            |
 767                 BITS_PD_CODEC_TOP_PWR_ON_DLY(8)            |
 768                 BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(0)        |
 769                 BITS_PD_CODEC_TOP_ISO_ON_DLY(4)            |
 770                 0
 771         );
 772
 773         /*chip service package init*/
 774         CSP_Init(0);
 775 }