board/spreadtrum/sp8815gaopenphone/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30         u32 reg_val;
  31
  32         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
  33         reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7);
  34         reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4);
  35         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val);
  36
  37         /**********************************************
  38          *   Following is AP LDO A DIE Sleep Control  *
  39          *********************************************/
  40         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  41         //BIT_SLP_IO_EN |
  42         //BIT_SLP_DCDCGEN_PD_EN |
  43         BIT_SLP_DCDCWPA_PD_EN |
  44         BIT_SLP_DCDCARM_PD_EN |
  45         BIT_SLP_LDORF0_PD_EN |
  46         BIT_SLP_LDOEMMCCORE_PD_EN |
  47         BIT_SLP_LDOEMMCIO_PD_EN |
  48         //BIT_SLP_LDODCXO_PD_EN |
  49         BIT_SLP_LDOCON_PD_EN |
  50         BIT_SLP_LDOVDD25_PD_EN |
  51         //BIT_SLP_LDOVDD28_PD_EN |
  52         //BIT_SLP_LODVDD18_PD_EN |
  53         0
  54         );
  55
  56         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  57         //BIT_SLP_LDO_PD_EN |
  58         BIT_SLP_LDOLPREF_PD_EN |
  59         BIT_SLP_LDOCLSG_PD_EN |
  60         BIT_SLP_LDOUSB_PD_EN |
  61         BIT_SLP_LDOCAMMOT_PD_EN |
  62         BIT_SLP_LDOCAMIO_PD_EN |
  63         BIT_SLP_LDOCAMD_PD_EN |
  64         BIT_SLP_LDOCAMA_PD_EN |
  65         BIT_SLP_LDOSIM2_PD_EN |
  66         BIT_SLP_LDOSIM1_PD_EN |
  67         BIT_SLP_LDOSIM0_PD_EN |
  68         BIT_SLP_LDOSD_PD_EN |
  69         0);
  70
  71         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
  72         //BIT_SLP_DCDCCORE_LP_EN |
  73         //BIT_SLP_DCDCMEM_LP_EN |
  74         //BIT_SLP_DCDCARM_LP_EN |
  75         //BIT_SLP_DCDCGEN_LP_EN |
  76         //BIT_SLP_DCDCWPA_LP_EN |
  77         //BIT_SLP_LDORF0_LP_EN |
  78         //BIT_SLP_LDOEMMCCORE_LP_EN |
  79         //BIT_SLP_LDOEMMCIO_LP_EN |
  80         //BIT_SLP_LDODCXO_LP_EN |
  81         //BIT_SLP_LDOCON_LP_EN |
  82         //BIT_SLP_LDOVDD25_LP_EN |
  83         //BIT_SLP_LDOVDD28_LP_EN |
  84         //BIT_SLP_LDOVDD18_LP_EN |
  85         0);
  86
  87         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
  88         //BIT_SLP_LDOCLSG_LP_EN |
  89         //BIT_SLP_LDOUSB_LP_EN |
  90         //BIT_SLP_LDOCAMMOT_LP_EN |
  91         //BIT_SLP_LDOCAMIO_LP_EN |
  92         //BIT_SLP_LDOCAMD_LP_EN |
  93         //BIT_SLP_LDOCAMA_LP_EN |
  94         //BIT_SLP_LDOSIM2_LP_EN |
  95         //BIT_SLP_LDOSIM1_LP_EN |
  96         //BIT_SLP_LDOSIM0_LP_EN |
  97         //BIT_SLP_LDOSD_LP_EN |
  98         0);
  99         /****************************************
 100         *   Following is CP LDO Sleep Control  *
 101         ****************************************/
 102         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 103         //BIT_LDO_XTL_EN |
 104         //BIT_LDO_DCXO_EXT_XTL1_EN |
 105         //BIT_LDO_DCXO_EXT_XTL0_EN |
 106         //BIT_LDO_DCXO_XTL2_EN |
 107         //BIT_LDO_DCXO_XTL0_EN |
 108         //BIT_LDO_VDD18_EXT_XTL1_EN |
 109         //BIT_LDO_VDD18_EXT_XTL0_EN |
 110         //BIT_LDO_VDD18_XTL2_EN |
 111         //BIT_LDO_VDD18_XTL0_EN |
 112         //BIT_LDO_VDD28_EXT_XTL1_EN |
 113         //BIT_LDO_VDD28_EXT_XTL0_EN |
 114         //BIT_LDO_VDD28_XTL2_EN |
 115         //BIT_LDO_VDD28_XTL0_EN |
 116         0);
 117
 118         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 119         //BIT_LDO_RF0_EXT_XTL1_EN |
 120         //BIT_LDO_RF0_EXT_XTL0_EN |
 121         //BIT_LDO_RF0_XTL2_EN |
 122         //BIT_LDO_RF0_XTL0_EN |
 123         //BIT_LDO_VDD25_EXT_XTL1_EN |
 124         //BIT_LDO_VDD25_EXT_XTL0_EN |
 125         BIT_LDO_VDD25_XTL2_EN |
 126         BIT_LDO_VDD25_XTL0_EN |
 127         //BIT_LDO_CON_EXT_XTL1_EN |
 128         //BIT_LDO_CON_EXT_XTL0_EN |
 129         BIT_LDO_CON_XTL2_EN |
 130         BIT_LDO_CON_XTL0_EN |
 131         0);
 132
 133         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 134         //BIT_LDO_SIM2_EXT_XTL1_EN |
 135         //BIT_LDO_SIM2_EXT_XTL0_EN |
 136         //BIT_LDO_SIM2_XTL2_EN |
 137         //BIT_LDO_SIM2_XTL0_EN |
 138         //BIT_LDO_SIM1_EXT_XTL1_EN |
 139         //BIT_LDO_SIM1_EXT_XTL0_EN |
 140         //BIT_LDO_SIM1_XTL2_EN |
 141         //BIT_LDO_SIM1_XTL0_EN |
 142         //BIT_LDO_SIM0_EXT_XTL1_EN |
 143         //BIT_LDO_SIM0_EXT_XTL0_EN |
 144         //BIT_LDO_SIM0_XTL2_EN |
 145         //BIT_LDO_SIM0_XTL0_EN |
 146         0);
 147
 148         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 149         //BIT_XO_EXT_XTL1_EN |
 150         //BIT_XO_EXT_XTL0_EN |
 151         //BIT_XO_XTL2_EN |
 152         //BIT_XO_XTL0_EN |
 153         //BIT_BG_EXT_XTL1_EN |
 154         //BIT_BG_EXT_XTL0_EN |
 155         //BIT_BG_XTL2_EN |
 156         //BIT_BG_XTL0_EN |
 157         0);
 158
 159         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 160         //BIT_DCDC_WPA_EXT_XTL1_EN |
 161         //BIT_DCDC_WPA_EXT_XTL0_EN |
 162         //BIT_DCDC_WPA_XTL2_EN |
 163         //BIT_DCDC_WPA_XTL0_EN |
 164         //BIT_DCDC_MEM_EXT_XTL1_EN |
 165         //BIT_DCDC_MEM_EXT_XTL0_EN |
 166         //BIT_DCDC_MEM_XTL2_EN |
 167         //BIT_DCDC_MEM_XTL0_EN |
 168         //BIT_DCDC_GEN_EXT_XTL1_EN |
 169         //BIT_DCDC_GEN_EXT_XTL0_EN |
 170         //BIT_DCDC_GEN_XTL2_EN |
 171         //BIT_DCDC_GEN_XTL0_EN |
 172         //BIT_DCDC_CORE_EXT_XTL1_EN |
 173         //BIT_DCDC_CORE_EXT_XTL0_EN |
 174         //BIT_DCDC_CORE_XTL2_EN |
 175         //BIT_DCDC_CORE_XTL0_EN |
 176         0);
 177         /************************************************
 178         *   Following is AP/CP LDO D DIE Sleep Control   *
 179         *************************************************/
 180         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 181                 BIT_XTL0_AP_SEL |
 182                 BIT_XTL0_CP0_SEL |
 183                 //BIT_XTL0_CP1_SEL |
 184                 BIT_XTL0_CP2_SEL |
 185                 0
 186         );
 187
 188         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 189                 //BIT_XTL1_AP_SEL |
 190                 //BIT_XTL1_CP0_SEL |
 191                 BIT_XTL1_CP1_SEL |
 192                 //BIT_XTL1_CP2_SEL |
 193                 0
 194         );
 195
 196         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 197                 //BIT_XTL2_AP_SEL |
 198                 //BIT_XTL2_CP0_SEL |
 199                 //BIT_XTL2_CP1_SEL |
 200                 BIT_XTL2_CP2_SEL |
 201                 0
 202         );
 203
 204         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 205                 BIT_XTLBUF0_CP2_SEL |
 206                 //BIT_XTLBUF0_CP1_SEL |
 207                 BIT_XTLBUF0_CP0_SEL |
 208                 BIT_XTLBUF0_AP_SEL  |
 209                 0
 210         );
 211
 212         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 213                 //BIT_XTLBUF1_CP2_SEL |
 214                 BIT_XTLBUF1_CP1_SEL |
 215                 //BIT_XTLBUF1_CP0_SEL |
 216                 //BIT_XTLBUF1_AP_SEL  |
 217                 0
 218         );
 219
 220         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 221                 //BIT_MPLL_REF_SEL |
 222                 //BIT_MPLL_CP2_SEL |
 223                 //BIT_MPLL_CP1_SEL |
 224                 //BIT_MPLL_CP0_SEL |
 225                 BIT_MPLL_AP_SEL  |
 226                 0
 227         );
 228
 229         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 230                 //BIT_DPLL_REF_SEL |
 231                 BIT_DPLL_CP2_SEL |
 232                 BIT_DPLL_CP1_SEL |
 233                 BIT_DPLL_CP0_SEL |
 234                 BIT_DPLL_AP_SEL  |
 235                 0
 236         );
 237
 238         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 239                 //BIT_TDPLL_REF_SEL |
 240                 BIT_TDPLL_CP2_SEL |
 241                 BIT_TDPLL_CP1_SEL |
 242                 BIT_TDPLL_CP0_SEL |
 243                 BIT_TDPLL_AP_SEL  |
 244                 0
 245         );
 246
 247         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 248                 //BIT_WPLL_REF_SEL |
 249                 //BIT_WPLL_CP2_SEL |
 250                 //BIT_WPLL_CP1_SEL |
 251                 BIT_WPLL_CP0_SEL |
 252                 //BIT_WPLL_AP_SEL  |
 253                 0
 254         );
 255
 256         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 257                 //BIT_CPLL_REF_SEL |
 258                 BIT_CPLL_CP2_SEL |
 259                 //BIT_CPLL_CP1_SEL |
 260                 //BIT_CPLL_CP0_SEL |
 261                 //BIT_CPLL_AP_SEL  |
 262                 0
 263         );
 264
 265         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 266                 //BIT_WIFIPLL1_REF_SEL |
 267                 BIT_WIFIPLL1_CP2_SEL |
 268                 //BIT_WIFIPLL1_CP1_SEL |
 269                 //BIT_WIFIPLL1_CP0_SEL |
 270                 //BIT_WIFIPLL1_AP_SEL |
 271                 0
 272         );
 273
 274         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 275                 //BIT_WIFIPLL2_REF_SEL |
 276                 BIT_WIFIPLL2_CP2_SEL |
 277                 //BIT_WIFIPLL2_CP1_SEL |
 278                 //BIT_WIFIPLL2_CP0_SEL |
 279                 //BIT_WIFIPLL2_AP_SEL |
 280                 0
 281         );
 282
 283         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 284                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 285                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 286                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 287                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 288                 0
 289         );
 290
 291         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 292                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 293                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 294                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 295                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 296                 0
 297         );
 298
 299         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 300                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 301                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 302                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 303                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 304                 0
 305         );
 306
 307         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 308                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 309                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 310                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 311                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 312                 0
 313         );
 314
 315         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 316                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 317                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 318                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 319                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 320                 0
 321         );
 322
 323         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 324                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 325                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 326                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 327                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 328                 0
 329         );
 330
 331         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 332                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 333                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 334                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 335                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 336                 0
 337         );
 338
 339         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 340                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 341                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 342                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 343                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 344                 0
 345         );
 346
 347         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 348                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 349                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 350                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 351                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 352                 0
 353         );
 354
 355         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 356                 BITS_XTL1_WAIT_CNT(0x39)                |
 357                 BITS_XTL0_WAIT_CNT(0x39)                |
 358                 0
 359         );
 360
 361         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 362                 BITS_XTLBUF1_WAIT_CNT(7)                |
 363                 BITS_XTLBUF0_WAIT_CNT(7)                |
 364                 0
 365         );
 366
 367         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 368                 BITS_WPLL_WAIT_CNT(7)                   |
 369                 BITS_TDPLL_WAIT_CNT(7)                  |
 370                 BITS_DPLL_WAIT_CNT(7)                   |
 371                 BITS_MPLL_WAIT_CNT(7)                   |
 372                 0
 373         );
 374
 375         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 376                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 377                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 378                 BITS_CPLL_WAIT_CNT(7)                   |
 379                 0
 380         );
 381
 382         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 383                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 384                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 385                 0
 386         );
 387 }