board/spreadtrum/sp8815ga/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30        u32 reg_val;
  31
  32        ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
  33
  34        do{
  35                reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
  36        }while(reg_val == 0);
  37
  38        reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_PD_CTRL);
  39        reg_val &= ~BIT_DCDC_WPA_PD;
  40        ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,reg_val);
  41
  42        ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
  43
  44         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
  45         reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7);
  46         reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4);
  47         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val);
  48
  49         /**********************************************
  50          *   Following is AP LDO A DIE Sleep Control  *
  51          *********************************************/
  52         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  53         BIT_SLP_IO_EN   |
  54         //BIT_SLP_DCDCGEN_PD_EN |
  55         BIT_SLP_DCDCWPA_PD_EN |
  56         BIT_SLP_DCDCARM_PD_EN |
  57         BIT_SLP_LDORF0_PD_EN |
  58         BIT_SLP_LDOEMMCCORE_PD_EN |
  59         BIT_SLP_LDOEMMCIO_PD_EN |
  60         //BIT_SLP_LDODCXO_PD_EN |
  61         BIT_SLP_LDOCON_PD_EN |
  62         BIT_SLP_LDOVDD25_PD_EN |
  63         //BIT_SLP_LDOVDD28_PD_EN |
  64         //BIT_SLP_LODVDD18_PD_EN |
  65         0
  66         );
  67
  68         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  69         BIT_SLP_LDO_PD_EN |
  70         BIT_SLP_LDOLPREF_PD_EN |
  71         BIT_SLP_LDOCLSG_PD_EN |
  72         BIT_SLP_LDOUSB_PD_EN |
  73         BIT_SLP_LDOCAMMOT_PD_EN |
  74         BIT_SLP_LDOCAMIO_PD_EN |
  75         BIT_SLP_LDOCAMD_PD_EN |
  76         BIT_SLP_LDOCAMA_PD_EN |
  77         BIT_SLP_LDOSIM2_PD_EN |
  78         //BIT_SLP_LDOSIM1_PD_EN |
  79         //BIT_SLP_LDOSIM0_PD_EN |
  80         BIT_SLP_LDOSD_PD_EN |
  81         0);
  82
  83         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
  84         //BIT_SLP_DCDCCORE_LP_EN |
  85         //BIT_SLP_DCDCMEM_LP_EN |
  86         //BIT_SLP_DCDCARM_LP_EN |
  87         //BIT_SLP_DCDCGEN_LP_EN |
  88         //BIT_SLP_DCDCWPA_LP_EN |
  89         //BIT_SLP_LDORF0_LP_EN |
  90         //BIT_SLP_LDOEMMCCORE_LP_EN |
  91         //BIT_SLP_LDOEMMCIO_LP_EN |
  92         //BIT_SLP_LDODCXO_LP_EN |
  93         //BIT_SLP_LDOCON_LP_EN |
  94         //BIT_SLP_LDOVDD25_LP_EN |
  95         //BIT_SLP_LDOVDD28_LP_EN |
  96         //BIT_SLP_LDOVDD18_LP_EN |
  97         0);
  98
  99         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 100         BIT_SLP_BG_LP_EN|
 101         //BIT_SLP_LDOCLSG_LP_EN |
 102         //BIT_SLP_LDOUSB_LP_EN |
 103         //BIT_SLP_LDOCAMMOT_LP_EN |
 104         //BIT_SLP_LDOCAMIO_LP_EN |
 105         //BIT_SLP_LDOCAMD_LP_EN |
 106         //BIT_SLP_LDOCAMA_LP_EN |
 107         //BIT_SLP_LDOSIM2_LP_EN |
 108         //BIT_SLP_LDOSIM1_LP_EN |
 109         //BIT_SLP_LDOSIM0_LP_EN |
 110         //BIT_SLP_LDOSD_LP_EN |
 111         0);
 112         /****************************************
 113         *   Following is CP LDO Sleep Control  *
 114         ****************************************/
 115         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 116         BIT_LDO_XTL_EN |
 117         //BIT_LDO_DCXO_EXT_XTL1_EN |
 118         //BIT_LDO_DCXO_EXT_XTL0_EN |
 119         //BIT_LDO_DCXO_XTL2_EN |
 120         //BIT_LDO_DCXO_XTL0_EN |
 121         //BIT_LDO_VDD18_EXT_XTL1_EN |
 122         //BIT_LDO_VDD18_EXT_XTL0_EN |
 123         //BIT_LDO_VDD18_XTL2_EN |
 124         //BIT_LDO_VDD18_XTL0_EN |
 125         //BIT_LDO_VDD28_EXT_XTL1_EN |
 126         //BIT_LDO_VDD28_EXT_XTL0_EN |
 127         //BIT_LDO_VDD28_XTL2_EN |
 128         //BIT_LDO_VDD28_XTL0_EN |
 129         0);
 130
 131         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 132         BIT_LDO_RF0_EXT_XTL1_EN |
 133         BIT_LDO_RF0_EXT_XTL0_EN |
 134         BIT_LDO_RF0_XTL2_EN |
 135         BIT_LDO_RF0_XTL0_EN |
 136         //BIT_LDO_VDD25_EXT_XTL1_EN |
 137         //BIT_LDO_VDD25_EXT_XTL0_EN |
 138         BIT_LDO_VDD25_XTL2_EN |
 139         BIT_LDO_VDD25_XTL0_EN |
 140         //BIT_LDO_CON_EXT_XTL1_EN |
 141         //BIT_LDO_CON_EXT_XTL0_EN |
 142         BIT_LDO_CON_XTL2_EN |
 143         BIT_LDO_CON_XTL0_EN |
 144         0);
 145
 146         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 147         //BIT_LDO_SIM2_EXT_XTL1_EN |
 148         //BIT_LDO_SIM2_EXT_XTL0_EN |
 149         //BIT_LDO_SIM2_XTL2_EN |
 150         //BIT_LDO_SIM2_XTL0_EN |
 151         //BIT_LDO_SIM1_EXT_XTL1_EN |
 152         //BIT_LDO_SIM1_EXT_XTL0_EN |
 153         //BIT_LDO_SIM1_XTL2_EN |
 154         //BIT_LDO_SIM1_XTL0_EN |
 155         //BIT_LDO_SIM0_EXT_XTL1_EN |
 156         //BIT_LDO_SIM0_EXT_XTL0_EN |
 157         //BIT_LDO_SIM0_XTL2_EN |
 158         //BIT_LDO_SIM0_XTL0_EN |
 159         0);
 160
 161         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 162         //BIT_XO_EXT_XTL1_EN |
 163         //BIT_XO_EXT_XTL0_EN |
 164         //BIT_XO_XTL2_EN |
 165         //BIT_XO_XTL0_EN |
 166         //BIT_BG_EXT_XTL1_EN |
 167         //BIT_BG_EXT_XTL0_EN |
 168         BIT_BG_XTL2_EN |
 169         BIT_BG_XTL0_EN |
 170         0);
 171
 172         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 173         //BIT_DCDC_WPA_EXT_XTL1_EN |
 174         //BIT_DCDC_WPA_EXT_XTL0_EN |
 175         //BIT_DCDC_WPA_XTL2_EN |
 176         //BIT_DCDC_WPA_XTL0_EN |
 177         //BIT_DCDC_MEM_EXT_XTL1_EN |
 178         //BIT_DCDC_MEM_EXT_XTL0_EN |
 179         BIT_DCDC_MEM_XTL2_EN |
 180         BIT_DCDC_MEM_XTL0_EN |
 181         //BIT_DCDC_GEN_EXT_XTL1_EN |
 182         //BIT_DCDC_GEN_EXT_XTL0_EN |
 183         BIT_DCDC_GEN_XTL2_EN |
 184         BIT_DCDC_GEN_XTL0_EN |
 185         //BIT_DCDC_CORE_EXT_XTL1_EN |
 186         //BIT_DCDC_CORE_EXT_XTL0_EN |
 187         BIT_DCDC_CORE_XTL2_EN |
 188         BIT_DCDC_CORE_XTL0_EN |
 189         0);
 190         /************************************************
 191         *   Following is AP/CP LDO D DIE Sleep Control   *
 192         *************************************************/
 193         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 194                 BIT_XTL0_AP_SEL |
 195                 BIT_XTL0_CP0_SEL |
 196                 BIT_XTL0_CP1_SEL |
 197                 BIT_XTL0_CP2_SEL |
 198                 0
 199         );
 200
 201         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 202                 BIT_XTL1_AP_SEL |
 203                 //BIT_XTL1_CP0_SEL |
 204                 BIT_XTL1_CP1_SEL |
 205                 BIT_XTL1_CP2_SEL |
 206                 0
 207         );
 208
 209         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 210                 //BIT_XTL2_AP_SEL |
 211                 //BIT_XTL2_CP0_SEL |
 212                 //BIT_XTL2_CP1_SEL |
 213                 BIT_XTL2_CP2_SEL |
 214                 0
 215         );
 216
 217         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 218                 BIT_XTLBUF0_CP2_SEL |
 219                 BIT_XTLBUF0_CP1_SEL |
 220                 BIT_XTLBUF0_CP0_SEL |
 221                 BIT_XTLBUF0_AP_SEL  |
 222                 0
 223         );
 224
 225         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 226                 //BIT_XTLBUF1_CP2_SEL |
 227                 BIT_XTLBUF1_CP1_SEL |
 228                 //BIT_XTLBUF1_CP0_SEL |
 229                 //BIT_XTLBUF1_AP_SEL  |
 230                 0
 231         );
 232
 233         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 234                 //BIT_MPLL_REF_SEL |
 235                 //BIT_MPLL_CP2_SEL |
 236                 //BIT_MPLL_CP1_SEL |
 237                 //BIT_MPLL_CP0_SEL |
 238                 BIT_MPLL_AP_SEL  |
 239                 0
 240         );
 241
 242         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 243                 //BIT_DPLL_REF_SEL |
 244                 BIT_DPLL_CP2_SEL |
 245                 BIT_DPLL_CP1_SEL |
 246                 BIT_DPLL_CP0_SEL |
 247                 BIT_DPLL_AP_SEL  |
 248                 0
 249         );
 250
 251         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 252                 //BIT_TDPLL_REF_SEL |
 253                 BIT_TDPLL_CP2_SEL |
 254                 BIT_TDPLL_CP1_SEL |
 255                 BIT_TDPLL_CP0_SEL |
 256                 BIT_TDPLL_AP_SEL  |
 257                 0
 258         );
 259
 260         if(ANA_GET_CHIP_ID() == 0x2711a000)
 261         {
 262                 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 263                         //BIT_WPLL_REF_SEL |
 264                         //BIT_WPLL_CP2_SEL |
 265                         //BIT_WPLL_CP1_SEL |
 266                         BIT_WPLL_CP0_SEL |
 267                         //BIT_WPLL_AP_SEL  |
 268                         0
 269                 );
 270         } else {
 271                 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 272                         //BIT_XTLBUF1_CP2_SEL |
 273                         //BIT_XTLBUF1_CP1_SEL |
 274                         BIT_XTLBUF1_CP0_SEL |
 275                         //BIT_XTLBUF1_AP_SEL  |
 276                         0
 277                 );
 278
 279                 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 280                         BIT_WPLL_REF_SEL |
 281                         //BIT_WPLL_CP2_SEL |
 282                         //BIT_WPLL_CP1_SEL |
 283                         BIT_WPLL_CP0_SEL |
 284                         //BIT_WPLL_AP_SEL  |
 285                         0
 286                 );
 287
 288                 CHIP_REG_SET(REG_AON_CLK_FM_CFG,
 289                         //BIT_CLK_FM_PAD_SEL |
 290                         //BIT_CLK_FM_SEL |
 291                         0
 292                 );
 293
 294                 CHIP_REG_SET(REG_AON_APB_GPS_26M_REF_SEL,
 295                         //BIT_XTLBUF1_GPS_SEL |
 296                         BIT_XTLBUF0_GPS_SEL |
 297                         //BIT_GPS_26M_REF_SEL |
 298                         0
 299                 );
 300         }
 301
 302         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 303                 //BIT_CPLL_REF_SEL |
 304                 BIT_CPLL_CP2_SEL |
 305                 //BIT_CPLL_CP1_SEL |
 306                 //BIT_CPLL_CP0_SEL |
 307                 //BIT_CPLL_AP_SEL  |
 308                 0
 309         );
 310
 311         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 312                 //BIT_WIFIPLL1_REF_SEL |
 313                 BIT_WIFIPLL1_CP2_SEL |
 314                 //BIT_WIFIPLL1_CP1_SEL |
 315                 //BIT_WIFIPLL1_CP0_SEL |
 316                 //BIT_WIFIPLL1_AP_SEL |
 317                 0
 318         );
 319
 320         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 321                 //BIT_WIFIPLL2_REF_SEL |
 322                 BIT_WIFIPLL2_CP2_SEL |
 323                 //BIT_WIFIPLL2_CP1_SEL |
 324                 //BIT_WIFIPLL2_CP0_SEL |
 325                 //BIT_WIFIPLL2_AP_SEL |
 326                 0
 327         );
 328
 329         CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
 330                 BIT_CGM_208M_AP_EN |
 331                 BIT_CGM_12M_AP_EN |
 332                 BIT_CGM_24M_AP_EN |
 333                 BIT_CGM_48M_AP_EN |
 334                 BIT_CGM_51M2_AP_EN |
 335                 BIT_CGM_64M_AP_EN |
 336                 BIT_CGM_76M8_AP_EN |
 337                 BIT_CGM_96M_AP_EN |
 338                 BIT_CGM_128M_AP_EN |
 339                 BIT_CGM_153M6_AP_EN |
 340                 BIT_CGM_192M_AP_EN |
 341                 BIT_CGM_256M_AP_EN |
 342                 BIT_CGM_384M_AP_EN |
 343                 BIT_CGM_312M_AP_EN |
 344                 BIT_CGM_MPLL_AP_EN |
 345                 //BIT_CGM_WPLL_AP_EN |
 346                 //BIT_CGM_WIFIPLL1_AP_EN |
 347                 BIT_CGM_TDPLL_AP_EN |
 348                 //BIT_CGM_CPLL_AP_EN |
 349                 BIT_CGM_DPLL_AP_EN |
 350                 BIT_CGM_26M_AP_EN |
 351                 0
 352         );
 353         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 354                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 355                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 356                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 357                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 358                 0
 359         );
 360
 361         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 362                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 363                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 364                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 365                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 366                 0
 367         );
 368
 369         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 370                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 371                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 372                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 373                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 374                 0
 375         );
 376
 377         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 378                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 379                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 380                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 381                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 382                 0
 383         );
 384
 385         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 386                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 387                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 388                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 389                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 390                 0
 391         );
 392
 393         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 394                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 395                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 396                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 397                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 398                 0
 399         );
 400
 401         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 402                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 403                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 404                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 405                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 406                 0
 407         );
 408
 409         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 410                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 411                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 412                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 413                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 414                 0
 415         );
 416
 417         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 418                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 419                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 420                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 421                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 422                 0
 423         );
 424
 425         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 426                 BITS_XTL1_WAIT_CNT(0x39)                |
 427                 BITS_XTL0_WAIT_CNT(0x39)                |
 428                 0
 429         );
 430
 431         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 432                 BITS_XTLBUF1_WAIT_CNT(7)                |
 433                 BITS_XTLBUF0_WAIT_CNT(7)                |
 434                 0
 435         );
 436
 437         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 438                 BITS_WPLL_WAIT_CNT(7)                   |
 439                 BITS_TDPLL_WAIT_CNT(7)                  |
 440                 BITS_DPLL_WAIT_CNT(7)                   |
 441                 BITS_MPLL_WAIT_CNT(7)                   |
 442                 0
 443         );
 444
 445         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 446                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 447                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 448                 BITS_CPLL_WAIT_CNT(7)                   |
 449                 0
 450         );
 451
 452         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 453                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 454                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 455                 0
 456         );
 457 }