board/spreadtrum/sp7720ea/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27 int set_default_regulator(void);
  28 void init_ldo_sleep_gr(void)
  29 {
  30         unsigned int reg_val;
  31
  32         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x6e7f);
  33         while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );
  34
  35 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
  36         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  37                 //BIT_LDO_EMM_PD |
  38                 //BIT_DCDC_TOPCLK6M_PD |
  39                 //BIT_DCDC_RF_PD |
  40                 //BIT_DCDC_GEN_PD |
  41                 //BIT_DCDC_MEM_PD |
  42                 //BIT_DCDC_ARM_PD |
  43                 //BIT_DCDC_CORE_PD |
  44                 //BIT_LDO_RF0_PD |
  45                 //BIT_LDO_EMMCCORE_PD |
  46                 //BIT_LDO_GEN1_PD |
  47                 //BIT_LDO_DCXO_PD |
  48                 //BIT_LDO_GEN0_PD |
  49                 //BIT_LDO_VDD25_PD |
  50                 //BIT_LDO_VDD28_PD |
  51                 //BIT_LDO_VDD18_PD |
  52                 //BIT_BG_PD |
  53                 0
  54         );
  55         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  56                 //BIT_LDO_LPREF_PD_SW |
  57                 //BIT_DCDC_WPA_PD |
  58                 //BIT_DCDC_CON_PD |
  59                 //BIT_LDO_WIFIPA_PD |
  60                 //BIT_LDO_SDCORE_PD |
  61                 //BIT_LDO_USB_PD |
  62                 //BIT_LDO_CAMMOT_PD |
  63                 //BIT_LDO_CAMIO_PD |
  64                 //BIT_LDO_CAMD_PD |
  65                 //BIT_LDO_CAMA_PD |
  66                 //BIT_LDO_SIM2_PD |
  67                 //BIT_LDO_SIM1_PD |
  68                 //BIT_LDO_SIM0_PD |
  69                 //BIT_LDO_SDIO_PD |
  70                 0
  71         );
  72
  73         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);
  74
  75         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  76                 BIT_SLP_IO_EN |
  77                 BIT_SLP_DCDCRF_PD_EN |
  78                 BIT_SLP_DCDCCON_PD_EN |
  79                 //BIT_SLP_DCDCGEN_PD_EN |
  80                 //BIT_SLP_DCDCWPA_PD_EN |
  81                 BIT_SLP_DCDCARM_PD_EN |
  82                 BIT_SLP_LDOVDD25_PD_EN |
  83                 BIT_SLP_LDORF0_PD_EN |
  84                 BIT_SLP_LDOEMMCCORE_PD_EN |
  85                 BIT_SLP_LDOGEN0_PD_EN |
  86                 BIT_SLP_LDODCXO_PD_EN |
  87                 //BIT_SLP_LDOGEN1_PD_EN |
  88                 BIT_SLP_LDOWIFIPA_PD_EN |
  89                 //BIT_SLP_LDOVDD28_PD_EN |
  90                 //BIT_SLP_LDOVDD18_PD_EN |
  91                 0
  92         );
  93         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  94                 BIT_SLP_LDO_PD_EN |
  95                 BIT_SLP_LDOLPREF_PD_EN |
  96                 BIT_SLP_LDOSDCORE_PD_EN |
  97                 BIT_SLP_LDOUSB_PD_EN |
  98                 BIT_SLP_LDOCAMMOT_PD_EN |
  99                 BIT_SLP_LDOCAMIO_PD_EN |
 100                 BIT_SLP_LDOCAMD_PD_EN |
 101                 BIT_SLP_LDOCAMA_PD_EN |
 102                 //BIT_SLP_LDOSIM2_PD_EN |
 103                 //BIT_SLP_LDOSIM1_PD_EN |
 104                 //BIT_SLP_LDOSIM0_PD_EN |
 105                 BIT_SLP_LDOSDIO_PD_EN |
 106                 0
 107         );
 108         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 109                 //BIT_SLP_DCDCRF_LP_EN |
 110                 //BIT_SLP_DCDCCON_LP_EN |
 111                 BIT_SLP_DCDCCORE_LP_EN |
 112                 BIT_SLP_DCDCMEM_LP_EN |
 113                 //BIT_SLP_DCDCARM_LP_EN |
 114                 BIT_SLP_DCDCGEN_LP_EN |
 115                 //BIT_SLP_DCDCWPA_LP_EN |
 116                 //BIT_SLP_LDORF0_LP_EN |
 117                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 118                 //BIT_SLP_LDOGEN0_LP_EN |
 119                 //BIT_SLP_LDODCXO_LP_EN |
 120                 //BIT_SLP_LDOGEN1_LP_EN |
 121                 //BIT_SLP_LDOWIFIPA_LP_EN |
 122                 //BIT_SLP_LDOVDD28_LP_EN |
 123                 //BIT_SLP_LDOVDD18_LP_EN |
 124                 0
 125         );
 126         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 127                 //BIT_SLP_BG_LP_EN |
 128                 //BIT_LDOVDD25_LP_EN_SW |
 129                 //BIT_LDOSDCORE_LP_EN_SW |
 130                 //BIT_LDOUSB_LP_EN_SW |
 131                 //BIT_SLP_LDOVDD25_LP_EN |
 132                 //BIT_SLP_LDOSDCORE_LP_EN |
 133                 //BIT_SLP_LDOUSB_LP_EN |
 134                 //BIT_SLP_LDOCAMMOT_LP_EN |
 135                 //BIT_SLP_LDOCAMIO_LP_EN |
 136                 //BIT_SLP_LDOCAMD_LP_EN |
 137                 //BIT_SLP_LDOCAMA_LP_EN |
 138                 //BIT_SLP_LDOSIM2_LP_EN |
 139                 //BIT_SLP_LDOSIM1_LP_EN |
 140                 //BIT_SLP_LDOSIM0_LP_EN |
 141                 //BIT_SLP_LDOSDIO_LP_EN |
 142                 0
 143         );
 144         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 145                 //BIT_LDOCAMIO_LP_EN_SW |
 146                 //BIT_LDOCAMMOT_LP_EN_SW |
 147                 //BIT_LDOCAMD_LP_EN_SW |
 148                 //BIT_LDOCAMA_LP_EN_SW |
 149                 //BIT_LDOSIM2_LP_EN_SW |
 150                 //BIT_LDOSIM1_LP_EN_SW |
 151                 //BIT_LDOSIM0_LP_EN_SW |
 152                 //BIT_LDOSDIO_LP_EN_SW |
 153                 //BIT_LDORF0_LP_EN_SW |
 154                 //BIT_LDOEMMCCORE_LP_EN_SW |
 155                 //BIT_LDOGEN0_LP_EN_SW |
 156                 //BIT_LDODCXO_LP_EN_SW |
 157                 //BIT_LDOGEN1_LP_EN_SW |
 158                 //BIT_LDOWIFIPA_LP_EN_SW |
 159                 //BIT_LDOVDD28_LP_EN_SW |
 160                 //BIT_LDOVDD18_LP_EN_SW |
 161                 0
 162         );
 163         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 164                 BIT_SLP_XTLBUF_PD_EN |
 165                 BIT_XTL_EN |
 166                 BITS_XTL_WAIT(0x32) |
 167                 0
 168         );
 169
 170         /****************************************
 171         *   Following is CP LDO Sleep Control  *
 172         ****************************************/
 173         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 174                 BIT_LDO_XTL_EN |
 175                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 176                 //BIT_LDO_GEN0_XTL1_EN |
 177                 //BIT_LDO_GEN0_XTL0_EN |
 178                 //BIT_LDO_GEN1_EXT_XTL0_EN |
 179                 //BIT_LDO_GEN1_XTL1_EN |
 180                 //BIT_LDO_GEN1_XTL0_EN |
 181                 BIT_LDO_DCXO_EXT_XTL0_EN |
 182                 BIT_LDO_DCXO_XTL1_EN |
 183                 BIT_LDO_DCXO_XTL0_EN |
 184                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 185                 //BIT_LDO_VDD18_XTL1_EN |
 186                 //BIT_LDO_VDD18_XTL0_EN |
 187                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 188                 //BIT_LDO_VDD28_XTL1_EN |
 189                 //BIT_LDO_VDD28_XTL0_EN |
 190                 0
 191         );
 192         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 193                 BIT_LDO_RF0_EXT_XTL0_EN |
 194                 BIT_LDO_RF0_XTL1_EN |
 195                 BIT_LDO_RF0_XTL0_EN |
 196                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 197                 BIT_LDO_WIFIPA_XTL1_EN |
 198                 BIT_LDO_WIFIPA_XTL0_EN |
 199                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 200                 //BIT_LDO_SIM2_XTL1_EN |
 201                 //BIT_LDO_SIM2_XTL0_EN |
 202                 //BIT_LDO_SIM1_EXT_XTL0_EN |
 203                 //BIT_LDO_SIM1_XTL1_EN |
 204                 //BIT_LDO_SIM1_XTL0_EN |
 205                 //BIT_LDO_SIM0_EXT_XTL0_EN |
 206                 //BIT_LDO_SIM0_XTL1_EN |
 207                 //BIT_LDO_SIM0_XTL0_EN |
 208                 0
 209         );
 210         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 211                 BIT_LDO_VDD25_EXT_XTL0_EN |
 212                 BIT_LDO_VDD25_XTL1_EN |
 213                 BIT_LDO_VDD25_XTL0_EN |
 214                 BIT_DCDC_RF_EXT_XTL0_EN |
 215                 BIT_DCDC_RF_XTL1_EN |
 216                 BIT_DCDC_RF_XTL0_EN |
 217                 BIT_XO_EXT_XTL0_EN |
 218                 BIT_XO_XTL1_EN |
 219                 BIT_XO_XTL0_EN |
 220                 BIT_BG_EXT_XTL0_EN |
 221                 BIT_BG_XTL1_EN |
 222                 BIT_BG_XTL0_EN |
 223                 0
 224         );
 225         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 226                 BIT_DCDC_CON_EXT_XTL0_EN |
 227                 BIT_DCDC_CON_XTL1_EN |
 228                 BIT_DCDC_CON_XTL0_EN |
 229                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 230                 //BIT_DCDC_WPA_XTL1_EN |
 231                 //BIT_DCDC_WPA_XTL0_EN |
 232                 BIT_DCDC_MEM_EXT_XTL0_EN |
 233                 BIT_DCDC_MEM_XTL1_EN |
 234                 BIT_DCDC_MEM_XTL0_EN |
 235                 BIT_DCDC_GEN_EXT_XTL0_EN |
 236                 BIT_DCDC_GEN_XTL1_EN |
 237                 BIT_DCDC_GEN_XTL0_EN |
 238                 BIT_DCDC_CORE_EXT_XTL0_EN |
 239                 BIT_DCDC_CORE_XTL1_EN |
 240                 BIT_DCDC_CORE_XTL0_EN |
 241                 0
 242         );
 243
 244         /*add by sam.sun, vddsim2 value 2.8v, bit15~bit8:a0*/
 245         ANA_REG_SET(ANA_REG_GLB_LDO_V_CTRL5,
 246                 BITS_LDO_SIM2_V(0xa0) |
 247                 0
 248         );
 249 #endif
 250         /************************************************
 251         *   Following is AP/CP LDO D DIE Sleep Control   *
 252         *************************************************/
 253
 254         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 255                 BIT_XTL0_AP_SEL |
 256                 BIT_XTL0_CP0_SEL |
 257                 BIT_XTL0_CP1_SEL |
 258                 BIT_XTL0_CP2_SEL |
 259                 0
 260         );
 261
 262         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 263                 BIT_XTL1_AP_SEL |
 264                 //BIT_XTL1_CP0_SEL |
 265                 BIT_XTL1_CP1_SEL |
 266                 BIT_XTL1_CP2_SEL |
 267                 0
 268         );
 269
 270         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 271                 //BIT_XTL2_AP_SEL |
 272                 //BIT_XTL2_CP0_SEL |
 273                 //BIT_XTL2_CP1_SEL |
 274                 BIT_XTL2_CP2_SEL |
 275                 0
 276         );
 277
 278         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 279                 BIT_XTLBUF0_CP2_SEL |
 280                 BIT_XTLBUF0_CP1_SEL |
 281                 BIT_XTLBUF0_CP0_SEL |
 282                 BIT_XTLBUF0_AP_SEL  |
 283                 0
 284         );
 285
 286         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 287                 BIT_XTLBUF1_CP2_SEL |
 288                 BIT_XTLBUF1_CP1_SEL |
 289                 BIT_XTLBUF1_CP0_SEL |
 290                 BIT_XTLBUF1_AP_SEL  |
 291                 0
 292         );
 293
 294         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 295                 //BIT_MPLL_REF_SEL |
 296                 //BIT_MPLL_CP2_SEL |
 297                 //BIT_MPLL_CP1_SEL |
 298                 //BIT_MPLL_CP0_SEL |
 299                 BIT_MPLL_AP_SEL  |
 300                 0
 301         );
 302
 303         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 304                 //BIT_DPLL_REF_SEL |
 305                 BIT_DPLL_CP2_SEL |
 306                 BIT_DPLL_CP1_SEL |
 307                 BIT_DPLL_CP0_SEL |
 308                 BIT_DPLL_AP_SEL  |
 309                 0
 310         );
 311         /*caution tdpll & wpll sel config in spl*/
 312         reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 313         reg_val &= ~0xF;
 314         reg_val |= (
 315                    BIT_TDPLL_CP2_SEL|
 316                    BIT_TDPLL_CP1_SEL|
 317                    BIT_TDPLL_CP0_SEL|
 318                    BIT_TDPLL_AP_SEL |
 319                    0);
 320         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
 321
 322         reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
 323         reg_val &= ~0xF;
 324         reg_val |= (
 325                    //BIT_WPLL_CP2_SEL|
 326                    //BIT_WPLL_CP1_SEL|
 327                    BIT_WPLL_CP0_SEL|
 328                    //BIT_WPLL_AP_SEL |
 329                    0);
 330         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
 331
 332         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 333                 //BIT_CPLL_REF_SEL |
 334                 BIT_CPLL_CP2_SEL |
 335                 BIT_CPLL_CP1_SEL |
 336                 BIT_CPLL_CP0_SEL |
 337                 BIT_CPLL_AP_SEL  |
 338                 0
 339         );
 340
 341         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 342                 //BIT_WIFIPLL1_REF_SEL |
 343                 BIT_WIFIPLL1_CP2_SEL |
 344                 //BIT_WIFIPLL1_CP1_SEL |
 345                 //BIT_WIFIPLL1_CP0_SEL |
 346                 //BIT_WIFIPLL1_AP_SEL |
 347                 0
 348         );
 349
 350         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 351                 //BIT_WIFIPLL2_REF_SEL |
 352                 BIT_WIFIPLL2_CP2_SEL |
 353                 //BIT_WIFIPLL2_CP1_SEL |
 354                 //BIT_WIFIPLL2_CP0_SEL |
 355                 //BIT_WIFIPLL2_AP_SEL |
 356                 0
 357         );
 358
 359         /*chip service package init*/
 360         CSP_Init(0);
 361         init_ldo_voltage();
 362 }
 363
 364 int init_ldo_voltage(void)
 365 {
 366     regulator_set_voltage("vddgen",2100);
 367     return 0;
 368 }