board/spreadtrum/sp5735/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30
  31         ANA_REG_OR(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, (BIT_LDO_RF1_PD_RTCSET));
  32         ANA_REG_AND(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, (~(BIT_LDO_RF1_PD_RTCSET)));
  33
  34         ANA_REG_OR(ANA_REG_GLB_LDO_PD_CTRL, (BIT_DCDC_WPA_PD));
  35
  36         /**********************************************
  37          *   Following is AP LDO A DIE Sleep Control  *
  38          *********************************************/
  39         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
  40                 BIT_SLP_IO_EN |
  41                 BIT_SLP_DCDC_OTP_PD_EN |
  42                 //BIT_SLP_DCDCGEN_PD_EN |
  43                 //BIT_SLP_DCDCWPA_PD_EN |
  44                 BIT_SLP_DCDCWRF_PD_EN |
  45                 BIT_SLP_DCDCARM_PD_EN |
  46                 BIT_SLP_LDOEMMCCORE_PD_EN |
  47                 BIT_SLP_LDOEMMCIO_PD_EN |
  48                 BIT_SLP_LDORF2_PD_EN |
  49                 //BIT_SLP_LDORF1_PD_EN |
  50                 BIT_SLP_LDORF0_PD_EN |
  51                 BIT_SLP_LDOVDD25_PD_EN |
  52                 //BIT_SLP_LDOVDD28_PD_EN |
  53                 //BIT_SLP_LDOVDD18_PD_EN |
  54                 0
  55         );
  56
  57         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
  58                 BIT_SLP_LDO_PD_EN |
  59                 BIT_SLP_LDOLPREF_PD_EN |
  60                 BIT_SLP_LDOCLSG_PD_EN |
  61                 BIT_SLP_LDOUSB_PD_EN |
  62                 BIT_SLP_LDOCAMMOT_PD_EN |
  63                 BIT_SLP_LDOCAMIO_PD_EN |
  64                 BIT_SLP_LDOCAMD_PD_EN |
  65                 BIT_SLP_LDOCAMA_PD_EN |
  66                 BIT_SLP_LDOSIM2_PD_EN |
  67                 //BIT_SLP_LDOSIM1_PD_EN |
  68                 //BIT_SLP_LDOSIM0_PD_EN |
  69                 BIT_SLP_LDOSD_PD_EN |
  70                 BIT_SLP_LDOAVDD18_PD_EN |
  71                 0
  72         );
  73
  74         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
  75                 //BIT_SLP_DCDC_BG_LP_EN |
  76                 //BIT_SLP_DCDCCORE_LP_EN |
  77                 //BIT_SLP_DCDCMEM_LP_EN |
  78                 //BIT_SLP_DCDCARM_LP_EN |
  79                 //BIT_SLP_DCDCGEN_LP_EN |
  80                 //BIT_SLP_DCDCWPA_LP_EN |
  81                 //BIT_SLP_DCDCWRF_LP_EN |
  82                 //BIT_SLP_LDOEMMCCORE_LP_EN |
  83                 //BIT_SLP_LDOEMMCIO_LP_EN |
  84                 //BIT_SLP_LDORF2_LP_EN |
  85                 //BIT_SLP_LDORF1_LP_EN |
  86                 //BIT_SLP_LDORF0_LP_EN |
  87                 0
  88         );
  89
  90         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
  91                 //BIT_SLP_BG_LP_EN |
  92                 //BIT_SLP_LDOVDD25_LP_EN |
  93                 //BIT_SLP_LDOVDD28_LP_EN |
  94                 //BIT_SLP_LDOVDD18_LP_EN |
  95                 //BIT_SLP_LDOCLSG_LP_EN |
  96                 //BIT_SLP_LDOUSB_LP_EN |
  97                 //BIT_SLP_LDOCAMMOT_LP_EN |
  98                 //BIT_SLP_LDOCAMIO_LP_EN |
  99                 //BIT_SLP_LDOCAMD_LP_EN |
 100                 //BIT_SLP_LDOCAMA_LP_EN |
 101                 //BIT_SLP_LDOSIM2_LP_EN |
 102                 //BIT_SLP_LDOSIM1_LP_EN |
 103                 //BIT_SLP_LDOSIM0_LP_EN |
 104                 //BIT_SLP_LDOSD_LP_EN |
 105                 //BIT_SLP_LDOAVDD18_LP_EN |
 106                 0
 107         );
 108
 109         /****************************************
 110         *   Following is CP LDO Sleep Control  *
 111         ****************************************/
 112
 113         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 114                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 115                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 116                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 117                 //BIT_LDO_VDD18_XTL2_EN     |
 118                 //BIT_LDO_VDD18_XTL1_EN     |
 119                 //BIT_LDO_VDD18_XTL0_EN     |
 120                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 121                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 122                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 123                 //BIT_LDO_VDD28_XTL2_EN     |
 124                 //BIT_LDO_VDD28_XTL1_EN     |
 125                 //BIT_LDO_VDD28_XTL0_EN     |
 126                 0
 127         );
 128
 129         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 130                 BIT_LDO_XTL_EN |
 131                 //BIT_LDO_RF1_EXT_XTL2_EN |
 132                 //BIT_LDO_RF1_EXT_XTL1_EN |
 133                 //BIT_LDO_RF1_EXT_XTL0_EN |
 134                 //BIT_LDO_RF1_XTL2_EN |
 135                 //BIT_LDO_RF1_XTL1_EN |
 136                 //BIT_LDO_RF1_XTL0_EN |
 137                 //BIT_LDO_RF0_EXT_XTL2_EN |
 138                 //BIT_LDO_RF0_EXT_XTL1_EN |
 139                 //BIT_LDO_RF0_EXT_XTL0_EN |
 140                 BIT_LDO_RF0_XTL2_EN |
 141                 BIT_LDO_RF0_XTL1_EN |
 142                 BIT_LDO_RF0_XTL0_EN |
 143                 0
 144         );
 145
 146         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 147                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 148                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 149                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 150                 BIT_LDO_VDD25_XTL2_EN |
 151                 BIT_LDO_VDD25_XTL1_EN |
 152                 BIT_LDO_VDD25_XTL0_EN |
 153                 //BIT_LDO_RF2_EXT_XTL2_EN |
 154                 //BIT_LDO_RF2_EXT_XTL1_EN |
 155                 //BIT_LDO_RF2_EXT_XTL0_EN |
 156                 BIT_LDO_RF2_XTL2_EN |
 157                 BIT_LDO_RF2_XTL1_EN |
 158                 BIT_LDO_RF2_XTL0_EN |
 159                 0
 160         );
 161
 162         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 163                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 164                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 165                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 166                 //BIT_LDO_AVDD18_XTL2_EN |
 167                 //BIT_LDO_AVDD18_XTL1_EN |
 168                 //BIT_LDO_AVDD18_XTL0_EN |
 169                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 170                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 171                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 172                 //BIT_LDO_SIM2_XTL2_EN |
 173                 //BIT_LDO_SIM2_XTL1_EN |
 174                 //BIT_LDO_SIM2_XTL0_EN |
 175                 0
 176         );
 177
 178         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 179                 //BIT_DCDC_BG_EXT_XTL2_EN |
 180                 //BIT_DCDC_BG_EXT_XTL1_EN |
 181                 //BIT_DCDC_BG_EXT_XTL0_EN |
 182                 BIT_DCDC_BG_XTL2_EN |
 183                 BIT_DCDC_BG_XTL1_EN |
 184                 BIT_DCDC_BG_XTL0_EN |
 185                 //BIT_BG_EXT_XTL2_EN |
 186                 //BIT_BG_EXT_XTL1_EN |
 187                 //BIT_BG_EXT_XTL0_EN |
 188                 //BIT_BG_XTL2_EN |
 189                 //BIT_BG_XTL1_EN |
 190                 //BIT_BG_XTL0_EN |
 191                 0
 192         );
 193
 194         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 195                 BIT_DCDC_WRF_XTL2_EN |
 196                 //BIT_DCDC_WRF_XTL1_EN |
 197                 BIT_DCDC_WRF_XTL0_EN |
 198                 //BIT_DCDC_WPA_XTL2_EN |
 199                 //BIT_DCDC_WPA_XTL1_EN |
 200                 //BIT_DCDC_WPA_XTL0_EN |
 201                 BIT_DCDC_MEM_XTL2_EN |
 202                 BIT_DCDC_MEM_XTL1_EN |
 203                 BIT_DCDC_MEM_XTL0_EN |
 204                 BIT_DCDC_GEN_XTL2_EN |
 205                 BIT_DCDC_GEN_XTL1_EN |
 206                 BIT_DCDC_GEN_XTL0_EN |
 207                 BIT_DCDC_CORE_XTL2_EN |
 208                 BIT_DCDC_CORE_XTL1_EN |
 209                 BIT_DCDC_CORE_XTL0_EN |
 210                 0
 211         );
 212
 213         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 214                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 215                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 216                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 217                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 218                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 219                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 220                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 221                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 222                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 223                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 224                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 225                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 226                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 227                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 228                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 229                 0
 230         );
 231
 232         /************************************************
 233         *   Following is AP/CP LDO D DIE Sleep Control   *
 234         *************************************************/
 235
 236         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 237                 BIT_XTL0_AP_SEL |
 238                 BIT_XTL0_CP0_SEL |
 239                 BIT_XTL0_CP1_SEL |
 240                 BIT_XTL0_CP2_SEL |
 241                 0
 242         );
 243
 244         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 245                 BIT_XTL1_AP_SEL |
 246                 BIT_XTL1_CP0_SEL |
 247                 BIT_XTL1_CP1_SEL |
 248                 BIT_XTL1_CP2_SEL |
 249                 0
 250         );
 251
 252         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 253                 BIT_XTL2_AP_SEL |
 254                 BIT_XTL2_CP0_SEL |
 255                 BIT_XTL2_CP1_SEL |
 256                 BIT_XTL2_CP2_SEL |
 257                 0
 258         );
 259
 260         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 261                 BIT_XTLBUF0_CP2_SEL |
 262                 BIT_XTLBUF0_CP1_SEL |
 263                 BIT_XTLBUF0_CP0_SEL |
 264                 BIT_XTLBUF0_AP_SEL  |
 265                 0
 266         );
 267
 268         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 269                 BIT_XTLBUF1_CP2_SEL |
 270                 BIT_XTLBUF1_CP1_SEL |
 271                 BIT_XTLBUF1_CP0_SEL |
 272                 BIT_XTLBUF1_AP_SEL  |
 273                 0
 274         );
 275
 276         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 277                 //BIT_MPLL_REF_SEL |
 278                 //BIT_MPLL_CP2_SEL |
 279                 //BIT_MPLL_CP1_SEL |
 280                 //BIT_MPLL_CP0_SEL |
 281                 BIT_MPLL_AP_SEL  |
 282                 0
 283         );
 284
 285         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 286                 //BIT_DPLL_REF_SEL |
 287                 BIT_DPLL_CP2_SEL |
 288                 BIT_DPLL_CP1_SEL |
 289                 BIT_DPLL_CP0_SEL |
 290                 BIT_DPLL_AP_SEL  |
 291                 0
 292         );
 293
 294         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 295                 //BIT_TDPLL_REF_SEL |
 296                 BIT_TDPLL_CP2_SEL |
 297                 BIT_TDPLL_CP1_SEL |
 298                 BIT_TDPLL_CP0_SEL |
 299                 BIT_TDPLL_AP_SEL  |
 300                 0
 301         );
 302
 303         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 304                 BIT_WPLL_REF_SEL |
 305                 //BIT_WPLL_CP2_SEL |
 306                 //BIT_WPLL_CP1_SEL |
 307                 BIT_WPLL_CP0_SEL |
 308                 //BIT_WPLL_AP_SEL  |
 309                 0
 310         );
 311
 312         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 313                 //BIT_CPLL_REF_SEL |
 314                 BIT_CPLL_CP2_SEL |
 315                 BIT_CPLL_CP1_SEL |
 316                 //BIT_CPLL_CP0_SEL |
 317                 //BIT_CPLL_AP_SEL  |
 318                 0
 319         );
 320
 321         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 322                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 323                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 324                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 325                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 326                 0
 327         );
 328
 329         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 330                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 331                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 332                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 333                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 334                 0
 335         );
 336
 337         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 338                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 339                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 340                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 341                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 342                 0
 343         );
 344
 345         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 346                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 347                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 348                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 349                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 350                 0
 351         );
 352
 353         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 354                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 355                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 356                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 357                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 358                 0
 359         );
 360
 361         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 362                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 363                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 364                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 365                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 366                 0
 367         );
 368
 369         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 370                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 371                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 372                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 373                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 374                 0
 375         );
 376
 377         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 378                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 379                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 380                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 381                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 382                 0
 383         );
 384
 385         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 386                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 387                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 388                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 389                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 390                 0
 391         );
 392
 393         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 394                 BITS_XTL1_WAIT_CNT(0x39)                |
 395                 BITS_XTL0_WAIT_CNT(0x39)                |
 396                 0
 397         );
 398
 399         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 400                 BITS_XTLBUF1_WAIT_CNT(7)                |
 401                 BITS_XTLBUF0_WAIT_CNT(7)                |
 402                 0
 403         );
 404
 405         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 406                 BITS_WPLL_WAIT_CNT(7)                   |
 407                 BITS_TDPLL_WAIT_CNT(7)                  |
 408                 BITS_DPLL_WAIT_CNT(7)                   |
 409                 BITS_MPLL_WAIT_CNT(7)                   |
 410                 0
 411         );
 412
 413         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 414                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 415                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 416                 BITS_CPLL_WAIT_CNT(7)                   |
 417                 0
 418         );
 419
 420         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 421                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 422                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 423                 0
 424         );
 425 }