board/spreadtrum/pikelfpga/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30 #if !defined(CONFIG_ARCH_SCX35L)
  31         /**********************************************
  32          *   Following is AP LDO A DIE Sleep Control  *
  33          *********************************************/
  34         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
  35                 BIT_SLP_IO_EN |
  36                 BIT_SLP_DCDC_OTP_PD_EN |
  37                 //BIT_SLP_DCDCGEN_PD_EN |
  38                 BIT_SLP_DCDCWPA_PD_EN |
  39                 BIT_SLP_DCDCWRF_PD_EN |
  40                 BIT_SLP_DCDCARM_PD_EN |
  41                 BIT_SLP_LDOEMMCCORE_PD_EN |
  42                 BIT_SLP_LDOEMMCIO_PD_EN |
  43                 BIT_SLP_LDORF2_PD_EN |
  44                 BIT_SLP_LDORF1_PD_EN |
  45                 BIT_SLP_LDORF0_PD_EN |
  46                 BIT_SLP_LDOVDD25_PD_EN |
  47                 //BIT_SLP_LDOVDD28_PD_EN |
  48                 //BIT_SLP_LDOVDD18_PD_EN |
  49                 0
  50         );
  51
  52         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
  53                 BIT_SLP_LDO_PD_EN |
  54                 BIT_SLP_LDOLPREF_PD_EN |
  55                 BIT_SLP_LDOCLSG_PD_EN |
  56                 BIT_SLP_LDOUSB_PD_EN |
  57                 BIT_SLP_LDOCAMMOT_PD_EN |
  58                 BIT_SLP_LDOCAMIO_PD_EN |
  59                 BIT_SLP_LDOCAMD_PD_EN |
  60                 BIT_SLP_LDOCAMA_PD_EN |
  61                 BIT_SLP_LDOSIM2_PD_EN |
  62                 //BIT_SLP_LDOSIM1_PD_EN |
  63                 //BIT_SLP_LDOSIM0_PD_EN |
  64                 BIT_SLP_LDOSD_PD_EN |
  65                 BIT_SLP_LDOAVDD18_PD_EN |
  66                 0
  67         );
  68
  69         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
  70                 //BIT_SLP_DCDC_BG_LP_EN |
  71                 //BIT_SLP_DCDCCORE_LP_EN |
  72                 //BIT_SLP_DCDCMEM_LP_EN |
  73                 //BIT_SLP_DCDCARM_LP_EN |
  74                 //BIT_SLP_DCDCGEN_LP_EN |
  75                 //BIT_SLP_DCDCWPA_LP_EN |
  76                 //BIT_SLP_DCDCWRF_LP_EN |
  77                 //BIT_SLP_LDOEMMCCORE_LP_EN |
  78                 //BIT_SLP_LDOEMMCIO_LP_EN |
  79                 //BIT_SLP_LDORF2_LP_EN |
  80                 //BIT_SLP_LDORF1_LP_EN |
  81                 //BIT_SLP_LDORF0_LP_EN |
  82                 0
  83         );
  84
  85         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
  86                 //BIT_SLP_BG_LP_EN |
  87                 //BIT_SLP_LDOVDD25_LP_EN |
  88                 //BIT_SLP_LDOVDD28_LP_EN |
  89                 //BIT_SLP_LDOVDD18_LP_EN |
  90                 //BIT_SLP_LDOCLSG_LP_EN |
  91                 //BIT_SLP_LDOUSB_LP_EN |
  92                 //BIT_SLP_LDOCAMMOT_LP_EN |
  93                 //BIT_SLP_LDOCAMIO_LP_EN |
  94                 //BIT_SLP_LDOCAMD_LP_EN |
  95                 //BIT_SLP_LDOCAMA_LP_EN |
  96                 //BIT_SLP_LDOSIM2_LP_EN |
  97                 //BIT_SLP_LDOSIM1_LP_EN |
  98                 //BIT_SLP_LDOSIM0_LP_EN |
  99                 //BIT_SLP_LDOSD_LP_EN |
 100                 //BIT_SLP_LDOAVDD18_LP_EN |
 101                 0
 102         );
 103
 104         /****************************************
 105         *   Following is CP LDO Sleep Control  *
 106         ****************************************/
 107
 108         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 109                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 110                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 111                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 112                 //BIT_LDO_VDD18_XTL2_EN     |
 113                 //BIT_LDO_VDD18_XTL1_EN     |
 114                 //BIT_LDO_VDD18_XTL0_EN     |
 115                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 116                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 117                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 118                 //BIT_LDO_VDD28_XTL2_EN     |
 119                 //BIT_LDO_VDD28_XTL1_EN     |
 120                 //BIT_LDO_VDD28_XTL0_EN     |
 121                 0
 122         );
 123
 124         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 125                 BIT_LDO_XTL_EN |
 126                 //BIT_LDO_RF1_EXT_XTL2_EN |
 127                 //BIT_LDO_RF1_EXT_XTL1_EN |
 128                 //BIT_LDO_RF1_EXT_XTL0_EN |
 129                 //BIT_LDO_RF1_XTL2_EN |
 130                 BIT_LDO_RF1_XTL1_EN |
 131                 BIT_LDO_RF1_XTL0_EN |
 132                 //BIT_LDO_RF0_EXT_XTL2_EN |
 133                 //BIT_LDO_RF0_EXT_XTL1_EN |
 134                 //BIT_LDO_RF0_EXT_XTL0_EN |
 135                 BIT_LDO_RF0_XTL2_EN |
 136                 BIT_LDO_RF0_XTL1_EN |
 137                 BIT_LDO_RF0_XTL0_EN |
 138                 0
 139         );
 140
 141         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 142                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 143                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 144                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 145                 BIT_LDO_VDD25_XTL2_EN |
 146                 BIT_LDO_VDD25_XTL1_EN |
 147                 BIT_LDO_VDD25_XTL0_EN |
 148                 //BIT_LDO_RF2_EXT_XTL2_EN |
 149                 //BIT_LDO_RF2_EXT_XTL1_EN |
 150                 //BIT_LDO_RF2_EXT_XTL0_EN |
 151                 //BIT_LDO_RF2_XTL2_EN |
 152                 //BIT_LDO_RF2_XTL1_EN |
 153                 //BIT_LDO_RF2_XTL0_EN |
 154                 0
 155         );
 156
 157         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 158                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 159                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 160                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 161                 //BIT_LDO_AVDD18_XTL2_EN |
 162                 //BIT_LDO_AVDD18_XTL1_EN |
 163                 //BIT_LDO_AVDD18_XTL0_EN |
 164                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 165                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 166                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 167                 //BIT_LDO_SIM2_XTL2_EN |
 168                 //BIT_LDO_SIM2_XTL1_EN |
 169                 //BIT_LDO_SIM2_XTL0_EN |
 170                 0
 171         );
 172
 173         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 174                 //BIT_DCDC_BG_EXT_XTL2_EN |
 175                 //BIT_DCDC_BG_EXT_XTL1_EN |
 176                 //BIT_DCDC_BG_EXT_XTL0_EN |
 177                 BIT_DCDC_BG_XTL2_EN |
 178                 BIT_DCDC_BG_XTL1_EN |
 179                 BIT_DCDC_BG_XTL0_EN |
 180                 //BIT_BG_EXT_XTL2_EN |
 181                 //BIT_BG_EXT_XTL1_EN |
 182                 //BIT_BG_EXT_XTL0_EN |
 183                 //BIT_BG_XTL2_EN |
 184                 //BIT_BG_XTL1_EN |
 185                 //BIT_BG_XTL0_EN |
 186                 0
 187         );
 188
 189         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 190                 BIT_DCDC_WRF_XTL2_EN |
 191                 //BIT_DCDC_WRF_XTL1_EN |
 192                 BIT_DCDC_WRF_XTL0_EN |
 193                 //BIT_DCDC_WPA_XTL2_EN |
 194                 //BIT_DCDC_WPA_XTL1_EN |
 195                 BIT_DCDC_WPA_XTL0_EN |
 196                 BIT_DCDC_MEM_XTL2_EN |
 197                 BIT_DCDC_MEM_XTL1_EN |
 198                 BIT_DCDC_MEM_XTL0_EN |
 199                 BIT_DCDC_GEN_XTL2_EN |
 200                 BIT_DCDC_GEN_XTL1_EN |
 201                 BIT_DCDC_GEN_XTL0_EN |
 202                 BIT_DCDC_CORE_XTL2_EN |
 203                 BIT_DCDC_CORE_XTL1_EN |
 204                 BIT_DCDC_CORE_XTL0_EN |
 205                 0
 206         );
 207
 208         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 209                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 210                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 211                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 212                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 213                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 214                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 215                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 216                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 217                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 218                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 219                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 220                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 221                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 222                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 223                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 224                 0
 225         );
 226
 227         /************************************************
 228         *   Following is AP/CP LDO D DIE Sleep Control   *
 229         *************************************************/
 230
 231         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 232                 BIT_XTL0_AP_SEL |
 233                 BIT_XTL0_CP0_SEL |
 234                 BIT_XTL0_CP1_SEL |
 235                 BIT_XTL0_CP2_SEL |
 236                 0
 237         );
 238
 239         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 240                 BIT_XTL1_AP_SEL |
 241                 BIT_XTL1_CP0_SEL |
 242                 BIT_XTL1_CP1_SEL |
 243                 //BIT_XTL1_CP2_SEL |
 244                 0
 245         );
 246
 247         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 248                 //BIT_XTL2_AP_SEL |
 249                 //BIT_XTL2_CP0_SEL |
 250                 //BIT_XTL2_CP1_SEL |
 251                 //BIT_XTL2_CP2_SEL |
 252                 0
 253         );
 254
 255         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 256                 BIT_XTLBUF0_CP2_SEL |
 257                 BIT_XTLBUF0_CP1_SEL |
 258                 BIT_XTLBUF0_CP0_SEL |
 259                 BIT_XTLBUF0_AP_SEL  |
 260                 0
 261         );
 262
 263         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 264                 //BIT_XTLBUF1_CP2_SEL |
 265                 BIT_XTLBUF1_CP1_SEL |
 266                 BIT_XTLBUF1_CP0_SEL |
 267                 BIT_XTLBUF1_AP_SEL  |
 268                 0
 269         );
 270
 271         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 272                 //BIT_MPLL_REF_SEL |
 273                 //BIT_MPLL_CP2_SEL |
 274                 //BIT_MPLL_CP1_SEL |
 275                 //BIT_MPLL_CP0_SEL |
 276                 BIT_MPLL_AP_SEL  |
 277                 0
 278         );
 279
 280         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 281                 //BIT_DPLL_REF_SEL |
 282                 BIT_DPLL_CP2_SEL |
 283                 BIT_DPLL_CP1_SEL |
 284                 BIT_DPLL_CP0_SEL |
 285                 BIT_DPLL_AP_SEL  |
 286                 0
 287         );
 288
 289         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 290                 //BIT_TDPLL_REF_SEL |
 291                 BIT_TDPLL_CP2_SEL |
 292                 BIT_TDPLL_CP1_SEL |
 293                 BIT_TDPLL_CP0_SEL |
 294                 BIT_TDPLL_AP_SEL  |
 295                 0
 296         );
 297
 298         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 299                 //BIT_WPLL_REF_SEL |
 300                 //BIT_WPLL_CP2_SEL |
 301                 //BIT_WPLL_CP1_SEL |
 302                 BIT_WPLL_CP0_SEL |
 303                 //BIT_WPLL_AP_SEL  |
 304                 0
 305         );
 306
 307         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 308                 //BIT_CPLL_REF_SEL |
 309                 BIT_CPLL_CP2_SEL |
 310                 BIT_CPLL_CP1_SEL |
 311                 //BIT_CPLL_CP0_SEL |
 312                 BIT_CPLL_AP_SEL  |
 313                 0
 314         );
 315
 316         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 317                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 318                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 319                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 320                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 321                 0
 322         );
 323
 324         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 325                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 326                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 327                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 328                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 329                 0
 330         );
 331
 332         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 333                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 334                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 335                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 336                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 337                 0
 338         );
 339
 340         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 341                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 342                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 343                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 344                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 345                 0
 346         );
 347
 348         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 349                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 350                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 351                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 352                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 353                 0
 354         );
 355
 356         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 357                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 358                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 359                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 360                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 361                 0
 362         );
 363
 364         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 365                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 366                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 367                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 368                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 369                 0
 370         );
 371
 372         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 373                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 374                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 375                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 376                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 377                 0
 378         );
 379
 380         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 381                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 382                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 383                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 384                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 385                 0
 386         );
 387
 388         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 389                 BITS_XTL1_WAIT_CNT(0x39)                |
 390                 BITS_XTL0_WAIT_CNT(0x39)                |
 391                 0
 392         );
 393
 394         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 395                 BITS_XTLBUF1_WAIT_CNT(7)                |
 396                 BITS_XTLBUF0_WAIT_CNT(7)                |
 397                 0
 398         );
 399
 400         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 401                 BITS_WPLL_WAIT_CNT(7)                   |
 402                 BITS_TDPLL_WAIT_CNT(7)                  |
 403                 BITS_DPLL_WAIT_CNT(7)                   |
 404                 BITS_MPLL_WAIT_CNT(7)                   |
 405                 0
 406         );
 407
 408         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 409                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 410                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 411                 BITS_CPLL_WAIT_CNT(7)                   |
 412                 0
 413         );
 414
 415         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 416                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 417                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 418                 0
 419         );
 420 #endif
 421 }