board/amcc/ebony/ebony.c

   1 /*
   2  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  28 #define FLASH_ONBD_N            2       /* 00000010 */
  29 #define FLASH_SRAM_SEL          1       /* 00000001 */
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 long int fixed_sdram(void);
  34
  35 int board_early_init_f(void)
  36 {
  37         uint reg;
  38         unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
  39         unsigned char status;
  40
  41         /*--------------------------------------------------------------------
  42          * Setup the external bus controller/chip selects
  43          *-------------------------------------------------------------------*/
  44         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  45         reg = mfdcr(EBC0_CFGDATA);
  46         mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
  47
  48         mtebc(PB1AP, 0x02815480);       /* NVRAM/RTC */
  49         mtebc(PB1CR, 0x48018000);       /* BA=0x480 1MB R/W 8-bit */
  50         mtebc(PB7AP, 0x01015280);       /* FPGA registers */
  51         mtebc(PB7CR, 0x48318000);       /* BA=0x483 1MB R/W 8-bit */
  52
  53         /* read FPGA_REG0  and set the bus controller */
  54         status = *fpga_base;
  55         if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
  56                 mtebc(PB0AP, 0x9b015480);       /* FLASH/SRAM */
  57                 mtebc(PB0CR, 0xfff18000);       /* BAS=0xfff 1MB R/W 8-bit */
  58                 mtebc(PB2AP, 0x9b015480);       /* 4MB FLASH */
  59                 mtebc(PB2CR, 0xff858000);       /* BAS=0xff8 4MB R/W 8-bit */
  60         } else {
  61                 mtebc(PB0AP, 0x9b015480);       /* 4MB FLASH */
  62                 mtebc(PB0CR, 0xffc58000);       /* BAS=0xffc 4MB R/W 8-bit */
  63
  64                 /* set CS2 if FLASH_ONBD_N == 0 */
  65                 if (!(status & FLASH_ONBD_N)) {
  66                         mtebc(PB2AP, 0x9b015480);       /* FLASH/SRAM */
  67                         mtebc(PB2CR, 0xff818000);       /* BAS=0xff8 4MB R/W 8-bit */
  68                 }
  69         }
  70
  71         /*--------------------------------------------------------------------
  72          * Setup the interrupt controller polarities, triggers, etc.
  73          *-------------------------------------------------------------------*/
  74         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  75         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  76         mtdcr(UIC0CR, 0x00000009);      /* SMI & UIC1 crit are critical */
  77         mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  78         mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  79         mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  80         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  81
  82         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  83         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  84         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  85         mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  86         mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
  87         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
  88         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  89
  90         return 0;
  91 }
  92
  93 int checkboard(void)
  94 {
  95         char *s = getenv("serial#");
  96
  97         printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
  98         if (s != NULL) {
  99                 puts(", serial# ");
 100                 puts(s);
 101         }
 102         putc('\n');
 103
 104         return (0);
 105 }
 106
 107 phys_size_t initdram(int board_type)
 108 {
 109         long dram_size = 0;
 110
 111 #if defined(CONFIG_SPD_EEPROM)
 112         dram_size = spd_sdram();
 113 #else
 114         dram_size = fixed_sdram();
 115 #endif
 116         return dram_size;
 117 }
 118
 119 #if !defined(CONFIG_SPD_EEPROM)
 120 /*************************************************************************
 121  *  fixed sdram init -- doesn't use serial presence detect.
 122  *
 123  *  Assumes:    128 MB, non-ECC, non-registered
 124  *              PLB @ 133 MHz
 125  *
 126  ************************************************************************/
 127 long int fixed_sdram(void)
 128 {
 129         uint reg;
 130
 131         /*--------------------------------------------------------------------
 132          * Setup some default
 133          *------------------------------------------------------------------*/
 134         mtsdram(SDRAM0_UABBA, 0x00000000);      /* ubba=0 (default)             */
 135         mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
 136         mtsdram(SDRAM0_DEVOPT, 0x00000000);     /* dll=0 ds=0 (normal)          */
 137         mtsdram(SDRAM0_WDDCTR, 0x00000000);     /* wrcp=0 dcd=0                 */
 138         mtsdram(SDRAM0_CLKTR, 0x40000000);      /* clkp=1 (90 deg wr) dcdt=0    */
 139
 140         /*--------------------------------------------------------------------
 141          * Setup for board-specific specific mem
 142          *------------------------------------------------------------------*/
 143         /*
 144          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 145          */
 146         mtsdram(SDRAM0_B0CR, 0x000a4001);       /* SDBA=0x000 128MB, Mode 3, enabled */
 147         mtsdram(SDRAM0_TR0, 0x410a4012);        /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 148         /* RA=10 RD=3                       */
 149         mtsdram(SDRAM0_TR1, 0x8080082f);        /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 150         mtsdram(SDRAM0_RTR, 0x08200000);        /* Rate 15.625 ns @ 133 MHz PLB     */
 151         mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM    */
 152         udelay(400);            /* Delay 200 usecs (min)            */
 153
 154         /*--------------------------------------------------------------------
 155          * Enable the controller, then wait for DCEN to complete
 156          *------------------------------------------------------------------*/
 157         mtsdram(SDRAM0_CFG0, 0x86000000);       /* DCEN=1, PMUD=1, 64-bit           */
 158         for (;;) {
 159                 mfsdram(SDRAM0_MCSTS, reg);
 160                 if (reg & 0x80000000)
 161                         break;
 162         }
 163
 164         return (128 * 1024 * 1024);     /* 128 MB                           */
 165 }
 166 #endif                          /* !defined(CONFIG_SPD_EEPROM) */