1 /******************************************************************************
2 ** File Name: pinmap.h *
3 ** Author: Richard.Yang *
5 ** Copyright: 2004 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: This file defines the structure of pin map. *
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION *
13 ** 03/08/2004 Richard.Yang Create. *
14 ******************************************************************************/
19 #include "sci_types.h"
28 //int pin_init(pinmap_t * pinmap);
30 #define CTL_PIN_BASE (SPRD_PIN_PHYS)
32 #ifdef CONFIG_ARCH_SCX20L
34 /* registers definitions for controller CTL_PIN */
35 #define REG_PIN_CTRL0 ( 0x0000 )
36 #define REG_PIN_CTRL1 ( 0x0004 )
37 #define REG_PIN_CTRL2 ( 0x0008 )
38 #define REG_PIN_CTRL3 ( 0x000c )
39 #define REG_PIN_CTRL4 ( 0x0010 )
40 #define REG_PIN_CTRL5 ( 0x0014 )
41 #define REG_PIN_RFSDA0 ( 0x0020 )
42 #define REG_PIN_RFSCK0 ( 0x0024 )
43 #define REG_PIN_RFSEN0 ( 0x0028 )
44 #define REG_PIN_RFSDA1 ( 0x002c )
45 #define REG_PIN_RFSCK1 ( 0x0030 )
46 #define REG_PIN_RFSEN1 ( 0x0034 )
47 #define REG_PIN_RFCTL0 ( 0x0038 )
48 #define REG_PIN_RFCTL1 ( 0x003c )
49 #define REG_PIN_RFCTL2 ( 0x0040 )
50 #define REG_PIN_RFCTL3 ( 0x0044 )
51 #define REG_PIN_RFCTL4 ( 0x0048 )
52 #define REG_PIN_RFCTL5 ( 0x004c )
53 #define REG_PIN_RFCTL6 ( 0x0050 )
54 #define REG_PIN_RFCTL7 ( 0x0054 )
55 #define REG_PIN_RFCTL8 ( 0x0058 )
56 #define REG_PIN_RFCTL9 ( 0x005c )
57 #define REG_PIN_RFCTL10 ( 0x0060 )
58 #define REG_PIN_RFCTL11 ( 0x0064 )
59 #define REG_PIN_RFCTL12 ( 0x0068 )
60 #define REG_PIN_RFCTL13 ( 0x006c )
61 #define REG_PIN_RFCTL14 ( 0x0070 )
62 #define REG_PIN_RFCTL15 ( 0x0074 )
63 #define REG_PIN_RFCTL16 ( 0x0078 )
64 #define REG_PIN_RFCTL17 ( 0x007c )
65 #define REG_PIN_RFCTL18 ( 0x0080 )
66 #define REG_PIN_RFCTL19 ( 0x0084 )
67 #define REG_PIN_RFCTL20 ( 0x0088 )
68 #define REG_PIN_RFCTL21 ( 0x008c )
69 #define REG_PIN_RFCTL22 ( 0x0090 )
70 #define REG_PIN_RFCTL23 ( 0x0094 )
71 #define REG_PIN_RFCTL24 ( 0x0098 )
72 #define REG_PIN_RFCTL25 ( 0x009c )
73 #define REG_PIN_RFCTL26 ( 0x00a0 )
74 #define REG_PIN_RFCTL27 ( 0x00a4 )
75 #define REG_PIN_RFCTL28 ( 0x00a8 )
76 #define REG_PIN_RFCTL29 ( 0x00ac )
77 #define REG_PIN_RFFE_SCK0 ( 0x00b0 )
78 #define REG_PIN_RFFE_SDA0 ( 0x00b4 )
79 #define REG_PIN_XTL_EN ( 0x00b8 )
80 #define REG_PIN_SIMCLK0 ( 0x00bc )
81 #define REG_PIN_SIMDA0 ( 0x00c0 )
82 #define REG_PIN_SIMRST0 ( 0x00c4 )
83 #define REG_PIN_SIMCLK1 ( 0x00c8 )
84 #define REG_PIN_SIMDA1 ( 0x00cc )
85 #define REG_PIN_SIMRST1 ( 0x00d0 )
86 #define REG_PIN_SIMCLK2 ( 0x00d4 )
87 #define REG_PIN_SIMDA2 ( 0x00d8 )
88 #define REG_PIN_SIMRST2 ( 0x00dc )
89 #define REG_PIN_IIS1DI ( 0x00e0 )
90 #define REG_PIN_IIS1DO ( 0x00e4 )
91 #define REG_PIN_IIS1CLK ( 0x00e8 )
92 #define REG_PIN_IIS1LRCK ( 0x00ec )
93 #define REG_PIN_IIS0DI ( 0x00f0 )
94 #define REG_PIN_IIS0DO ( 0x00f4 )
95 #define REG_PIN_IIS0CLK ( 0x00f8 )
96 #define REG_PIN_IIS0LRCK ( 0x00fc )
97 #define REG_PIN_U0TXD ( 0x0100 )
98 #define REG_PIN_U0RXD ( 0x0104 )
99 #define REG_PIN_U0CTS ( 0x0108 )
100 #define REG_PIN_U0RTS ( 0x010c )
101 #define REG_PIN_U1TXD ( 0x0110 )
102 #define REG_PIN_U1RXD ( 0x0114 )
103 #define REG_PIN_U2TXD ( 0x0118 )
104 #define REG_PIN_U2RXD ( 0x011c )
105 #define REG_PIN_U3TXD ( 0x0120 )
106 #define REG_PIN_U3RXD ( 0x0124 )
107 #define REG_PIN_U3CTS ( 0x0128 )
108 #define REG_PIN_U3RTS ( 0x012c )
109 #define REG_PIN_U4TXD ( 0x0130 )
110 #define REG_PIN_U4RXD ( 0x0134 )
111 #define REG_PIN_PTEST ( 0x0138 )
112 #define REG_PIN_ANA_INT ( 0x013c )
113 #define REG_PIN_EXT_RST_B ( 0x0140 )
114 #define REG_PIN_CHIP_SLEEP ( 0x0144 )
115 #define REG_PIN_XTL_BUF_EN0 ( 0x0148 )
116 #define REG_PIN_XTL_BUF_EN1 ( 0x014c )
117 #define REG_PIN_CLK_32K ( 0x0150 )
118 #define REG_PIN_AUD_SCLK ( 0x0154 )
119 #define REG_PIN_AUD_ADD0 ( 0x0158 )
120 #define REG_PIN_AUD_ADSYNC ( 0x015c )
121 #define REG_PIN_AUD_DAD1 ( 0x0160 )
122 #define REG_PIN_AUD_DAD0 ( 0x0164 )
123 #define REG_PIN_AUD_DASYNC ( 0x0168 )
124 #define REG_PIN_ADI_D ( 0x016c )
125 #define REG_PIN_ADI_SYNC ( 0x0170 )
126 #define REG_PIN_ADI_SCLK ( 0x0174 )
127 #define REG_PIN_SD0_D3 ( 0x0178 )
128 #define REG_PIN_SD0_D2 ( 0x017c )
129 #define REG_PIN_SD0_CMD ( 0x0180 )
130 #define REG_PIN_SD0_D0 ( 0x0184 )
131 #define REG_PIN_SD0_D1 ( 0x0188 )
132 #define REG_PIN_SD0_CLK0 ( 0x018c )
133 #define REG_PIN_SD1_CLK ( 0x0190 )
134 #define REG_PIN_SD1_CMD ( 0x0194 )
135 #define REG_PIN_SD1_D0 ( 0x0198 )
136 #define REG_PIN_SD1_D1 ( 0x019c )
137 #define REG_PIN_SD1_D2 ( 0x01a0 )
138 #define REG_PIN_SD1_D3 ( 0x01a4 )
139 #define REG_PIN_TRACECLK ( 0x01a8 )
140 #define REG_PIN_TRACECTRL ( 0x01ac )
141 #define REG_PIN_TRACEDAT0 ( 0x01b0 )
142 #define REG_PIN_TRACEDAT1 ( 0x01b4 )
143 #define REG_PIN_TRACEDAT2 ( 0x01b8 )
144 #define REG_PIN_TRACEDAT3 ( 0x01bc )
145 #define REG_PIN_TRACEDAT4 ( 0x01c0 )
146 #define REG_PIN_TRACEDAT5 ( 0x01c4 )
147 #define REG_PIN_TRACEDAT6 ( 0x01c8 )
148 #define REG_PIN_TRACEDAT7 ( 0x01cc )
149 #define REG_PIN_LCM_RSTN ( 0x01d0 )
150 #define REG_PIN_DSI_TE ( 0x01d4 )
151 #define REG_PIN_MTDO_ARM ( 0x01d8 )
152 #define REG_PIN_MTDI_ARM ( 0x01dc )
153 #define REG_PIN_MTCK_ARM ( 0x01e0 )
154 #define REG_PIN_MTMS_ARM ( 0x01e4 )
155 #define REG_PIN_MTRST_N_ARM ( 0x01e8 )
156 #define REG_PIN_DTDO_LTE ( 0x01ec )
157 #define REG_PIN_DTDI_LTE ( 0x01f0 )
158 #define REG_PIN_DTCK_LTE ( 0x01f4 )
159 #define REG_PIN_DTMS_LTE ( 0x01f8 )
160 #define REG_PIN_DRTCK_LTE ( 0x01fc )
161 #define REG_PIN_NFWPN ( 0x0200 )
162 #define REG_PIN_NFRB ( 0x0204 )
163 #define REG_PIN_NFCLE ( 0x0208 )
164 #define REG_PIN_NFALE ( 0x020c )
165 #define REG_PIN_NFREN ( 0x0210 )
166 #define REG_PIN_NFD4 ( 0x0214 )
167 #define REG_PIN_NFD5 ( 0x0218 )
168 #define REG_PIN_NFD6 ( 0x021c )
169 #define REG_PIN_NFD7 ( 0x0220 )
170 #define REG_PIN_NFD10 ( 0x0224 )
171 #define REG_PIN_NFD11 ( 0x0228 )
172 #define REG_PIN_NFD14 ( 0x022c )
173 #define REG_PIN_NFCEN0 ( 0x0230 )
174 #define REG_PIN_NFWEN ( 0x0234 )
175 #define REG_PIN_NFD0 ( 0x0238 )
176 #define REG_PIN_NFD1 ( 0x023c )
177 #define REG_PIN_NFD2 ( 0x0240 )
178 #define REG_PIN_NFD3 ( 0x0244 )
179 #define REG_PIN_NFD8 ( 0x0248 )
180 #define REG_PIN_NFD9 ( 0x024c )
181 #define REG_PIN_NFD12 ( 0x0250 )
182 #define REG_PIN_NFD13 ( 0x0254 )
183 #define REG_PIN_NFD15 ( 0x0258 )
184 #define REG_PIN_CCIRD0 ( 0x025c )
185 #define REG_PIN_CCIRD1 ( 0x0260 )
186 #define REG_PIN_CMMCLK ( 0x0264 )
187 #define REG_PIN_CMPCLK ( 0x0268 )
188 #define REG_PIN_CMRST0 ( 0x026c )
189 #define REG_PIN_CMRST1 ( 0x0270 )
190 #define REG_PIN_CMPD0 ( 0x0274 )
191 #define REG_PIN_CMPD1 ( 0x0278 )
192 #define REG_PIN_SCL0 ( 0x027c )
193 #define REG_PIN_SDA0 ( 0x0280 )
194 #define REG_PIN_SPI2_CSN ( 0x0284 )
195 #define REG_PIN_SPI2_DO ( 0x0288 )
196 #define REG_PIN_SPI2_DI ( 0x028c )
197 #define REG_PIN_SPI2_CLK ( 0x0290 )
198 #define REG_PIN_SPI0_CSN ( 0x0294 )
199 #define REG_PIN_SPI0_DO ( 0x0298 )
200 #define REG_PIN_SPI0_DI ( 0x029c )
201 #define REG_PIN_SPI0_CLK ( 0x02a0 )
202 #define REG_PIN_MEMS_MIC_CLK0 ( 0x02a4 )
203 #define REG_PIN_MEMS_MIC_DATA0 ( 0x02a8 )
204 #define REG_PIN_MEMS_MIC_CLK1 ( 0x02ac )
205 #define REG_PIN_MEMS_MIC_DATA1 ( 0x02b0 )
206 #define REG_PIN_KEYOUT0 ( 0x02b4 )
207 #define REG_PIN_KEYOUT1 ( 0x02b8 )
208 #define REG_PIN_KEYOUT2 ( 0x02bc )
209 #define REG_PIN_KEYIN0 ( 0x02c0 )
210 #define REG_PIN_KEYIN1 ( 0x02c4 )
211 #define REG_PIN_KEYIN2 ( 0x02c8 )
212 #define REG_PIN_SCL2 ( 0x02cc )
213 #define REG_PIN_SDA2 ( 0x02d0 )
214 #define REG_PIN_CLK_AUX0 ( 0x02d4 )
215 #define REG_PIN_EXTINT0 ( 0x02d8 )
216 #define REG_PIN_EXTINT1 ( 0x02dc )
217 #define REG_PIN_SCL3 ( 0x02e0 )
218 #define REG_PIN_SDA3 ( 0x02e4 )
222 /* registers definitions for controller CTL_PIN */
223 #define REG_PIN_CTRL0 ( 0x0000 )
224 #define REG_PIN_CTRL1 ( 0x0004 )
225 #define REG_PIN_CTRL2 ( 0x0008 )
226 #define REG_PIN_CTRL3 ( 0x000c )
227 #define REG_PIN_CTRL4 ( 0x0010 )
228 #define REG_PIN_CTRL5 ( 0x0014 )
229 #define REG_PIN_RFSDA0 ( 0x0020 )
230 #define REG_PIN_RFSCK0 ( 0x0024 )
231 #define REG_PIN_RFSEN0 ( 0x0028 )
232 #define REG_PIN_RFSDA1 ( 0x002c )
233 #define REG_PIN_RFSCK1 ( 0x0030 )
234 #define REG_PIN_RFSEN1 ( 0x0034 )
235 #define REG_PIN_RFCTL15 ( 0x0038 )
236 #define REG_PIN_RFCTL16 ( 0x003c )
237 #define REG_PIN_RFCTL17 ( 0x0040 )
238 #define REG_PIN_RFCTL18 ( 0x0044 )
239 #define REG_PIN_RFCTL19 ( 0x0048 )
240 #define REG_PIN_RFCTL20 ( 0x004c )
241 #define REG_PIN_RFCTL21 ( 0x0050 )
242 #define REG_PIN_RFCTL22 ( 0x0054 )
243 #define REG_PIN_RFCTL23 ( 0x0058 )
244 #define REG_PIN_RFCTL24 ( 0x005c )
245 #define REG_PIN_RFCTL25 ( 0x0060 )
246 #define REG_PIN_RFCTL26 ( 0x0064 )
247 #define REG_PIN_RFCTL0 ( 0x0068 )
248 #define REG_PIN_RFCTL1 ( 0x006c )
249 #define REG_PIN_RFCTL2 ( 0x0070 )
250 #define REG_PIN_RFCTL3 ( 0x0074 )
251 #define REG_PIN_RFCTL4 ( 0x0078 )
252 #define REG_PIN_RFCTL5 ( 0x007c )
253 #define REG_PIN_RFCTL6 ( 0x0080 )
254 #define REG_PIN_RFCTL7 ( 0x0084 )
255 #define REG_PIN_RFCTL8 ( 0x0088 )
256 #define REG_PIN_RFCTL9 ( 0x008c )
257 #define REG_PIN_RFCTL10 ( 0x0090 )
258 #define REG_PIN_RFCTL11 ( 0x0094 )
259 #define REG_PIN_RFCTL12 ( 0x0098 )
260 #define REG_PIN_RFCTL13 ( 0x009c )
261 #define REG_PIN_RFCTL14 ( 0x00a0 )
262 #define REG_PIN_RFCTL27 ( 0x00a4 )
263 #define REG_PIN_XTL_EN ( 0x00a8 )
264 #define REG_PIN_RFFE_SCK0 ( 0x00ac )
265 #define REG_PIN_RFFE_SDA0 ( 0x00b0 )
266 #define REG_PIN_RFCTL28 ( 0x00b4 )
267 #define REG_PIN_RFCTL29 ( 0x00b8 )
268 #define REG_PIN_SIMCLK0 ( 0x00bc )
269 #define REG_PIN_SIMDA0 ( 0x00c0 )
270 #define REG_PIN_SIMRST0 ( 0x00c4 )
271 #define REG_PIN_SIMCLK1 ( 0x00c8 )
272 #define REG_PIN_SIMDA1 ( 0x00cc )
273 #define REG_PIN_SIMRST1 ( 0x00d0 )
274 #define REG_PIN_SIMCLK2 ( 0x00d4 )
275 #define REG_PIN_SIMDA2 ( 0x00d8 )
276 #define REG_PIN_SIMRST2 ( 0x00dc )
277 #define REG_PIN_SD0_D3 ( 0x00e0 )
278 #define REG_PIN_SD0_D2 ( 0x00e4 )
279 #define REG_PIN_SD0_CMD ( 0x00e8 )
280 #define REG_PIN_SD0_D0 ( 0x00ec )
281 #define REG_PIN_SD0_D1 ( 0x00f0 )
282 #define REG_PIN_SD0_CLK0 ( 0x00f4 )
283 #define REG_PIN_SD1_CLK ( 0x00f8 )
284 #define REG_PIN_SD1_CMD ( 0x00fc )
285 #define REG_PIN_SD1_D0 ( 0x0100 )
286 #define REG_PIN_SD1_D1 ( 0x0104 )
287 #define REG_PIN_SD1_D2 ( 0x0108 )
288 #define REG_PIN_SD1_D3 ( 0x010c )
289 #define REG_PIN_IIS0DI ( 0x0110 )
290 #define REG_PIN_IIS0DO ( 0x0114 )
291 #define REG_PIN_IIS0CLK ( 0x0118 )
292 #define REG_PIN_IIS0LRCK ( 0x011c )
293 #define REG_PIN_U0TXD ( 0x0120 )
294 #define REG_PIN_U0RXD ( 0x0124 )
295 #define REG_PIN_U0CTS ( 0x0128 )
296 #define REG_PIN_U0RTS ( 0x012c )
297 #define REG_PIN_PTEST ( 0x0130 )
298 #define REG_PIN_ANA_INT ( 0x0134 )
299 #define REG_PIN_EXT_RST_B ( 0x0138 )
300 #define REG_PIN_CHIP_SLEEP ( 0x013c )
301 #define REG_PIN_XTL_BUF_EN0 ( 0x0140 )
302 #define REG_PIN_XTL_BUF_EN1 ( 0x0144 )
303 #define REG_PIN_CLK_32K ( 0x0148 )
304 #define REG_PIN_AUD_SCLK ( 0x014c )
305 #define REG_PIN_AUD_ADD0 ( 0x0150 )
306 #define REG_PIN_AUD_ADSYNC ( 0x0154 )
307 #define REG_PIN_AUD_DAD1 ( 0x0158 )
308 #define REG_PIN_AUD_DAD0 ( 0x015C )
309 #define REG_PIN_AUD_DASYNC ( 0x0160 )
310 #define REG_PIN_ADI_D ( 0x0164 )
311 #define REG_PIN_ADI_SYNC ( 0x0168 )
312 #define REG_PIN_ADI_SCLK ( 0x016c )
313 #define REG_PIN_LCM_RSTN ( 0x0170 )
314 #define REG_PIN_DSI_TE ( 0x0174 )
315 #define REG_PIN_MTDO_ARM ( 0x0178 )
316 #define REG_PIN_MTDI_ARM ( 0x017c )
317 #define REG_PIN_MTCK_ARM ( 0x0180 )
318 #define REG_PIN_MTMS_ARM ( 0x0184 )
319 #define REG_PIN_MTRST_N_ARM ( 0x0188 )
320 #define REG_PIN_DTDO_LTE ( 0x018c )
321 #define REG_PIN_DTDI_LTE ( 0x0190 )
322 #define REG_PIN_DTCK_LTE ( 0x0194 )
323 #define REG_PIN_DTMS_LTE ( 0x0198 )
324 #define REG_PIN_DRTCK_LTE ( 0x019c )
325 #define REG_PIN_NFWPN ( 0x01a0 )
326 #define REG_PIN_NFRB ( 0x01a4 )
327 #define REG_PIN_NFCLE ( 0x01a8 )
328 #define REG_PIN_NFALE ( 0x01ac )
329 #define REG_PIN_NFREN ( 0x01b0 )
330 #define REG_PIN_NFD4 ( 0x01b4 )
331 #define REG_PIN_NFD5 ( 0x01b8 )
332 #define REG_PIN_NFD6 ( 0x01bc )
333 #define REG_PIN_NFD7 ( 0x01c0 )
334 #define REG_PIN_NFD10 ( 0x01c4 )
335 #define REG_PIN_NFD11 ( 0x01c8 )
336 #define REG_PIN_NFD14 ( 0x01cc )
337 #define REG_PIN_NFCEN0 ( 0x01d0 )
338 #define REG_PIN_NFWEN ( 0x01d4 )
339 #define REG_PIN_NFD0 ( 0x01d8 )
340 #define REG_PIN_NFD1 ( 0x01dc )
341 #define REG_PIN_NFD2 ( 0x01e0 )
342 #define REG_PIN_NFD3 ( 0x01e4 )
343 #define REG_PIN_NFD8 ( 0x01e8 )
344 #define REG_PIN_NFD9 ( 0x01ec )
345 #define REG_PIN_NFD12 ( 0x01f0 )
346 #define REG_PIN_NFD13 ( 0x01f4 )
347 #define REG_PIN_NFD15 ( 0x01f8 )
348 #define REG_PIN_CCIRD0 ( 0x01fc )
349 #define REG_PIN_CCIRD1 ( 0x0200 )
350 #define REG_PIN_CMMCLK ( 0x0204 )
351 #define REG_PIN_CMPCLK ( 0x0208 )
352 #define REG_PIN_CMRST0 ( 0x020C )
353 #define REG_PIN_CMRST1 ( 0x0210 )
354 #define REG_PIN_CMPD0 ( 0x0214 )
355 #define REG_PIN_CMPD1 ( 0x0218 )
356 #define REG_PIN_SCL0 ( 0x021c )
357 #define REG_PIN_SDA0 ( 0x0220 )
358 #define REG_PIN_SPI2_CSN ( 0x0224 )
359 #define REG_PIN_SPI2_DO ( 0x0228 )
360 #define REG_PIN_SPI2_DI ( 0x022c )
361 #define REG_PIN_SPI2_CLK ( 0x0230 )
362 #define REG_PIN_SPI0_CSN ( 0x0234 )
363 #define REG_PIN_SPI0_DO ( 0x0238 )
364 #define REG_PIN_SPI0_DI ( 0x023c )
365 #define REG_PIN_SPI0_CLK ( 0x0240 )
366 #define REG_PIN_MEMS_MIC_CLK0 ( 0x0244 )
367 #define REG_PIN_MEMS_MIC_DATA0 ( 0x0248 )
368 #define REG_PIN_MEMS_MIC_CLK1 ( 0x024c )
369 #define REG_PIN_MEMS_MIC_DATA1 ( 0x0250 )
370 #define REG_PIN_KEYOUT0 ( 0x0254 )
371 #define REG_PIN_KEYOUT1 ( 0x0258 )
372 #define REG_PIN_KEYOUT2 ( 0x025c )
373 #define REG_PIN_KEYIN0 ( 0x0260 )
374 #define REG_PIN_KEYIN1 ( 0x0264 )
375 #define REG_PIN_KEYIN2 ( 0x0268 )
376 #define REG_PIN_SCL2 ( 0x026c )
377 #define REG_PIN_SDA2 ( 0x0270 )
378 #define REG_PIN_CLK_AUX0 ( 0x0274 )
379 #define REG_PIN_IIS1DI ( 0x0278 )
380 #define REG_PIN_IIS1DO ( 0x027c )
381 #define REG_PIN_IIS1CLK ( 0x0280 )
382 #define REG_PIN_IIS1LRCK ( 0x0284 )
383 #define REG_PIN_TRACECLK ( 0x0288 )
384 #define REG_PIN_TRACECTRL ( 0x028c )
385 #define REG_PIN_TRACEDAT0 ( 0x0290 )
386 #define REG_PIN_TRACEDAT1 ( 0x0294 )
387 #define REG_PIN_TRACEDAT2 ( 0x0298 )
388 #define REG_PIN_TRACEDAT3 ( 0x029c )
389 #define REG_PIN_TRACEDAT4 ( 0x02a0 )
390 #define REG_PIN_TRACEDAT5 ( 0x02a4 )
391 #define REG_PIN_TRACEDAT6 ( 0x02a8 )
392 #define REG_PIN_TRACEDAT7 ( 0x02ac )
393 #define REG_PIN_EXTINT0 ( 0x02b0 )
394 #define REG_PIN_EXTINT1 ( 0x02b4 )
395 #define REG_PIN_SCL3 ( 0x02b8 )
396 #define REG_PIN_SDA3 ( 0x02bc )
397 #define REG_PIN_U1TXD ( 0x02c0 )
398 #define REG_PIN_U1RXD ( 0x02c4 )
399 #define REG_PIN_U2TXD ( 0x02c8 )
400 #define REG_PIN_U2RXD ( 0x02cc )
401 #define REG_PIN_U3TXD ( 0x02d0 )
402 #define REG_PIN_U3RXD ( 0x02d4 )
403 #define REG_PIN_U3CTS ( 0x02d8 )
404 #define REG_PIN_U3RTS ( 0x02dc )
405 #define REG_PIN_U4TXD ( 0x02e0 )
406 #define REG_PIN_U4RXD ( 0x02e4 )
410 /* bits definitions for register REG_PIN_XXX */
411 #define BITS_PIN_DS(_x_) ( ((_x_) << 19) & (BIT_19|BIT_20|BIT_21|BIT_22) )
412 #define BIT_PIN_SLP_AP ( BIT_13 )
413 #define BIT_PIN_SLP_CP0 ( BIT_14 )
414 #define BIT_PIN_SLP_CP1 ( BIT_15 )
415 #define BIT_PIN_SLP_VCP0 ( BIT_16 )
416 #define BIT_PIN_SLP_VCP1 ( BIT_17 )
417 #define BITS_PIN_SLP(_x_) ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16|BIT_17) )
418 #define BIT_PIN_WPU_SEL ( BIT_12 )
419 #define BIT_PIN_WPU ( BIT_7 )
420 #define BIT_PIN_WPD ( BIT_6 )
421 #define BITS_PIN_AF(_x_) ( ((_x_) << 4) & (BIT_4|BIT_5) )
422 #define BIT_PIN_SLP_WPU ( BIT_3 )
423 #define BIT_PIN_SLP_WPD ( BIT_2 )
424 #define BIT_PIN_SLP_IE ( BIT_1 )
425 #define BIT_PIN_SLP_OE ( BIT_0 )
427 /* vars definitions for controller CTL_PIN */
428 #define BIT_PIN_NUL ( 0 )
429 #define BIT_PIN_SLP_NUL ( 0 )
430 #define BIT_PIN_SLP_Z ( 0 )
431 #define BIT_PIN_WPU_SEL ( BIT_12 )
432 #define BIT_PIN_WPUS ( BIT_12 )
433 #define BIT_PIN_NULL ( 0 )
435 /*here is the pinmap info of adie such as 2723*/
436 #define CTL_ANA_PIN_BASE (SPRD_ANA_PIN_PHYS)
438 /* registers definitions for controller CTL_PIN */
439 #define REG_PIN_ANA_EXT_XTL_EN0 ( 0x04 )
440 #define REG_PIN_ANA_PBINT ( 0x08 )
441 #define REG_PIN_ANA_PBINT2 ( 0x0C )
442 #define REG_PIN_ANA_ADI_SCLK ( 0x10 )
443 #define REG_PIN_ANA_ADI_SYNC ( 0x14 )
444 #define REG_PIN_ANA_ADI_D ( 0x18 )
445 #define REG_PIN_ANA_AUD_DASYNC ( 0x1C )
446 #define REG_PIN_ANA_AUD_DAD0 ( 0x20 )
447 #define REG_PIN_ANA_AUD_DAD1 ( 0x24 )
448 #define REG_PIN_ANA_AUD_ADSYNC ( 0x28 )
449 #define REG_PIN_ANA_AUD_ADD0 ( 0x2C )
450 #define REG_PIN_ANA_AUD_SCLK ( 0x30 )
451 #define REG_PIN_ANA_CLK_32K ( 0x34 )
452 #define REG_PIN_ANA_XTL_BUF_EN1 ( 0x38 )
453 #define REG_PIN_ANA_XTL_BUF_EN0 ( 0x3C )
454 #define REG_PIN_ANA_CHIP_SLEEP ( 0x40 )
455 #define REG_PIN_ANA_EXT_RST_B ( 0x44 )
456 #define REG_PIN_ANA_ANA_INT ( 0x48 )
457 #define REG_PIN_ANA_PTEST ( 0x4C )
459 /* bits definitions for register REG_PIN_XXX */
460 #define BITS_ANA_PIN_DS(_x_) ( ((_x_) << 8) & (BIT_8|BIT_9) )
461 #define BIT_ANA_PIN_WPU ( BIT_7 )
462 #define BIT_ANA_PIN_WPD ( BIT_6 )
463 #define BITS_ANA_PIN_AF(_x_) ( ((_x_) << 4) & (BIT_4|BIT_5) )
464 #define BIT_ANA_PIN_SLP_WPU ( BIT_3 )
465 #define BIT_ANA_PIN_SLP_WPD ( BIT_2 )
466 #define BIT_ANA_PIN_SLP_IE ( BIT_1 )
467 #define BIT_ANA_PIN_SLP_OE ( BIT_0 )
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