arch/arm/include/asm/arch-sc9630/cp_boot.h

   1 /******************************************************************************
   2  ** File Name:      cp_mode.c                                                 *
   3  ** Author:         Andrew.Yang                                               *
   4  ** DATE:           31/03/2014                                                *
   5  ** Copyright:      2014 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file defines the logic interfaces called during boot,*
   7  **                 including reset mode setting, initialization etc.
   8  ******************************************************************************
   9
  10  ******************************************************************************
  11  **                        Edit History                                       *
  12  ** ------------------------------------------------------------------------- *
  13  ** DATE           NAME             DESCRIPTION                               *
  14  ** 31/03/2014     Andrew           Create.                                   *
  15  ******************************************************************************/
  16
  17 /**---------------------------------------------------------------------------*
  18  **                         Dependencies                                      *
  19  **---------------------------------------------------------------------------*/
  20 /**---------------------------------------------------------------------------*
  21  **                         Compiler Flag                                     *
  22  **---------------------------------------------------------------------------*/
  23 #ifndef _CP_BOOT_H_
  24 #define  _CP_BOOT_H__
  25
  26
  27 /**---------------------------------------------------------------------------*
  28  **                         Global variables                                  *
  29  **---------------------------------------------------------------------------*/
  30
  31 #define msleep(cnt) udelay(cnt*1000)
  32 /**---------------------------------------------------------------------------*
  33  **                         Local variables                                   *
  34  **---------------------------------------------------------------------------*/
  35
  36 /**---------------------------------------------------------------------------*
  37  **                     Local Function Prototypes                             *
  38  **---------------------------------------------------------------------------*/
  39
  40 /**---------------------------------------------------------------------------*
  41  **                         Function Prototypes                               *
  42  **---------------------------------------------------------------------------*/
  43 /*****************************************************************************/
  44 //  Description:    Sets the different kinds of reset modes, used in normal p-
  45 //                  ower up mode, watchdog reset mode and calibration mode etc.
  46 //  Author:         Andrew.Yang
  47 //  Note:
  48 /*****************************************************************************/
  49 static inline void cp0_arm0_boot(void)
  50 {
  51     u32 state;
  52
  53       /* open cp0 pmu controller
  54     *((volatile u32*)REG_PMU_APB_PD_CP0_SYS_CFG ) &= ~BIT_25;
  55     msleep(50);
  56     *((volatile u32*)REG_PMU_APB_PD_CP0_SYS_CFG ) &= ~BIT_28;
  57     */
  58
  59     *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~BIT_17;   /*clear cp0 sleep */
  60     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_0;   /* reset cp0 */
  61     msleep(50);
  62     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_0; /* clear cp0 force shutdown */
  63
  64     while(1)
  65     {
  66     state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
  67     if(!(state & BIT_0))
  68       break;
  69     }
  70 }
  71
  72 /*****************************************************************************/
  73 //  Description:    Gets the current reset mode.
  74 //  Author:         Andrew.Yang
  75 //  Note:
  76 /*****************************************************************************/
  77 static inline void cp1_boot(void)
  78 {
  79     u32 state;
  80     *((volatile u32*)REG_AON_APB_APB_RST1) |= BIT_20;   /* reset cp1 */
  81     msleep(50);
  82     *((volatile u32*)REG_AON_APB_APB_RST1) &= ~BIT_20;   /*clear reset cp1 */
  83 #ifdef CONFIG_ARCH_SCX20L
  84     *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~(BIT_17 |BIT_18 | BIT_20);/*clear cp0/cp1 sleep*/
  85 #else
  86     *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~(BIT_18 | BIT_20);   /*clear cp1 sleep */
  87 #endif
  88
  89     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_1;   /* reset cp0 */
  90     msleep(50);
  91     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_1; /* clear cp0 force shutdown */
  92
  93     while(1)
  94     {
  95     state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
  96     if(!(state & BIT_1))
  97       break;
  98     }
  99 }
 100 /*****************************************************************************/
 101 //  Description:    Gets the current reset mode.
 102 //  Author:         Andrew.Yang
 103 //  Note:
 104 /*****************************************************************************/
 105 static inline void pmic_arm7_RAM_active(void)
 106 {
 107     u32 state;
 108     *((volatile u32*)REG_AON_APB_ARM7_SYS_SOFT_RST) |= BIT_0;   /* 0x402e0114*/
 109     msleep(50);
 110     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_8;   /* reset arm7*/
 111     msleep(50);
 112     *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_8; /* clear arm7*/
 113     while(1)
 114     {
 115         state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
 116         if(!(state & BIT_8))
 117           break;
 118     }
 119 }
 120
 121
 122 /*****************************************************************************/
 123 //  Description:    Gets the current reset mode.
 124 //  Author:         Andrew.Yang
 125 //  Note:
 126 /*****************************************************************************/
 127 static inline void pmic_arm7_boot(void)
 128 {
 129     u32 state;
 130     *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~BIT_21;   /*clear arm7 force sleep */
 131     *((volatile u32*)REG_AON_APB_ARM7_SYS_SOFT_RST) &= ~BIT_0;   /* reset arm7 */
 132     msleep(50);
 133 }
 134
 135
 136 /*****************************************************************************/
 137 //  Description:    After normal power on, the HW_RST flag should be reset in
 138 //                  order to judge differrent reset conditions between normal
 139 //                  power on reset and watchdog reset.
 140 //  Author:         Andrew.Yang
 141 //  Note:
 142 /*****************************************************************************/
 143 static inline void cp2_boot()
 144 {
 145 }
 146
 147 /*****************************************************************************/
 148 //  Description:    Before watchdog reset, writting HW_RST flag is uesed to j-
 149 //                  udge differrent watchdog reset conditions between MCU reset
 150 //                  and system-halted.
 151 //  Author:         Andrew.Yang
 152 //  Note:
 153 /*****************************************************************************/
 154 static inline void cp0_arm1_boot(void)
 155 {
 156 }
 157
 158 static inline void cp0_arm2_boot(void)
 159 {
 160 }
 161
 162
 163 /**---------------------------------------------------------------------------*
 164  **                         Compiler Flag                                     *
 165  **---------------------------------------------------------------------------*/
 166 #endif