2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
\r
4 * This file is dual-licensed: you can use it either under the terms
\r
5 * of the GPL or the X11 license, at your option. Note that this dual
\r
6 * licensing only applies to this file, and not this project as a
\r
12 #ifndef __H_REGS_PMU_APB_RF_HEADFILE_H__
\r
13 #define __H_REGS_PMU_APB_RF_HEADFILE_H__ __FILE__
\r
15 #define REGS_PMU_APB_RF
\r
17 /* registers definitions for PMU_APB_RF */
\r
18 #define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)
\r
19 #define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)
\r
20 #define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)
\r
21 #define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)
\r
22 #define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)
\r
23 #define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)
\r
24 #define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)
\r
25 #define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)
\r
26 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)
\r
27 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)
\r
28 #define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)
\r
29 #define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)
\r
30 #define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)
\r
31 #define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)
\r
32 #define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)
\r
33 #define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)
\r
34 #define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)
\r
35 #define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)
\r
36 #define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)
\r
37 #define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)
\r
38 #define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)
\r
39 #define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)
\r
40 #define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)
\r
41 #define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)
\r
42 #define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)
\r
43 #define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)
\r
44 #define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)
\r
45 #define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)
\r
46 #define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)
\r
47 #define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)
\r
48 #define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)
\r
49 #define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)
\r
50 #define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)
\r
51 #define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)
\r
52 #define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)
\r
53 #define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)
\r
54 #define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)
\r
55 #define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)
\r
56 #define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)
\r
57 #define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)
\r
58 #define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)
\r
59 #define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)
\r
60 #define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)
\r
61 #define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)
\r
62 #define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)
\r
63 #define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)
\r
64 #define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)
\r
65 #define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)
\r
66 #define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)
\r
67 #define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)
\r
68 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)
\r
69 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)
\r
70 #define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)
\r
71 #define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)
\r
72 #define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)
\r
73 #define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)
\r
74 #define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)
\r
75 #define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)
\r
76 #define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)
\r
77 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)
\r
78 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)
\r
79 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)
\r
80 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)
\r
81 #define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)
\r
82 #define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)
\r
83 #define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)
\r
84 #define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164)
\r
85 #define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168)
\r
86 #define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C)
\r
87 #define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170)
\r
88 #define REG_PMU_APB_CA7_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)
\r
89 #define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178)
\r
90 #define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C)
\r
91 #define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180)
\r
92 #define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184)
\r
93 #define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188)
\r
94 #define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C)
\r
95 #define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190)
\r
96 #define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194)
\r
97 #define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198)
\r
98 #define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C)
\r
99 #define REG_PMU_APB_WAKEUP_LOCK_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0)
\r
100 #if defined(CONFIG_SP9830IEA_5M_H100)
\r
101 #define REG_PMU_APB_PD_CODEC_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0X01A4)
\r
103 #define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)
\r
104 #define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)
\r
105 #define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)
\r
106 #define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)
\r
107 #define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)
\r
108 #define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014)
\r
109 #define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018)
\r
110 #define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C)
\r
111 #define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020)
\r
112 #define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024)
\r
113 #define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028)
\r
114 #define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C)
\r
115 #define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030)
\r
116 #define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034)
\r
117 #define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038)
\r
118 #define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C)
\r
119 #define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040)
\r
120 #define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044)
\r
121 #define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048)
\r
122 #define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C)
\r
123 #define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050)
\r
124 #define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054)
\r
128 /* bits definitions for register REG_PMU_APB_RF_PD_CA7_TOP_CFG */
\r
129 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) )
\r
130 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) )
\r
131 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
132 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
133 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
134 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
136 /* bits definitions for register REG_PMU_APB_RF_PD_CA7_C0_CFG */
\r
137 #define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN ( BIT(29) )
\r
138 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) )
\r
139 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) )
\r
140 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
141 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
142 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
143 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
145 /* bits definitions for register REG_PMU_APB_RF_PD_CA7_C1_CFG */
\r
146 #define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN ( BIT(29) )
\r
147 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) )
\r
148 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) )
\r
149 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
150 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
151 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
152 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
154 /* bits definitions for register REG_PMU_APB_RF_PD_CA7_C2_CFG */
\r
155 #define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN ( BIT(29) )
\r
156 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) )
\r
157 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) )
\r
158 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
159 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
160 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
161 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
163 /* bits definitions for register REG_PMU_APB_RF_PD_CA7_C3_CFG */
\r
164 #define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN ( BIT(29) )
\r
165 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) )
\r
166 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) )
\r
167 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
168 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
169 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
170 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
172 /* bits definitions for register REG_PMU_APB_RF_PD_AP_SYS_CFG */
\r
173 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
174 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
175 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
176 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
177 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
179 /* bits definitions for register REG_PMU_APB_RF_PD_MM_TOP_CFG */
\r
180 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) )
\r
181 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
182 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
183 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
184 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
186 /* bits definitions for register REG_PMU_APB_RF_PD_GPU_TOP_CFG */
\r
187 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) )
\r
188 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
189 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
190 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
191 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
193 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_ARM9_0_CFG */
\r
194 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) )
\r
195 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
196 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
197 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
198 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
200 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_ARM9_1_CFG */
\r
201 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) )
\r
202 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
203 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
204 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
205 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
207 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_HU3GE_CFG */
\r
208 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) )
\r
209 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
210 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
211 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
212 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
214 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_GSM_0_CFG */
\r
215 #define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) )
\r
216 #define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
217 #define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
218 #define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
219 #define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
221 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_GSM_1_CFG */
\r
222 #define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) )
\r
223 #define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
224 #define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
225 #define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
226 #define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
228 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_TD_CFG */
\r
229 #define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) )
\r
230 #define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
231 #define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
232 #define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
233 #define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
235 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_CEVA_0_CFG */
\r
236 #define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) )
\r
237 #define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
238 #define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
239 #define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
240 #define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
242 /* bits definitions for register REG_PMU_APB_RF_PD_CP0_CEVA_1_CFG */
\r
243 #define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) )
\r
244 #define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
245 #define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
246 #define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
247 #define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
249 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
\r
251 /* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */
\r
252 #define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) )
\r
253 #define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
254 #define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
255 #define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
256 #define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
258 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */
\r
259 #define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) )
\r
260 #define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
261 #define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
262 #define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
263 #define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
265 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */
\r
266 #define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) )
\r
267 #define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
268 #define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
269 #define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
270 #define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
272 /* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */
\r
273 #define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) )
\r
274 #define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
275 #define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
276 #define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
277 #define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
279 /* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */
\r
280 #define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) )
\r
281 #define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
282 #define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
283 #define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
284 #define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
286 /* bits definitions for register REG_PMU_APB_RF_PD_PUB_SYS_CFG */
\r
287 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
288 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
289 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
290 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
291 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
293 /* bits definitions for register REG_PMU_APB_RF_AP_WAKEUP_POR_CFG */
\r
294 #define BIT_AP_WAKEUP_POR_N ( BIT(0) )
\r
296 /* bits definitions for register REG_PMU_APB_RF_XTL_WAIT_CNT */
\r
297 #define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
298 #define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
300 /* bits definitions for register REG_PMU_APB_RF_XTLBUF_WAIT_CNT */
\r
301 #define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
302 #define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
304 /* bits definitions for register REG_PMU_APB_RF_PLL_WAIT_CNT1 */
\r
305 #define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
306 #define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
307 #define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
308 #define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
310 /* bits definitions for register REG_PMU_APB_RF_PLL_WAIT_CNT2 */
\r
311 #define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
313 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
\r
314 #define BIT_XTL0_ARM7_SEL ( BIT(5) )
\r
315 #define BIT_XTL0_VCP1_SEL ( BIT(4) )
\r
316 #define BIT_XTL0_VCP0_SEL ( BIT(3) )
\r
317 #define BIT_XTL0_CP1_SEL ( BIT(2) )
\r
318 #define BIT_XTL0_CP0_SEL ( BIT(1) )
\r
319 #define BIT_XTL0_AP_SEL ( BIT(0) )
\r
321 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
\r
322 #define BIT_XTL1_ARM7_SEL ( BIT(5) )
\r
323 #define BIT_XTL1_VCP1_SEL ( BIT(4) )
\r
324 #define BIT_XTL1_VCP0_SEL ( BIT(3) )
\r
325 #define BIT_XTL1_CP1_SEL ( BIT(2) )
\r
326 #define BIT_XTL1_CP0_SEL ( BIT(1) )
\r
327 #define BIT_XTL1_AP_SEL ( BIT(0) )
\r
329 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
\r
330 #define BIT_XTLBUF0_ARM7_SEL ( BIT(5) )
\r
331 #define BIT_XTLBUF0_VCP1_SEL ( BIT(4) )
\r
332 #define BIT_XTLBUF0_VCP0_SEL ( BIT(3) )
\r
333 #define BIT_XTLBUF0_CP1_SEL ( BIT(2) )
\r
334 #define BIT_XTLBUF0_CP0_SEL ( BIT(1) )
\r
335 #define BIT_XTLBUF0_AP_SEL ( BIT(0) )
\r
337 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
\r
338 #define BIT_XTLBUF1_ARM7_SEL ( BIT(5) )
\r
339 #define BIT_XTLBUF1_VCP1_SEL ( BIT(4) )
\r
340 #define BIT_XTLBUF1_VCP0_SEL ( BIT(3) )
\r
341 #define BIT_XTLBUF1_CP1_SEL ( BIT(2) )
\r
342 #define BIT_XTLBUF1_CP0_SEL ( BIT(1) )
\r
343 #define BIT_XTLBUF1_AP_SEL ( BIT(0) )
\r
345 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
\r
346 #define BIT_MPLL_REF_SEL ( BIT(8) )
\r
347 #define BIT_MPLL_ARM7_SEL ( BIT(5) )
\r
348 #define BIT_MPLL_VCP1_SEL ( BIT(4) )
\r
349 #define BIT_MPLL_VCP0_SEL ( BIT(3) )
\r
350 #define BIT_MPLL_CP1_SEL ( BIT(2) )
\r
351 #define BIT_MPLL_CP0_SEL ( BIT(1) )
\r
352 #define BIT_MPLL_AP_SEL ( BIT(0) )
\r
354 /* bits definitions for register REG_PMU_APB_RF_DPLL_REL_CFG */
\r
355 #define BIT_DPLL_REF_SEL ( BIT(8) )
\r
356 #define BIT_DPLL_ARM7_SEL ( BIT(5) )
\r
357 #define BIT_DPLL_VCP1_SEL ( BIT(4) )
\r
358 #define BIT_DPLL_VCP0_SEL ( BIT(3) )
\r
359 #define BIT_DPLL_CP1_SEL ( BIT(2) )
\r
360 #define BIT_DPLL_CP0_SEL ( BIT(1) )
\r
361 #define BIT_DPLL_AP_SEL ( BIT(0) )
\r
363 /* bits definitions for register REG_PMU_APB_RF_LTEPLL_REL_CFG */
\r
364 #define BIT_LTEPLL_REF_SEL ( BIT(8) )
\r
365 #define BIT_LTEPLL_ARM7_SEL ( BIT(5) )
\r
366 #define BIT_LTEPLL_VCP1_SEL ( BIT(4) )
\r
367 #define BIT_LTEPLL_VCP0_SEL ( BIT(3) )
\r
368 #define BIT_LTEPLL_CP1_SEL ( BIT(2) )
\r
369 #define BIT_LTEPLL_CP0_SEL ( BIT(1) )
\r
370 #define BIT_LTEPLL_AP_SEL ( BIT(0) )
\r
372 /* bits definitions for register REG_PMU_APB_RF_TWPLL_REL_CFG */
\r
373 #define BIT_TWPLL_REF_SEL ( BIT(8) )
\r
374 #define BIT_TWPLL_ARM7_SEL ( BIT(5) )
\r
375 #define BIT_TWPLL_VCP1_SEL ( BIT(4) )
\r
376 #define BIT_TWPLL_VCP0_SEL ( BIT(3) )
\r
377 #define BIT_TWPLL_CP1_SEL ( BIT(2) )
\r
378 #define BIT_TWPLL_CP0_SEL ( BIT(1) )
\r
379 #define BIT_TWPLL_AP_SEL ( BIT(0) )
\r
381 /* bits definitions for register REG_PMU_APB_RF_LVDSDIS_PLL_REL_CFG */
\r
382 #define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) )
\r
383 #define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) )
\r
384 #define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) )
\r
385 #define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) )
\r
386 #define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) )
\r
387 #define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) )
\r
388 #define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) )
\r
390 /* bits definitions for register REG_PMU_APB_RF_CP_SOFT_RST */
\r
391 #define BIT_ARM7_SOFT_RST ( BIT(8) )
\r
392 #define BIT_PUB_SOFT_RST ( BIT(6) )
\r
393 #define BIT_AP_SOFT_RST ( BIT(5) )
\r
394 #define BIT_GPU_SOFT_RST ( BIT(4) )
\r
395 #define BIT_MM_SOFT_RST ( BIT(3) )
\r
396 #define BIT_CP1_SOFT_RST ( BIT(1) )
\r
397 #define BIT_CP0_SOFT_RST ( BIT(0) )
\r
399 /* bits definitions for register REG_PMU_APB_RF_CP_SLP_STATUS_DBG0 */
\r
400 #define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
401 #define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
403 /* bits definitions for register REG_PMU_APB_RF_PWR_STATUS0_DBG */
\r
404 #define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
405 #define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
406 #define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
407 #define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
408 #define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
409 #define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
410 #define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
411 #define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
413 /* bits definitions for register REG_PMU_APB_RF_PWR_STATUS1_DBG */
\r
414 #define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
415 #define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
416 #define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
417 #define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
418 #define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
419 #define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
420 #define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
421 #define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
423 /* bits definitions for register REG_PMU_APB_RF_PWR_STATUS2_DBG */
\r
424 #define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
425 #define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
426 #define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
427 #define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
428 #define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
429 #define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
431 /* bits definitions for register REG_PMU_APB_RF_SLEEP_CTRL */
\r
432 #define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) )
\r
433 #define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) )
\r
434 #define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) )
\r
435 #define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) )
\r
436 #define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) )
\r
437 #define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) )
\r
438 #define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) )
\r
439 #define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) )
\r
440 #define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) )
\r
441 #define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) )
\r
442 #define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) )
\r
443 #define BIT_VCP1_LIGHT_SLEEP ( BIT(12) )
\r
444 #define BIT_VCP0_LIGHT_SLEEP ( BIT(11) )
\r
445 #define BIT_CP1_LIGHT_SLEEP ( BIT(10) )
\r
446 #define BIT_CP0_LIGHT_SLEEP ( BIT(9) )
\r
447 #define BIT_AP_LIGHT_SLEEP ( BIT(8) )
\r
448 #define BIT_VCP1_DEEP_SLEEP ( BIT(4) )
\r
449 #define BIT_VCP0_DEEP_SLEEP ( BIT(3) )
\r
450 #define BIT_CP1_DEEP_SLEEP ( BIT(2) )
\r
451 #define BIT_CP0_DEEP_SLEEP ( BIT(1) )
\r
452 #define BIT_AP_DEEP_SLEEP ( BIT(0) )
\r
454 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
\r
455 #define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) )
\r
456 #define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) )
\r
457 #define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) )
\r
458 #define BIT_DDR_PUBL_SOFT_RST ( BIT(10) )
\r
459 #define BIT_DDR_PHY_SOFT_RST ( BIT(8) )
\r
460 #define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) )
\r
461 #define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) )
\r
462 #define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) )
\r
463 #define BIT_DDR_PHY_EB ( BIT(2) )
\r
464 #define BIT_DDR_UMCTL_EB ( BIT(1) )
\r
465 #define BIT_DDR_PUBL_EB ( BIT(0) )
\r
467 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
\r
468 #define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
469 #define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
470 #define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
471 #define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
472 #define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
473 #define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
475 /* bits definitions for register REG_PMU_APB_RF_CA7_TOP_CFG */
\r
476 #define BIT_CA7_L2RSTDISABLE ( BIT(0) )
\r
478 /* bits definitions for register REG_PMU_APB_RF_CA7_C0_CFG */
\r
479 #define BIT_CA7_VINITHI_C0 ( BIT(0) )
\r
481 /* bits definitions for register REG_PMU_APB_RF_CA7_C1_CFG */
\r
482 #define BIT_CA7_VINITHI_C1 ( BIT(0) )
\r
484 /* bits definitions for register REG_PMU_APB_RF_CA7_C2_CFG */
\r
485 #define BIT_CA7_VINITHI_C2 ( BIT(0) )
\r
487 /* bits definitions for register REG_PMU_APB_RF_CA7_C3_CFG */
\r
488 #define BIT_CA7_VINITHI_C3 ( BIT(0) )
\r
490 /* bits definitions for register REG_PMU_APB_RF_DDR_CHN_SLEEP_CTRL0 */
\r
491 #define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) )
\r
492 #define BIT_DDR_CTRL_CGM_SEL ( BIT(30) )
\r
493 #define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) )
\r
494 #define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) )
\r
495 #define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) )
\r
496 #define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) )
\r
497 #define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) )
\r
498 #define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) )
\r
499 #define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) )
\r
500 #define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) )
\r
501 #define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) )
\r
502 #define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) )
\r
503 #define BIT_DDR_CHN9_CGM_SEL ( BIT(9) )
\r
504 #define BIT_DDR_CHN8_CGM_SEL ( BIT(8) )
\r
505 #define BIT_DDR_CHN7_CGM_SEL ( BIT(7) )
\r
506 #define BIT_DDR_CHN6_CGM_SEL ( BIT(6) )
\r
507 #define BIT_DDR_CHN5_CGM_SEL ( BIT(5) )
\r
508 #define BIT_DDR_CHN4_CGM_SEL ( BIT(4) )
\r
509 #define BIT_DDR_CHN3_CGM_SEL ( BIT(3) )
\r
510 #define BIT_DDR_CHN2_CGM_SEL ( BIT(2) )
\r
511 #define BIT_DDR_CHN1_CGM_SEL ( BIT(1) )
\r
512 #define BIT_DDR_CHN0_CGM_SEL ( BIT(0) )
\r
514 /* bits definitions for register REG_PMU_APB_RF_DDR_CHN_SLEEP_CTRL1 */
\r
515 #define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) )
\r
516 #define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) )
\r
517 #define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) )
\r
518 #define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) )
\r
519 #define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) )
\r
520 #define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) )
\r
521 #define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) )
\r
522 #define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) )
\r
523 #define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) )
\r
524 #define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) )
\r
526 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
\r
527 #define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) )
\r
528 #define BIT_DDR_PUBL_RET_EN ( BIT(27) )
\r
529 #define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) )
\r
530 #define BIT_DDR_UMCTL_RET_EN ( BIT(25) )
\r
531 #define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) )
\r
532 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
533 #define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
\r
534 #define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
\r
536 /* bits definitions for register REG_PMU_APB_RF_DDR_PHY_RET_CFG */
\r
537 #define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) )
\r
538 #define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) )
\r
540 /* bits definitions for register REG_PMU_APB_RF_26M_SEL_CFG */
\r
541 #define BIT_AON_RC_4M_SEL ( BIT(8) )
\r
542 #define BIT_GGE_26M_SEL ( BIT(6) )
\r
543 #define BIT_PUB_26M_SEL ( BIT(5) )
\r
544 #define BIT_AON_26M_SEL ( BIT(4) )
\r
545 #define BIT_CP1_26M_SEL ( BIT(2) )
\r
546 #define BIT_CP0_26M_SEL ( BIT(1) )
\r
547 #define BIT_AP_26M_SEL ( BIT(0) )
\r
549 /* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */
\r
550 #define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) )
\r
551 #define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) )
\r
552 #define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) )
\r
553 #define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) )
\r
554 #define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) )
\r
555 #define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) )
\r
556 #define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) )
\r
557 #define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) )
\r
558 #define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) )
\r
559 #define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) )
\r
560 #define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) )
\r
561 #define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) )
\r
562 #define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) )
\r
563 #define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) )
\r
564 #define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) )
\r
565 #define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) )
\r
566 #define BIT_PD_CA7_TOP_BISR_DONE ( BIT(4) )
\r
567 #define BIT_PD_CA7_C3_BISR_DONE ( BIT(3) )
\r
568 #define BIT_PD_CA7_C2_BISR_DONE ( BIT(2) )
\r
569 #define BIT_PD_CA7_C1_BISR_DONE ( BIT(1) )
\r
570 #define BIT_PD_CA7_C0_BISR_DONE ( BIT(0) )
\r
572 /* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */
\r
573 #define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) )
\r
574 #define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) )
\r
575 #define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) )
\r
576 #define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) )
\r
577 #define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) )
\r
578 #define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) )
\r
579 #define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) )
\r
580 #define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) )
\r
581 #define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) )
\r
582 #define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) )
\r
583 #define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) )
\r
584 #define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) )
\r
585 #define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) )
\r
586 #define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) )
\r
587 #define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) )
\r
588 #define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) )
\r
589 #define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(4) )
\r
590 #define BIT_PD_CA7_C3_BISR_BUSY ( BIT(3) )
\r
591 #define BIT_PD_CA7_C2_BISR_BUSY ( BIT(2) )
\r
592 #define BIT_PD_CA7_C1_BISR_BUSY ( BIT(1) )
\r
593 #define BIT_PD_CA7_C0_BISR_BUSY ( BIT(0) )
\r
595 /* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */
\r
596 #define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) )
\r
597 #define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) )
\r
598 #define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) )
\r
599 #define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) )
\r
600 #define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) )
\r
601 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) )
\r
602 #define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) )
\r
603 #define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) )
\r
604 #define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) )
\r
605 #define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) )
\r
606 #define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) )
\r
607 #define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) )
\r
608 #define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) )
\r
609 #define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) )
\r
610 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) )
\r
611 #define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) )
\r
612 #define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(4) )
\r
613 #define BIT_PD_CA7_C3_BISR_FORCE_BYP ( BIT(3) )
\r
614 #define BIT_PD_CA7_C2_BISR_FORCE_BYP ( BIT(2) )
\r
615 #define BIT_PD_CA7_C1_BISR_FORCE_BYP ( BIT(1) )
\r
616 #define BIT_PD_CA7_C0_BISR_FORCE_BYP ( BIT(0) )
\r
618 /* bits definitions for register REG_PMU_APB_BISR_EN_CFG */
\r
619 #define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) )
\r
620 #define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) )
\r
621 #define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) )
\r
622 #define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) )
\r
623 #define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) )
\r
624 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) )
\r
625 #define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) )
\r
626 #define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) )
\r
627 #define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) )
\r
628 #define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) )
\r
629 #define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) )
\r
630 #define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) )
\r
631 #define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) )
\r
632 #define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) )
\r
633 #define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) )
\r
634 #define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) )
\r
635 #define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(4) )
\r
636 #define BIT_PD_CA7_C3_BISR_FORCE_EN ( BIT(3) )
\r
637 #define BIT_PD_CA7_C2_BISR_FORCE_EN ( BIT(2) )
\r
638 #define BIT_PD_CA7_C1_BISR_FORCE_EN ( BIT(1) )
\r
639 #define BIT_PD_CA7_C0_BISR_FORCE_EN ( BIT(0) )
\r
641 /* bits definitions for register REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG0 */
\r
642 #define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_)
\r
644 /* bits definitions for register REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG1 */
\r
645 #define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_)
\r
647 /* bits definitions for register REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG2 */
\r
648 #define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_)
\r
650 /* bits definitions for register REG_PMU_APB_RF_CGM_AUTO_GATE_SEL_CFG3 */
\r
651 #define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_)
\r
653 /* bits definitions for register REG_PMU_APB_RF_CGM_FORCE_EN_CFG0 */
\r
654 #define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_)
\r
656 /* bits definitions for register REG_PMU_APB_RF_CGM_FORCE_EN_CFG1 */
\r
657 #define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_)
\r
659 /* bits definitions for register REG_PMU_APB_RF_CGM_FORCE_EN_CFG2 */
\r
660 #define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_)
\r
662 /* bits definitions for register REG_PMU_APB_RF_CGM_FORCE_EN_CFG3 */
\r
663 #define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_)
\r
665 /* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */
\r
666 #define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) )
\r
667 #define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) )
\r
668 #define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) )
\r
669 #define BIT_CP1_SLEEP_XTL_ON ( BIT(2) )
\r
670 #define BIT_CP0_SLEEP_XTL_ON ( BIT(1) )
\r
671 #define BIT_AP_SLEEP_XTL_ON ( BIT(0) )
\r
673 /* bits definitions for register REG_PMU_APB_RF_MEM_SLP_CFG */
\r
674 #define BITS_MEM_SLP_CFG(_X_) (_X_)
\r
676 /* bits definitions for register REG_PMU_APB_RF_MEM_SD_CFG */
\r
677 #define BITS_MEM_SD_CFG(_X_) (_X_)
\r
679 /* bits definitions for register REG_PMU_APB_RF_CA7_CORE_PU_LOCK */
\r
680 #define BIT_CA7_C3_GIC_WAKEUP_EN ( BIT(11) )
\r
681 #define BIT_CA7_C2_GIC_WAKEUP_EN ( BIT(10) )
\r
682 #define BIT_CA7_C1_GIC_WAKEUP_EN ( BIT(9) )
\r
683 #define BIT_CA7_C0_GIC_WAKEUP_EN ( BIT(8) )
\r
684 #define BIT_CA7_C3_PU_LOCK ( BIT(3) )
\r
685 #define BIT_CA7_C2_PU_LOCK ( BIT(2) )
\r
686 #define BIT_CA7_C1_PU_LOCK ( BIT(1) )
\r
687 #define BIT_CA7_C0_PU_LOCK ( BIT(0) )
\r
689 /* bits definitions for register REG_PMU_APB_RF_ARM7_HOLD_CGM_EN */
\r
690 #define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) )
\r
691 #define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) )
\r
692 #define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) )
\r
693 #define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) )
\r
694 #define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) )
\r
695 #define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) )
\r
696 #define BIT_PD_CA7_TOP_CMG_HOLD_EN ( BIT(4) )
\r
697 #define BIT_PD_CA7_C3_CMG_HOLD_EN ( BIT(3) )
\r
698 #define BIT_PD_CA7_C2_CMG_HOLD_EN ( BIT(2) )
\r
699 #define BIT_PD_CA7_C1_CMG_HOLD_EN ( BIT(1) )
\r
700 #define BIT_PD_CA7_C0_CMG_HOLD_EN ( BIT(0) )
\r
702 /* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */
\r
703 #define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
704 #define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
705 #define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
706 #define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
708 /* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */
\r
709 #define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
710 #define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
712 /* bits definitions for register REG_PMU_APB_RC0_REL_CFG */
\r
713 #define BIT_RC0_ARM7_SEL ( BIT(5) )
\r
714 #define BIT_RC0_VCP1_SEL ( BIT(4) )
\r
715 #define BIT_RC0_VCP0_SEL ( BIT(3) )
\r
716 #define BIT_RC0_CP1_SEL ( BIT(2) )
\r
717 #define BIT_RC0_CP0_SEL ( BIT(1) )
\r
718 #define BIT_RC0_AP_SEL ( BIT(0) )
\r
720 /* bits definitions for register REG_PMU_APB_RC1_REL_CFG */
\r
721 #define BIT_RC1_ARM7_SEL ( BIT(5) )
\r
722 #define BIT_RC1_VCP1_SEL ( BIT(4) )
\r
723 #define BIT_RC1_VCP0_SEL ( BIT(3) )
\r
724 #define BIT_RC1_CP1_SEL ( BIT(2) )
\r
725 #define BIT_RC1_CP0_SEL ( BIT(1) )
\r
726 #define BIT_RC1_AP_SEL ( BIT(0) )
\r
728 /* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */
\r
729 #define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
730 #define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
732 /* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */
\r
733 #define BITS_MEM_AUTO_SLP_EN(_X_) (_X_)
\r
735 /* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */
\r
736 #define BITS_MEM_AUTO_SD_EN(_X_) (_X_)
\r
738 /* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */
\r
739 #define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) )
\r
740 #define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) )
\r
741 #define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) )
\r
742 #define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) )
\r
743 #define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) )
\r
744 #define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) )
\r
745 #define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) )
\r
746 #define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) )
\r
747 #define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) )
\r
748 #define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) )
\r
749 #define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) )
\r
750 #define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) )
\r
752 /* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */
\r
753 #define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) )
\r
754 #define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) )
\r
755 #define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) )
\r
756 #define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) )
\r
757 #define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) )
\r
758 #define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) )
\r
759 #define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) )
\r
760 #define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) )
\r
761 #define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) )
\r
762 #define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) )
\r
764 /* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */
\r
765 #define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) )
\r
766 #define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) )
\r
767 #define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) )
\r
768 #define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) )
\r
769 #define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) )
\r
770 #define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) )
\r
771 #define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) )
\r
772 #define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) )
\r
773 #define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) )
\r
774 #define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) )
\r
775 #define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) )
\r
776 #define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) )
\r
777 #define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) )
\r
778 #define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) )
\r
779 #define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) )
\r
780 #define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) )
\r
781 #define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) )
\r
782 #define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) )
\r
783 #define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) )
\r
784 #define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) )
\r
785 #define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) )
\r
786 #define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) )
\r
787 #define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN ( BIT(4) )
\r
788 #define BIT_PD_CA7_C3_WAKEUP_LOCK_EN ( BIT(3) )
\r
789 #define BIT_PD_CA7_C2_WAKEUP_LOCK_EN ( BIT(2) )
\r
790 #define BIT_PD_CA7_C1_WAKEUP_LOCK_EN ( BIT(1) )
\r
791 #define BIT_PD_CA7_C0_WAKEUP_LOCK_EN ( BIT(0) )
\r
793 #if defined(CONFIG_SP9830IEA_5M_H100)
\r
794 /* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_CFG */
\r
795 #define BIT_PD_CODEC_TOP_FORCE_SHUTDOWN (BIT(25))
\r
796 #define BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN (BIT(24))
\r
797 #define BITS_PD_CODEC_TOP_PWR_ON_DLY(_X_) ((_X_) & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
\r
798 #define BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
\r
799 #define BITS_PD_CODEC_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
\r
802 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS */
\r
803 #define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
805 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS */
\r
806 #define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
808 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS */
\r
809 #define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
811 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS */
\r
812 #define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
814 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS */
\r
815 #define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
817 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */
\r
818 #define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
820 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */
\r
821 #define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
823 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */
\r
824 #define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
826 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */
\r
827 #define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
829 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */
\r
830 #define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
832 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */
\r
833 #define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
835 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */
\r
836 #define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
838 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */
\r
839 #define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
841 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */
\r
842 #define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
844 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */
\r
845 #define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
847 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */
\r
848 #define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
850 /* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */
\r
851 #define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
853 /* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */
\r
854 #define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
856 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */
\r
857 #define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
859 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */
\r
860 #define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
862 /* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */
\r
863 #define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
865 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */
\r
866 #define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
projects / kernel / u-boot-tm1.git / blob