1 /******************************************************************************
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2 ** File Name: umctl2_reg.h *
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4 ** DATE: 01/06/2013 *
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5 ** Copyright: 2010 Spreatrum, Incoporated. All Rights Reserved. *
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6 ** Description: Refer to uMCTL2 databook for detail *
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7 ******************************************************************************
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9 ******************************************************************************
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11 ** ------------------------------------------------------------------------- *
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12 ** DATE NAME DESCRIPTION *
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13 ** 01/06/2013 changde.li Create. *
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14 ******************************************************************************/
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16 #ifndef _UMCTL2_REG_H_
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17 #define _UMCTL2_REG_H_
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18 /*----------------------------------------------------------------------------*
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20 **------------------------------------------------------------------------- */
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21 #include "sci_types.h"
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23 /**---------------------------------------------------------------------------*
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25 **--------------------------------------------------------------------------*/
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31 /**---------------------------------------------------------------------------*
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33 **---------------------------------------------------------------------------*/
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34 /**---------------------------------------------------------------------------*
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36 **---------------------------------------------------------------------------*/
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37 #define UMCTL_REG_BASE (0x30000000)
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38 #define PUBL_REG_BASE (0x30010000)
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40 #define UMCTL2_REG_(x) (UMCTL_REG_BASE+(x))
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43 *uMCTL2 DDRC registers
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45 #define UMCTL_MSTR UMCTL2_REG_(0x0000) /*master*/
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46 #define UMCTL_STAT UMCTL2_REG_(0x0004) /*oeration mode status*/
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47 #define UMCTL_MRCTRL0 UMCTL2_REG_(0x0010)/*mode register read/werite control*/
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48 #define UMCTL_MRCTRL1 UMCTL2_REG_(0x0014)
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49 #define UMCTL_MRSTAT UMCTL2_REG_(0x0018)/*mode register read/weite status*/
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51 #define UMCTL_DERATEEN UMCTL2_REG_(0x0020)/*temperature derate enable*/
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52 #define UMCTL_DERATEINT UMCTL2_REG_(0x0024)/*temperature derate interval*/
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53 #define UMCTL_PWRCTL UMCTL2_REG_(0x0030)/*low power control*/
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54 #define UMCTL_PWRTMG UMCTL2_REG_(0x0034)/*low power timing*/
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55 #define UMCTL_HWLPCTL UMCTL2_REG_(0x0038)/*low power timing*/
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58 #define UMCTL_RFSHCTL0 UMCTL2_REG_(0x0050)/*refresh control0*/
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59 #define UMCTL_RFSHCTL1 UMCTL2_REG_(0x0054)
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60 #define UMCTL_RFSHCTL2 UMCTL2_REG_(0x0058)
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61 #define UMCTL_RFSHCTL3 UMCTL2_REG_(0x0060)
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62 #define UMCTL_RFSHTMG UMCTL2_REG_(0x0064)/*refresh Timing*/
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63 #define UMCTL_ECCCFG0 UMCTL2_REG_(0x0070)/*ecc configuration*/
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64 #define UMCTL_ECCCFG1 UMCTL2_REG_(0x0074)
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65 #define UMCTL_ECCSTAT UMCTL2_REG_(0x0078)/*ecc status*/
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66 #define UMCTL_ECCCLR UMCTL2_REG_(0x007C)/*ecc clear*/
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67 #define UMCTL_ECCERRCNT UMCTL2_REG_(0x0080)/*ecc error counter*/
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69 #define UMCTL_ECCADDR0 UMCTL2_REG_(0x0084)/*ecc corrected error address reg0*/
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70 #define UMCTL_ECCADDR1 UMCTL2_REG_(0x0088)
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71 #define UMCTL_ECCSYN0 UMCTL2_REG_(0x008C)/*ecc corected syndrome reg0*/
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72 #define UMCTL_ECCSYN1 UMCTL2_REG_(0x0090)
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73 #define UMCTL_ECCSYN2 UMCTL2_REG_(0x0094)
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74 #define UMCTL_ECCBITMASK0 UMCTL2_REG_(0x0098)
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75 #define UMCTL_ECCBITMASK1 UMCTL2_REG_(0x009C)
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76 #define UMCTL_ECCBITMASK2 UMCTL2_REG_(0x00A0)
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77 #define UMCTL_ECCUADDR0 UMCTL2_REG_(0x00A4)/*ecc uncorrected error address reg0*/
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78 #define UMCTL_ECCUADDR1 UMCTL2_REG_(0x00A8)
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79 #define UMCTL_ECCUSYN0 UMCTL2_REG_(0x00AC)/*ecc UNcorected syndrome reg0*/
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80 #define UMCTL_ECCUSYN1 UMCTL2_REG_(0x00B0)
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81 #define UMCTL_ECCUSYN2 UMCTL2_REG_(0x00B4)
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82 #define UMCTL_ECCPOISONADDR0 UMCTL2_REG_(0x00B8)/*ecc data poisoning address reg0*/
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83 #define UMCTL_ECCPOISONADDR1 UMCTL2_REG_(0x00BC)
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86 #define UMCTL_PARCTL UMCTL2_REG_(0x00C0)/*parity control register*/
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87 #define UMCTL_PARSTAT UMCTL2_REG_(0x00C4)/*parity status register*/
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89 #define UMCTL_INIT0 UMCTL2_REG_(0x00D0)/*SDRAM initialization register0*/
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90 #define UMCTL_INIT1 UMCTL2_REG_(0x00D4)
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91 #define UMCTL_INIT2 UMCTL2_REG_(0x00D8)
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92 #define UMCTL_INIT3 UMCTL2_REG_(0x00DC)
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93 #define UMCTL_INIT4 UMCTL2_REG_(0x00E0)
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94 #define UMCTL_INIT5 UMCTL2_REG_(0x00E4)
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97 #define UMCTL_DIMMCTL UMCTL2_REG_(0x00F0)/*DIMM control register*/
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98 #define UMCTL_RANKCTL UMCTL2_REG_(0x00F4)
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100 #define UMCTL_DRAMTMG0 UMCTL2_REG_(0x0100)/*SDRAM timing register0*/
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101 #define UMCTL_DRAMTMG1 UMCTL2_REG_(0x0104)
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102 #define UMCTL_DRAMTMG2 UMCTL2_REG_(0x0108)
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103 #define UMCTL_DRAMTMG3 UMCTL2_REG_(0x010C)
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104 #define UMCTL_DRAMTMG4 UMCTL2_REG_(0x0110)
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105 #define UMCTL_DRAMTMG5 UMCTL2_REG_(0x0114)
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106 #define UMCTL_DRAMTMG6 UMCTL2_REG_(0x0118)
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107 #define UMCTL_DRAMTMG7 UMCTL2_REG_(0x011C)
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108 #define UMCTL_DRAMTMG8 UMCTL2_REG_(0x0120)
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110 #define UMCTL_ZQCTL0 UMCTL2_REG_(0x0180)/*ZQ control register0*/
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111 #define UMCTL_ZQCTL1 UMCTL2_REG_(0x0184)
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112 #define UMCTL_ZQCTL2 UMCTL2_REG_(0x0188)
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113 #define UMCTL_ZQSTAT UMCTL2_REG_(0x018C)
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116 #define UMCTL_DFITMG0 UMCTL2_REG_(0x0190)/*DFI timing register0*/
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117 #define UMCTL_DFITMG1 UMCTL2_REG_(0x0194)
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119 #define UMCTL_DFILPCFG0 UMCTL2_REG_(0x0198)/*DFI low power configuration*/
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120 #define UMCTL_DFIUPD0 UMCTL2_REG_(0x01A0)/*DFI update register0*/
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121 #define UMCTL_DFIUPD1 UMCTL2_REG_(0x01A4)
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122 #define UMCTL_DFIUPD2 UMCTL2_REG_(0x01A8)
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123 #define UMCTL_DFIUPD3 UMCTL2_REG_(0x01AC)
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125 #define UMCTL_DFIMISC UMCTL2_REG_(0x01B0)
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127 #define UMCTL_TRAINCTL0 UMCTL2_REG_(0x01D0)/*PHY eval training control reg0*/
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128 #define UMCTL_TRAINCTL1 UMCTL2_REG_(0x01D4)
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129 #define UMCTL_TRAINCTL2 UMCTL2_REG_(0x01D8)
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130 #define UMCTL_TRAINSTAT UMCTL2_REG_(0x01DC)
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132 #define UMCTL_ADDRMAP0 UMCTL2_REG_(0x0200)/*address map register0*/
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133 #define UMCTL_ADDRMAP1 UMCTL2_REG_(0x0204)
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134 #define UMCTL_ADDRMAP2 UMCTL2_REG_(0x0208)
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135 #define UMCTL_ADDRMAP3 UMCTL2_REG_(0x020C)
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136 #define UMCTL_ADDRMAP4 UMCTL2_REG_(0x0210)
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137 #define UMCTL_ADDRMAP5 UMCTL2_REG_(0x0214)
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138 #define UMCTL_ADDRMAP6 UMCTL2_REG_(0x0218)
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140 #define UMCTL_ODTCFG UMCTL2_REG_(0x0240)/*ODT configuration register*/
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141 #define UMCTL_ODTMAP UMCTL2_REG_(0x0244)
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143 #define UMCTL_SCHED UMCTL2_REG_(0x0250)/*scheduler control register*/
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144 #define UMCTL_PERFHPR0 UMCTL2_REG_(0x0258)/*high priority read CAM reg0*/
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145 #define UMCTL_PERFHPR1 UMCTL2_REG_(0x025C)
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146 #define UMCTL_PERFLPR0 UMCTL2_REG_(0x0260)
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147 #define UMCTL_PERFLPR1 UMCTL2_REG_(0x0264)
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149 #define UMCTL_PERFWR0 UMCTL2_REG_(0x0268)/*write CAM reg0*/
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150 #define UMCTL_PERFWR1 UMCTL2_REG_(0x026C)
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151 #define UMCTL_DBG0 UMCTL2_REG_(0x0300)/*debug register0*/
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152 #define UMCTL_DBG1 UMCTL2_REG_(0x0304)
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153 #define UMCTL_DBGCAM UMCTL2_REG_(0x0308)/*cam debug register*/
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157 *uMCTL2 Multi-Port registers
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159 #define UMCTL_PCCFG UMCTL2_REG_(0x0400)/*port common configuration*/
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161 #define UMCTL_PCFGR_0 UMCTL2_REG_(0x0404+(0x00)*0xB0)/*Port n configuration read reg*/
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162 #define UMCTL_PCFGR_1 UMCTL2_REG_(0x0404+(0x01)*0xB0)
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163 #define UMCTL_PCFGR_2 UMCTL2_REG_(0x0404+(0x02)*0xB0)
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164 #define UMCTL_PCFGR_3 UMCTL2_REG_(0x0404+(0x03)*0xB0)
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165 #define UMCTL_PCFGR_4 UMCTL2_REG_(0x0404+(0x04)*0xB0)
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166 #define UMCTL_PCFGR_5 UMCTL2_REG_(0x0404+(0x05)*0xB0)
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167 #define UMCTL_PCFGR_6 UMCTL2_REG_(0x0404+(0x06)*0xB0)
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168 #define UMCTL_PCFGR_7 UMCTL2_REG_(0x0404+(0x07)*0xB0)
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169 #define UMCTL_PCFGR_8 UMCTL2_REG_(0x0404+(0x08)*0xB0)
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170 #define UMCTL_PCFGR_9 UMCTL2_REG_(0x0404+(0x09)*0xB0)
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171 #define UMCTL_PCFGR_10 UMCTL2_REG_(0x0404+(0x0A)*0xB0)
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172 #define UMCTL_PCFGR_11 UMCTL2_REG_(0x0404+(0x0B)*0xB0)
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173 #define UMCTL_PCFGR_12 UMCTL2_REG_(0x0404+(0x0C)*0xB0)
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174 #define UMCTL_PCFGR_13 UMCTL2_REG_(0x0404+(0x0D)*0xB0)
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175 #define UMCTL_PCFGR_14 UMCTL2_REG_(0x0404+(0x0E)*0xB0)
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176 #define UMCTL_PCFGR_15 UMCTL2_REG_(0x0404+(0x0F)*0xB0)
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179 #define UMCTL_PCFGW(_x_) UMCTL2_REG_(0x0408+(_x_)*0xB0)
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182 #define UMCTL_PCFGW_0 UMCTL2_REG_(0x0408+(0x00)*0xB0)/*Port n configuration write reg*/
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183 #define UMCTL_PCFGW_1 UMCTL2_REG_(0x0408+(0x01)*0xB0)
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184 #define UMCTL_PCFGW_2 UMCTL2_REG_(0x0408+(0x02)*0xB0)
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185 #define UMCTL_PCFGW_3 UMCTL2_REG_(0x0408+(0x03)*0xB0)
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186 #define UMCTL_PCFGW_4 UMCTL2_REG_(0x0408+(0x04)*0xB0)
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187 #define UMCTL_PCFGW_5 UMCTL2_REG_(0x0408+(0x05)*0xB0)
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188 #define UMCTL_PCFGW_6 UMCTL2_REG_(0x0408+(0x06)*0xB0)
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189 #define UMCTL_PCFGW_7 UMCTL2_REG_(0x0408+(0x07)*0xB0)
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190 #define UMCTL_PCFGW_8 UMCTL2_REG_(0x0408+(0x08)*0xB0)
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191 #define UMCTL_PCFGW_9 UMCTL2_REG_(0x0408+(0x09)*0xB0)
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192 #define UMCTL_PCFGW_10 UMCTL2_REG_(0x0408+(0x0A)*0xB0)
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193 #define UMCTL_PCFGW_11 UMCTL2_REG_(0x0408+(0x0B)*0xB0)
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194 #define UMCTL_PCFGW_12 UMCTL2_REG_(0x0408+(0x0C)*0xB0)
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195 #define UMCTL_PCFGW_13 UMCTL2_REG_(0x0408+(0x0D)*0xB0)
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196 #define UMCTL_PCFGW_14 UMCTL2_REG_(0x0408+(0x0E)*0xB0)
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197 #define UMCTL_PCFGW_15 UMCTL2_REG_(0x0408+(0x0F)*0xB0)
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199 #define UMCTL_PORT_EN(_x_) UMCTL2_REG_(0x0490+(_x_)*0xB0)
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201 #define UMCTL_PORT_EN_0 UMCTL2_REG_(0x0490+(0x00)*0xB0)/*Port n enable reg*/
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202 #define UMCTL_PORT_EN_1 UMCTL2_REG_(0x0490+(0x01)*0xB0)/*Port n enable reg*/
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203 #define UMCTL_PORT_EN_2 UMCTL2_REG_(0x0490+(0x02)*0xB0)/*Port n enable reg*/
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204 #define UMCTL_PORT_EN_3 UMCTL2_REG_(0x0490+(0x03)*0xB0)/*Port n enable reg*/
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205 #define UMCTL_PORT_EN_4 UMCTL2_REG_(0x0490+(0x04)*0xB0)/*Port n enable reg*/
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206 #define UMCTL_PORT_EN_5 UMCTL2_REG_(0x0490+(0x05)*0xB0)/*Port n enable reg*/
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207 #define UMCTL_PORT_EN_6 UMCTL2_REG_(0x0490+(0x06)*0xB0)/*Port n enable reg*/
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208 #define UMCTL_PORT_EN_7 UMCTL2_REG_(0x0490+(0x07)*0xB0)/*Port n enable reg*/
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209 #define UMCTL_PORT_EN_8 UMCTL2_REG_(0x0490+(0x08)*0xB0)/*Port n enable reg*/
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210 #define UMCTL_PORT_EN_9 UMCTL2_REG_(0x0490+(0x09)*0xB0)/*Port n enable reg*/
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214 #define UMCTL2_PCFGIDMASKCH_m_N
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215 #define UMCTL2_PCFGIDVALUECH_m_N
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220 *Refer to PUBL databook 1.44a for detail,Chapter3.3 Registers.
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222 #define PUBL_RIDR (PUBL_REG_BASE+0x00*4) // R - Revision Identification Register
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223 #define PUBL_PIR (PUBL_REG_BASE+0x01*4) // R/W - PHY Initialization Register
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224 #define PUBL_PGCR (PUBL_REG_BASE+0x02*4) // R/W - PHY General Configuration Register
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225 #define PUBL_PGSR (PUBL_REG_BASE+0x03*4) // R - PHY General Status Register
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226 #define PUBL_DLLGCR (PUBL_REG_BASE+0x04*4) // R/W - DLL General Control Register
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227 #define PUBL_ACDLLCR (PUBL_REG_BASE+0x05*4) // R/W - AC DLL Control Register
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228 #define PUBL_PTR0 (PUBL_REG_BASE+0x06*4) // R/W - PHY Timing Register 0
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229 #define PUBL_PTR1 (PUBL_REG_BASE+0x07*4) // R/W - PHY Timing Register 1
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230 #define PUBL_PTR2 (PUBL_REG_BASE+0x08*4) // R/W - PHY Timing Register 2
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231 #define PUBL_ACIOCR (PUBL_REG_BASE+0x09*4) // R/W - AC I/O Configuration Register
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232 #define PUBL_DXCCR (PUBL_REG_BASE+0x0A*4) // R/W - DATX8 I/O Configuration Register
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233 #define PUBL_DSGCR (PUBL_REG_BASE+0x0B*4) // R/W - DFI Configuration Register
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234 #define PUBL_DCR (PUBL_REG_BASE+0x0C*4) // R/W - DRAM Configuration Register
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235 #define PUBL_DTPR0 (PUBL_REG_BASE+0x0D*4) // R/W - SDRAM Timing Parameters Register 0
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236 #define PUBL_DTPR1 (PUBL_REG_BASE+0x0E*4) // R/W - SDRAM Timing Parameters Register 1
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237 #define PUBL_DTPR2 (PUBL_REG_BASE+0x0F*4) // R/W - SDRAM Timing Parameters Register 2
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238 #define PUBL_MR0 (PUBL_REG_BASE+0x10*4) // R/W - Mode Register
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239 #define PUBL_MR1 (PUBL_REG_BASE+0x11*4) // R/W - Ext}ed Mode Register
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240 #define PUBL_MR2 (PUBL_REG_BASE+0x12*4) // R/W - Ext}ed Mode Register 2
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241 #define PUBL_MR3 (PUBL_REG_BASE+0x13*4) // R/W - Ext}ed Mode Register 3
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242 #define PUBL_ODTCR (PUBL_REG_BASE+0x14*4) // R/W - ODT Configuration Register
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243 #define PUBL_DTAR (PUBL_REG_BASE+0x15*4) // R/W - Data Training Address Register
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244 #define PUBL_DTDR0 (PUBL_REG_BASE+0x16*4) // R/W - Data Training Data Register 0
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245 #define PUBL_DTDR1 (PUBL_REG_BASE+0x17*4) // R/W - Data Training Data Register 1
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246 #define PUBL_DCUAR (PUBL_REG_BASE+0X30*4) // R/W - DCU Address Resiter
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247 #define PUBL_DCUDR (PUBL_REG_BASE+0x31*4) // R/W - DCU Data Register
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248 #define PUBL_DCURR (PUBL_REG_BASE+0x32*4) // R/W - DCU Run Register
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249 #define PUBL_DCULR (PUBL_REG_BASE+0x33*4) // R/W - DCU Loop Register
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250 #define PUBL_DCUGCR (PUBL_REG_BASE+0x34*4) // R/W - DCU General Configuration Register
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251 #define PUBL_DCUTPR (PUBL_REG_BASE+0x35*4) // R/W - DCU Timing Parameters Registers
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252 #define PUBL_DCUSR0 (PUBL_REG_BASE+0x36*4) // R - DCU Status Register 0
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253 #define PUBL_DCUSR1 (PUBL_REG_BASE+0x37*4) // R - DCU Status Register 1
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254 #define PUBL_BISTRR (PUBL_REG_BASE+0x40*4) // R/W - BIST Run Register
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255 #define PUBL_BISTMSKR0 (PUBL_REG_BASE+0x41*4) // R/W - BIST Mask Register 0
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256 #define PUBL_BISTMSKR1 (PUBL_REG_BASE+0x42*4) // R/W - BIST Mask Register 1
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257 #define PUBL_BISTWCR (PUBL_REG_BASE+0x43*4) // R/W - BIST Word Count Register
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258 #define PUBL_BISTLSR (PUBL_REG_BASE+0x44*4) // R/W - BIST LFSR Seed Register
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259 #define PUBL_BISTAR0 (PUBL_REG_BASE+0x45*4) // R/W - BIST Address Register 0
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260 #define PUBL_BISTAR1 (PUBL_REG_BASE+0x46*4) // R/W - BIST Address Register 1
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261 #define PUBL_BISTAR2 (PUBL_REG_BASE+0x47*4) // R/W - BIST Address Register 2
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262 #define PUBL_BISTUDPR (PUBL_REG_BASE+0x48*4) // R/W - BIST User Data Pattern Register
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263 #define PUBL_BISTGSR (PUBL_REG_BASE+0x49*4) // R - BIST General Status Register
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264 #define PUBL_BISTWER (PUBL_REG_BASE+0x4A*4) // R - BIST Word Error Register
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265 #define PUBL_BISTBER0 (PUBL_REG_BASE+0x4B*4) // R - BIST Bit Error Register 0
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266 #define PUBL_BISTBER1 (PUBL_REG_BASE+0x4C*4) // R - BIST Bit Error Register 1
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267 #define PUBL_BISTBER2 (PUBL_REG_BASE+0x4D*4) // R - BIST Bit Error Register 2
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268 #define PUBL_BISTWCSR (PUBL_REG_BASE+0x4E*4) // R - BIST Word Count Status Register
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269 #define PUBL_BISTFWR0 (PUBL_REG_BASE+0x4F*4) // R - BIST Fail Word Register 0
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270 #define PUBL_BISTFWR1 (PUBL_REG_BASE+0x50*4) // R - BIST Fail Word Register 1
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271 #define PUBL_ZQ0CR0 (PUBL_REG_BASE+0x60*4) // R/W - ZQ 0 Impedance Control Register 0
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272 #define PUBL_ZQ0CR1 (PUBL_REG_BASE+0x61*4) // R/W - ZQ 0 Impedance Control Register 1
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273 #define PUBL_ZQ0SR0 (PUBL_REG_BASE+0x62*4) // R - ZQ 0 Impedance Status Register 0
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274 #define PUBL_ZQ0SR1 (PUBL_REG_BASE+0x63*4) // R - ZQ 0 Impedance Status Register 1
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275 #define PUBL_ZQ1CR0 (PUBL_REG_BASE+0x64*4) // R/W - ZQ 1 Impedance Control Register 0
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276 #define PUBL_ZQ1CR1 (PUBL_REG_BASE+0x65*4) // R/W - ZQ 1 Impedance Control Register 1
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277 #define PUBL_ZQ1SR0 (PUBL_REG_BASE+0x66*4) // R - ZQ 1 Impedance Status Register 0
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278 #define PUBL_ZQ1SR1 (PUBL_REG_BASE+0x67*4) // R - ZQ 1 Impedance Status Register 1
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279 #define PUBL_ZQ2CR0 (PUBL_REG_BASE+0x68*4) // R/W - ZQ 2 Impedance Control Register 0
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280 #define PUBL_ZQ2CR1 (PUBL_REG_BASE+0x69*4) // R/W - ZQ 2 Impedance Control Register 1
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281 #define PUBL_ZQ2SR0 (PUBL_REG_BASE+0x6A*4) // R - ZQ 2 Impedance Status Register 0
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282 #define PUBL_ZQ2SR1 (PUBL_REG_BASE+0x6B*4) // R - ZQ 2 Impedance Status Register 1
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283 #define PUBL_ZQ3CR0 (PUBL_REG_BASE+0x6C*4) // R/W - ZQ 3 Impedance Control Register 0
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284 #define PUBL_ZQ3CR1 (PUBL_REG_BASE+0x6D*4) // R/W - ZQ 3 Impedance Control Register 1
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285 #define PUBL_ZQ3SR0 (PUBL_REG_BASE+0x6E*4) // R - ZQ 3 Impedance Status Register 0
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286 #define PUBL_ZQ3SR1 (PUBL_REG_BASE+0x6F*4) // R - ZQ 3 Impedance Status Register 1
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287 #define PUBL_DX0GCR (PUBL_REG_BASE+0x70*4) // R/W - DATX8 0 General Configuration Register
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288 #define PUBL_DX0GSR0 (PUBL_REG_BASE+0x71*4) // R - DATX8 0 General Status Register
\r
289 #define PUBL_DX0GSR1 (PUBL_REG_BASE+0x72*4) // R - DATX8 0 General Status Register 1
\r
290 #define PUBL_DX0DLLCR (PUBL_REG_BASE+0x73*4) // R - DATX8 0 DLL Control Register
\r
291 #define PUBL_DX0DQTR (PUBL_REG_BASE+0x74*4) // R/W - DATX8 0 DQ Timing Register
\r
292 #define PUBL_DX0DQSTR (PUBL_REG_BASE+0x75*4) // R/W - DATX8 0 DQS Timing Register
\r
293 #define PUBL_DX1GCR (PUBL_REG_BASE+0x80*4) // R - DATX8 1 General Configration Register
\r
294 #define PUBL_DX1GSR0 (PUBL_REG_BASE+0x81*4) // R - DATX8 1 General Status Register
\r
295 #define PUBL_DX1GSR1 (PUBL_REG_BASE+0x82*4) // R - DATX8 1 General Status Register
\r
296 #define PUBL_DX1DLLCR (PUBL_REG_BASE+0x83*4) // R - DATX8 1 DLL Control Register
\r
297 #define PUBL_DX1DQTR (PUBL_REG_BASE+0x84*4) // R/W - DATX8 1 DQ Timing Register
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298 #define PUBL_DX1DQSTR (PUBL_REG_BASE+0x85*4) // R/W - DATX8 1 DQS Timing Register
\r
299 #define PUBL_DX2GCR (PUBL_REG_BASE+0x90*4) // R - DATX8 2 General Configration Register
\r
300 #define PUBL_DX2GSR0 (PUBL_REG_BASE+0x91*4) // R - DATX8 2 General Status Register
\r
301 #define PUBL_DX2GSR1 (PUBL_REG_BASE+0x92*4) // R - DATX8 2 General Status Register
\r
302 #define PUBL_DX2DLLCR (PUBL_REG_BASE+0x93*4) // R - DATX8 2 DLL Control Register
\r
303 #define PUBL_DX2DQTR (PUBL_REG_BASE+0x94*4) // R/W - DATX8 2 DQ Timing Register
\r
304 #define PUBL_DX2DQSTR (PUBL_REG_BASE+0x95*4) // R/W - DATX8 2 DQS Timing Register
\r
305 #define PUBL_DX3GCR (PUBL_REG_BASE+0xA0*4) // R - DATX8 3 General Configration Register
\r
306 #define PUBL_DX3GSR0 (PUBL_REG_BASE+0xA1*4) // R - DATX8 3 General Status Register
\r
307 #define PUBL_DX3GSR1 (PUBL_REG_BASE+0xA2*4) // R - DATX8 3 General Status Register
\r
308 #define PUBL_DX3DLLCR (PUBL_REG_BASE+0xA3*4) // R - DATX8 3 DLL Control Register
\r
309 #define PUBL_DX3DQTR (PUBL_REG_BASE+0xA4*4) // R/W - DATX8 3 DQ Timing Register
\r
310 #define PUBL_DX3DQSTR (PUBL_REG_BASE+0xA5*4) // R/W - DATX8 3 DQS Timing Register
\r
311 #define PUBL_DX4GCR (PUBL_REG_BASE+0xB0*4) // R - DATX8 4 General Configration Register
\r
312 #define PUBL_DX4GSR0 (PUBL_REG_BASE+0xB1*4) // R - DATX8 4 General Status Register
\r
313 #define PUBL_DX4GSR1 (PUBL_REG_BASE+0xB2*4) // R - DATX8 4 General Status Register
\r
314 #define PUBL_DX4DLLCR (PUBL_REG_BASE+0xB3*4) // R - DATX8 4 DLL Control Register
\r
315 #define PUBL_DX4DQTR (PUBL_REG_BASE+0xB4*4) // R/W - DATX8 4 DQ Timing Register
\r
316 #define PUBL_DX4DQSTR (PUBL_REG_BASE+0xB5*4) // R/W - DATX8 4 DQS Timing Register
\r
317 #define PUBL_DX5GCR (PUBL_REG_BASE+0xC0*4) // R - DATX8 5 General Configration Register
\r
318 #define PUBL_DX5GSR0 (PUBL_REG_BASE+0xC1*4) // R - DATX8 5 General Status Register
\r
319 #define PUBL_DX5GSR1 (PUBL_REG_BASE+0xC2*4) // R - DATX8 5 General Status Register
\r
320 #define PUBL_DX5DLLCR (PUBL_REG_BASE+0xC3*4) // R - DATX8 5 DLL Control Register
\r
321 #define PUBL_DX5DQTR (PUBL_REG_BASE+0xC4*4) // R/W - DATX8 5 DQ Timing Register
\r
322 #define PUBL_DX5DQSTR (PUBL_REG_BASE+0xC5*4) // R/W - DATX8 5 DQS Timing Register
\r
323 #define PUBL_DX6GCR (PUBL_REG_BASE+0xD0*4) // R - DATX8 6 General Configration Register
\r
324 #define PUBL_DX6GSR0 (PUBL_REG_BASE+0xD1*4) // R - DATX8 6 General Status Register
\r
325 #define PUBL_DX6GSR1 (PUBL_REG_BASE+0xD2*4) // R - DATX8 6 General Status Register
\r
326 #define PUBL_DX6DLLCR (PUBL_REG_BASE+0xD3*4) // R - DATX8 6 DLL Control Register
\r
327 #define PUBL_DX6DQTR (PUBL_REG_BASE+0xD4*4) // R/W - DATX8 6 DQ Timing Register
\r
328 #define PUBL_DX6DQSTR (PUBL_REG_BASE+0xD5*4) // R/W - DATX8 6 DQS Timing Register
\r
329 #define PUBL_DX7GCR (PUBL_REG_BASE+0xE0*4) // R - DATX8 7 General Configration Register
\r
330 #define PUBL_DX7GSR0 (PUBL_REG_BASE+0xE1*4) // R - DATX8 7 General Status Register
\r
331 #define PUBL_DX7GSR1 (PUBL_REG_BASE+0xE2*4) // R - DATX8 7 General Status Register
\r
332 #define PUBL_DX7DLLCR (PUBL_REG_BASE+0xE3*4) // R - DATX8 7 DLL Control Register
\r
333 #define PUBL_DX7DQTR (PUBL_REG_BASE+0xE4*4) // R/W - DATX8 7 DQ Timing Register
\r
334 #define PUBL_DX7DQSTR (PUBL_REG_BASE+0xE5*4) // R/W - DATX8 7 DQS Timing Register
\r
335 #define PUBL_DX8GCR (PUBL_REG_BASE+0xF0*4) // R - DATX8 8 General Configration Register
\r
336 #define PUBL_DX8GSR0 (PUBL_REG_BASE+0xF1*4) // R - DATX8 8 General Status Register
\r
337 #define PUBL_DX8GSR1 (PUBL_REG_BASE+0xF2*4) // R - DATX8 8 General Status Register
\r
338 #define PUBL_DX8DLLCR (PUBL_REG_BASE+0xF3*4) // R - DATX8 8 DLL Control Register
\r
339 #define PUBL_DX8DQTR (PUBL_REG_BASE+0xF4*4) // R/W - DATX8 8 DQ Timing Register
\r
340 #define PUBL_DX8DQSTR (PUBL_REG_BASE+0xF5*4) // R/W - DATX8 8 DQS Timing Register
\r
343 /******************************************************************************
\r
345 ******************************************************************************/
\r
348 /**----------------------------------------------------------------------------*
\r
349 ** Compiler Flag **
\r
350 **----------------------------------------------------------------------------*/
\r
354 /**---------------------------------------------------------------------------*/
\r
projects / kernel / u-boot-tm1.git / blob