arch/arm/include/asm/arch-sc8830/pinmap.h

   1 /******************************************************************************
   2  ** File Name:      pinmap.h                                                  *
   3  ** Author:         Richard.Yang                                              *
   4  ** DATE:           03/08/2004                                                *
   5  ** Copyright:      2004 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file defines the structure of pin map.               *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 03/08/2004     Richard.Yang     Create.                                   *
  14  ******************************************************************************/
  15
  16 #ifndef _PINMAP_H_
  17 #define _PINMAP_H_
  18
  19 #include "sci_types.h"
  20 #include "sprd_reg.h"
  21
  22 typedef struct {
  23         uint32_t reg;
  24         uint32_t val;
  25 } pinmap_t;
  26 int pin_init(void);
  27 //int pin_init(pinmap_t * pinmap);
  28
  29 #define CTL_PIN_BASE                    (SPRD_PIN_PHYS)
  30 #ifdef CONFIG_SPX15
  31 /* registers definitions for controller CTL_PIN */
  32 #define REG_PIN_CTRL0                   ( 0x0000 )
  33 #define REG_PIN_CTRL1                   ( 0x0004 )
  34 #define REG_PIN_CTRL2                   ( 0x0008 )
  35 #define REG_PIN_CTRL3                   ( 0x000c )
  36 #define REG_PIN_TRACECLK                ( 0x0010 )
  37 #define REG_PIN_TRACECTRL               ( 0x0014 )
  38 #define REG_PIN_TRACEDAT0               ( 0x0018 )
  39 #define REG_PIN_TRACEDAT1               ( 0x001c )
  40 #define REG_PIN_TRACEDAT2               ( 0x0020 )
  41 #define REG_PIN_TRACEDAT3               ( 0x0024 )
  42 #define REG_PIN_TRACEDAT4               ( 0x0028 )
  43 #define REG_PIN_TRACEDAT5               ( 0x002c )
  44 #define REG_PIN_TRACEDAT6               ( 0x0030 )
  45 #define REG_PIN_TRACEDAT7               ( 0x0034 )
  46 #define REG_PIN_U0TXD                   ( 0x0038 )
  47 #define REG_PIN_U0RXD                   ( 0x003c )
  48 #define REG_PIN_U0CTS                   ( 0x0040 )
  49 #define REG_PIN_U0RTS                   ( 0x0044 )
  50 #define REG_PIN_U1TXD                   ( 0x0048 )
  51 #define REG_PIN_U1RXD                   ( 0x004c )
  52 #define REG_PIN_U2TXD                   ( 0x0050 )
  53 #define REG_PIN_U2RXD                   ( 0x0054 )
  54 #define REG_PIN_U2CTS                   ( 0x0058 )
  55 #define REG_PIN_U2RTS                   ( 0x005c )
  56 #define REG_PIN_U3TXD                   ( 0x0060 )
  57 #define REG_PIN_U3RXD                   ( 0x0064 )
  58 #define REG_PIN_U3CTS                   ( 0x0068 )
  59 #define REG_PIN_U3RTS                   ( 0x006c )
  60 #define REG_PIN_CP2_RFCTL0              ( 0x0070 )
  61 #define REG_PIN_CP2_RFCTL1              ( 0x0074 )
  62 #define REG_PIN_CP2_RFCTL2              ( 0x0078 )
  63 #define REG_PIN_WIFI_AGCGAIN3           ( 0x007c )
  64 #define REG_PIN_WIFI_AGCGAIN4           ( 0x0080 )
  65 #define REG_PIN_WIFI_AGCGAIN5           ( 0x0084 )
  66 #define REG_PIN_WIFI_AGCGAIN6           ( 0x0088 )
  67 #define REG_PIN_RFSDA0                  ( 0x008c )
  68 #define REG_PIN_RFSCK0                  ( 0x0090 )
  69 #define REG_PIN_RFSEN0                  ( 0x0094 )
  70 #define REG_PIN_CP_RFCTL0               ( 0x0098 )
  71 #define REG_PIN_CP_RFCTL1               ( 0x009c )
  72 #define REG_PIN_CP_RFCTL2               ( 0x00a0 )
  73 #define REG_PIN_CP_RFCTL3               ( 0x00a4 )
  74 #define REG_PIN_CP_RFCTL4               ( 0x00a8 )
  75 #define REG_PIN_CP_RFCTL5               ( 0x00ac )
  76 #define REG_PIN_CP_RFCTL6               ( 0x00b0 )
  77 #define REG_PIN_CP_RFCTL7               ( 0x00b4 )
  78 #define REG_PIN_CP_RFCTL8               ( 0x00b8 )
  79 #define REG_PIN_CP_RFCTL9               ( 0x00bc )
  80 #define REG_PIN_CP_RFCTL10              ( 0x00c0 )
  81 #define REG_PIN_CP_RFCTL11              ( 0x00c4 )
  82 #define REG_PIN_CP_RFCTL12              ( 0x00c8 )
  83 #define REG_PIN_CP_RFCTL13              ( 0x00cc )
  84 #define REG_PIN_CP_RFCTL14              ( 0x00d0 )
  85 #define REG_PIN_CP_RFCTL15              ( 0x00d4 )
  86 #define REG_PIN_XTLEN                   ( 0x00d8 )
  87 #define REG_PIN_SPI0_CSN                ( 0x00dc )
  88 #define REG_PIN_SPI0_DO                 ( 0x00e0 )
  89 #define REG_PIN_SPI0_DI                 ( 0x00e4 )
  90 #define REG_PIN_SPI0_CLK                ( 0x00e8 )
  91 #define REG_PIN_EXTINT0                 ( 0x00ec )
  92 #define REG_PIN_EXTINT1                 ( 0x00f0 )
  93 #define REG_PIN_SCL1                    ( 0x00f4 )
  94 #define REG_PIN_SDA1                    ( 0x00f8 )
  95 #define REG_PIN_SIMCLK0                 ( 0x00fc )
  96 #define REG_PIN_SIMDA0                  ( 0x0100 )
  97 #define REG_PIN_SIMRST0                 ( 0x0104 )
  98 #define REG_PIN_SIMCLK1                 ( 0x0108 )
  99 #define REG_PIN_SIMDA1                  ( 0x010c )
 100 #define REG_PIN_SIMRST1                 ( 0x0110 )
 101 #define REG_PIN_SIMCLK2                 ( 0x0114 )
 102 #define REG_PIN_SIMDA2                  ( 0x0118 )
 103 #define REG_PIN_SIMRST2                 ( 0x011c )
 104 #define REG_PIN_SD1_CLK                 ( 0x0120 )
 105 #define REG_PIN_SD1_CMD                 ( 0x0124 )
 106 #define REG_PIN_SD1_D0                  ( 0x0128 )
 107 #define REG_PIN_SD1_D1                  ( 0x012c )
 108 #define REG_PIN_SD1_D2                  ( 0x0130 )
 109 #define REG_PIN_SD1_D3                  ( 0x0134 )
 110 #define REG_PIN_SD0_D3                  ( 0x0138 )
 111 #define REG_PIN_SD0_D2                  ( 0x013c )
 112 #define REG_PIN_SD0_CMD                 ( 0x0140 )
 113 #define REG_PIN_SD0_D0                  ( 0x0144 )
 114 #define REG_PIN_SD0_D1                  ( 0x0148 )
 115 #define REG_PIN_SD0_CLK0                ( 0x014c )
 116 #define REG_PIN_PTEST                   ( 0x0150 )
 117 #define REG_PIN_ANA_INT                 ( 0x0154 )
 118 #define REG_PIN_EXT_RST_B               ( 0x0158 )
 119 #define REG_PIN_CHIP_SLEEP              ( 0x015c )
 120 #define REG_PIN_XTL_BUF_EN0             ( 0x0160 )
 121 #define REG_PIN_XTL_BUF_EN2             ( 0x0164 )
 122 #define REG_PIN_CLK_32K                 ( 0x0168 )
 123 #define REG_PIN_AUD_SCLK                ( 0x016c )
 124 #define REG_PIN_AUD_ADD0                ( 0x0170 )
 125 #define REG_PIN_AUD_ADSYNC              ( 0x0174 )
 126 #define REG_PIN_AUD_DAD1                ( 0x0178 )
 127 #define REG_PIN_AUD_DAD0                ( 0x017c )
 128 #define REG_PIN_AUD_DASYNC              ( 0x0180 )
 129 #define REG_PIN_ADI_D                   ( 0x0184 )
 130 #define REG_PIN_ADI_SYNC                ( 0x0188 )
 131 #define REG_PIN_ADI_SCLK                ( 0x018c )
 132 #define REG_PIN_LCD_CSN1                ( 0x0190 )
 133 #define REG_PIN_LCD_CSN0                ( 0x0194 )
 134 #define REG_PIN_LCD_RSTN                ( 0x0198 )
 135 #define REG_PIN_LCD_CD                  ( 0x019c )
 136 #define REG_PIN_LCD_FMARK               ( 0x01a0 )
 137 #define REG_PIN_LCD_WRN                 ( 0x01a4 )
 138 #define REG_PIN_LCD_RDN                 ( 0x01a8 )
 139 #define REG_PIN_LCD_D0                  ( 0x01ac )
 140 #define REG_PIN_LCD_D1                  ( 0x01b0 )
 141 #define REG_PIN_LCD_D2                  ( 0x01b4 )
 142 #define REG_PIN_LCD_D3                  ( 0x01b8 )
 143 #define REG_PIN_LCD_D4                  ( 0x01bc )
 144 #define REG_PIN_LCD_D5                  ( 0x01c0 )
 145 #define REG_PIN_LCD_D6                  ( 0x01c4 )
 146 #define REG_PIN_LCD_D7                  ( 0x01c8 )
 147 #define REG_PIN_LCD_D8                  ( 0x01cc )
 148 #define REG_PIN_LCD_D9                  ( 0x01d0 )
 149 #define REG_PIN_LCD_D10                 ( 0x01d4 )
 150 #define REG_PIN_LCD_D11                 ( 0x01d8 )
 151 #define REG_PIN_LCD_D12                 ( 0x01dc )
 152 #define REG_PIN_LCD_D13                 ( 0x01e0 )
 153 #define REG_PIN_LCD_D14                 ( 0x01e4 )
 154 #define REG_PIN_LCD_D15                 ( 0x01e8 )
 155 #define REG_PIN_LCD_D16                 ( 0x01ec )
 156 #define REG_PIN_LCD_D17                 ( 0x01f0 )
 157 #define REG_PIN_LCD_D18                 ( 0x01f4 )
 158 #define REG_PIN_LCD_D19                 ( 0x01f8 )
 159 #define REG_PIN_LCD_D20                 ( 0x01fc )
 160 #define REG_PIN_LCD_D21                 ( 0x0200 )
 161 #define REG_PIN_LCD_D22                 ( 0x0204 )
 162 #define REG_PIN_LCD_D23                 ( 0x0208 )
 163 #define REG_PIN_SPI2_CSN                ( 0x020c )
 164 #define REG_PIN_SPI2_DO                 ( 0x0210 )
 165 #define REG_PIN_SPI2_DI                 ( 0x0214 )
 166 #define REG_PIN_SPI2_CLK                ( 0x0218 )
 167 #define REG_PIN_NFWPN                   ( 0x021c )
 168 #define REG_PIN_NFRB                    ( 0x0220 )
 169 #define REG_PIN_NFCLE                   ( 0x0224 )
 170 #define REG_PIN_NFALE                   ( 0x0228 )
 171 #define REG_PIN_NFCEN0                  ( 0x022c )
 172 #define REG_PIN_NFCEN1                  ( 0x0230 )
 173 #define REG_PIN_NFREN                   ( 0x0234 )
 174 #define REG_PIN_NFWEN                   ( 0x0238 )
 175 #define REG_PIN_NFD0                    ( 0x023c )
 176 #define REG_PIN_NFD1                    ( 0x0240 )
 177 #define REG_PIN_NFD2                    ( 0x0244 )
 178 #define REG_PIN_NFD3                    ( 0x0248 )
 179 #define REG_PIN_NFD4                    ( 0x024c )
 180 #define REG_PIN_NFD5                    ( 0x0250 )
 181 #define REG_PIN_NFD6                    ( 0x0254 )
 182 #define REG_PIN_NFD7                    ( 0x0258 )
 183 #define REG_PIN_NFD8                    ( 0x025c )
 184 #define REG_PIN_NFD9                    ( 0x0260 )
 185 #define REG_PIN_NFD10                   ( 0x0264 )
 186 #define REG_PIN_NFD11                   ( 0x0268 )
 187 #define REG_PIN_NFD12                   ( 0x026c )
 188 #define REG_PIN_NFD13                   ( 0x0270 )
 189 #define REG_PIN_NFD14                   ( 0x0274 )
 190 #define REG_PIN_NFD15                   ( 0x0278 )
 191 #define REG_PIN_CCIRCK0                 ( 0x027c )
 192 #define REG_PIN_CCIRCK1                 ( 0x0280 )
 193 #define REG_PIN_CCIRMCLK                ( 0x0284 )
 194 #define REG_PIN_CCIRHS                  ( 0x0288 )
 195 #define REG_PIN_CCIRVS                  ( 0x028c )
 196 #define REG_PIN_CCIRD0                  ( 0x0290 )
 197 #define REG_PIN_CCIRD1                  ( 0x0294 )
 198 #define REG_PIN_CCIRD2                  ( 0x0298 )
 199 #define REG_PIN_CCIRD3                  ( 0x029c )
 200 #define REG_PIN_CCIRD4                  ( 0x02a0 )
 201 #define REG_PIN_CCIRD5                  ( 0x02a4 )
 202 #define REG_PIN_CCIRD6                  ( 0x02a8 )
 203 #define REG_PIN_CCIRD7                  ( 0x02ac )
 204 #define REG_PIN_CCIRD8                  ( 0x02b0 )
 205 #define REG_PIN_CCIRD9                  ( 0x02b4 )
 206 #define REG_PIN_CCIRRST                 ( 0x02b8 )
 207 #define REG_PIN_CCIRPD1                 ( 0x02bc )
 208 #define REG_PIN_CCIRPD0                 ( 0x02c0 )
 209 #define REG_PIN_SCL0                    ( 0x02c4 )
 210 #define REG_PIN_SDA0                    ( 0x02c8 )
 211 #define REG_PIN_KEYOUT0                 ( 0x02cc )
 212 #define REG_PIN_KEYOUT1                 ( 0x02d0 )
 213 #define REG_PIN_KEYOUT2                 ( 0x02d4 )
 214 #define REG_PIN_KEYIN0                  ( 0x02d8 )
 215 #define REG_PIN_KEYIN1                  ( 0x02dc )
 216 #define REG_PIN_KEYIN2                  ( 0x02e0 )
 217 #define REG_PIN_SCL2                    ( 0x02e4 )
 218 #define REG_PIN_SDA2                    ( 0x02e8 )
 219 #define REG_PIN_CLK_AUX0                ( 0x02ec )
 220 #define REG_PIN_IIS0DI                  ( 0x02f0 )
 221 #define REG_PIN_IIS0DO                  ( 0x02f4 )
 222 #define REG_PIN_IIS0CLK                 ( 0x02f8 )
 223 #define REG_PIN_IIS0LRCK                ( 0x02fc )
 224 #define REG_PIN_IIS0MCK                 ( 0x0300 )
 225 #define REG_PIN_MTDO                    ( 0x0304 )
 226 #define REG_PIN_MTDI                    ( 0x0308 )
 227 #define REG_PIN_MTCK                    ( 0x030c )
 228 #define REG_PIN_MTMS                    ( 0x0310 )
 229 #define REG_PIN_MTRST_N                 ( 0x0314 )
 230
 231 #elif defined(CONFIG_SPX20)
 232 /* registers definitions for controller CTL_PIN */
 233 #define REG_PIN_CTRL0                   ( 0x0000 )
 234 #define REG_PIN_CTRL1                   ( 0x0004 )
 235 #define REG_PIN_CTRL2                   ( 0x0008 )
 236 #define REG_PIN_CTRL3                   ( 0x000c )
 237 #define REG_PIN_CTRL4                   ( 0x0010 )
 238 #define REG_PIN_CTRL5                   ( 0x0014 )
 239 #define REG_PIN_CTRL6                   ( 0x0018 )
 240 #define REG_PIN_CTRL7                   ( 0x001c )
 241
 242 #define  REG_PIN_RFSDA0                 ( 0x0020 )
 243 #define  REG_PIN_RFSCK0                 ( 0x0024 )
 244 #define  REG_PIN_RFSEN0                 ( 0x0028 )
 245 #define  REG_PIN_RFCTL0                 ( 0x002c )
 246 #define  REG_PIN_RFCTL1                 ( 0x0030 )
 247 #define  REG_PIN_RFCTL2                 ( 0x0034 )
 248 #define  REG_PIN_RFCTL3                 ( 0x0038 )
 249 #define  REG_PIN_RFCTL4                 ( 0x003c )
 250 #define  REG_PIN_RFCTL5                 ( 0x0040 )
 251 #define  REG_PIN_RFCTL6                 ( 0x0044 )
 252 #define  REG_PIN_RFCTL7                 ( 0x0048 )
 253 #define  REG_PIN_RFCTL8                 ( 0x004c )
 254 #define  REG_PIN_RFCTL9                 ( 0x0050 )
 255 #define  REG_PIN_RFCTL10                ( 0x0054 )
 256 #define  REG_PIN_RFCTL11                ( 0x0058 )
 257 #define  REG_PIN_RFCTL12                ( 0x005c )
 258 #define  REG_PIN_RFCTL13                ( 0x0060 )
 259 #define  REG_PIN_RFCTL14                ( 0x0064 )
 260 #define  REG_PIN_RFCTL15                ( 0x0068 )
 261 #define  REG_PIN_PTEST                  ( 0x006c )
 262 #define  REG_PIN_ANA_INT                ( 0x0070 )
 263 #define  REG_PIN_EXT_RST_B              ( 0x0074 )
 264 #define  REG_PIN_CHIP_SLEEP             ( 0x0078 )
 265 #define  REG_PIN_XTL_BUF_EN0            ( 0x007c )
 266 #define  REG_PIN_XTL_BUF_EN1            ( 0x0080 )
 267 #define  REG_PIN_CLK_32K                ( 0x0084 )
 268 #define  REG_PIN_AUD_SCLK               ( 0x0088 )
 269 #define  REG_PIN_AUD_ADD0               ( 0x008c )
 270 #define  REG_PIN_AUD_ADSYNC             ( 0x0090 )
 271 #define  REG_PIN_AUD_DAD1               ( 0x0094 )
 272 #define  REG_PIN_AUD_DAD0               ( 0x0098 )
 273 #define  REG_PIN_AUD_DASYNC             ( 0x009c )
 274 #define  REG_PIN_ADI_D                  ( 0x00a0 )
 275 #define  REG_PIN_ADI_SYNC               ( 0x00a4 )
 276 #define  REG_PIN_ADI_SCLK               ( 0x00a8 )
 277 #define  REG_PIN_LCD_RSTN               ( 0x00ac )
 278 #define  REG_PIN_LCD_FMARK              ( 0x00b0 )
 279 #define  REG_PIN_SPI1_CSN               ( 0x00b4 )
 280 #define  REG_PIN_SPI1_DO                ( 0x00b8 )
 281 #define  REG_PIN_SPI1_DI                ( 0x00bc )
 282 #define  REG_PIN_SPI1_CLK               ( 0x00c0 )
 283 #define  REG_PIN_NFWPN                  ( 0x00c4 )
 284 #define  REG_PIN_NFRBN                  ( 0x00c8 )
 285 #define  REG_PIN_NFCLE                  ( 0x00cc )
 286 #define  REG_PIN_NFALE                  ( 0x00d0 )
 287 #define  REG_PIN_NFREN                  ( 0x00d4 )
 288 #define  REG_PIN_NFD4                   ( 0x00d8 )
 289 #define  REG_PIN_NFD5                   ( 0x00dc )
 290 #define  REG_PIN_NFD6                   ( 0x00e0 )
 291 #define  REG_PIN_NFD7                   ( 0x00e4 )
 292 #define  REG_PIN_NFD10                  ( 0x00e8 )
 293 #define  REG_PIN_NFD11                  ( 0x00ec )
 294 #define  REG_PIN_NFD14                  ( 0x00f0 )
 295 #define  REG_PIN_NFCEN0                 ( 0x00f4 )
 296 #define  REG_PIN_NFCEN1                 ( 0x00f8 )
 297 #define  REG_PIN_NFWEN                  ( 0x00fc )
 298 #define  REG_PIN_NFD0                   ( 0x0100 )
 299 #define  REG_PIN_NFD1                   ( 0x0104 )
 300 #define  REG_PIN_NFD2                   ( 0x0108 )
 301 #define  REG_PIN_NFD3                   ( 0x010c )
 302 #define  REG_PIN_NFD8                   ( 0x0110 )
 303 #define  REG_PIN_NFD9                   ( 0x0114 )
 304 #define  REG_PIN_NFD12                  ( 0x0118 )
 305 #define  REG_PIN_NFD13                  ( 0x011c )
 306 #define  REG_PIN_NFD15                  ( 0x0120 )
 307 #define  REG_PIN_CCIRMCLK               ( 0x0124 )
 308 #define  REG_PIN_CCIRRST                ( 0x0128 )
 309 #define  REG_PIN_CCIRPD1                ( 0x012c )
 310 #define  REG_PIN_CCIRPD0                ( 0x0130 )
 311 #define  REG_PIN_SCL0                   ( 0x0134 )
 312 #define  REG_PIN_SDA0                   ( 0x0138 )
 313 #define  REG_PIN_KEYOUT0                ( 0x013c )
 314 #define  REG_PIN_KEYOUT1                ( 0x0140 )
 315 #define  REG_PIN_KEYOUT2                ( 0x0144 )
 316 #define  REG_PIN_KEYIN0                 ( 0x0148 )
 317 #define  REG_PIN_KEYIN1                 ( 0x014c )
 318 #define  REG_PIN_KEYIN2                 ( 0x0150 )
 319 #define  REG_PIN_CLK_AUX0               ( 0x0154 )
 320 #define  REG_PIN_CLK_AUX1               ( 0x0158 )
 321 #define  REG_PIN_IIS0DI                 ( 0x015c )
 322 #define  REG_PIN_IIS0DO                 ( 0x0160 )
 323 #define  REG_PIN_IIS0CLK                ( 0x0164 )
 324 #define  REG_PIN_IIS0LRCK               ( 0x0168 )
 325 #define  REG_PIN_MTDO                   ( 0x016c )
 326 #define  REG_PIN_MTDI                   ( 0x0170 )
 327 #define  REG_PIN_MTCK                   ( 0x0174 )
 328 #define  REG_PIN_MTMS                   ( 0x0178 )
 329 #define  REG_PIN_MTRST_N                ( 0x017c )
 330 #define  REG_PIN_TRACECLK               ( 0x0180 )
 331 #define  REG_PIN_TRACECTRL              ( 0x0184 )
 332 #define  REG_PIN_TRACEDAT0              ( 0x0188 )
 333 #define  REG_PIN_TRACEDAT1              ( 0x018c )
 334 #define  REG_PIN_TRACEDAT2              ( 0x0190 )
 335 #define  REG_PIN_TRACEDAT3              ( 0x0194 )
 336 #define  REG_PIN_TRACEDAT4              ( 0x0198 )
 337 #define  REG_PIN_TRACEDAT5              ( 0x019c )
 338 #define  REG_PIN_TRACEDAT6              ( 0x01a0 )
 339 #define  REG_PIN_TRACEDAT7              ( 0x01a4 )
 340 #define  REG_PIN_U0TXD                  ( 0x01a8 )
 341 #define  REG_PIN_U0RXD                  ( 0x01ac )
 342 #define  REG_PIN_U0CTS                  ( 0x01b0 )
 343 #define  REG_PIN_U0RTS                  ( 0x01b4 )
 344 #define  REG_PIN_U1TXD                  ( 0x01b8 )
 345 #define  REG_PIN_U1RXD                  ( 0x01bc )
 346 #define  REG_PIN_U2TXD                  ( 0x01c0 )
 347 #define  REG_PIN_U2RXD                  ( 0x01c4 )
 348 #define  REG_PIN_U2CTS                  ( 0x01c8 )
 349 #define  REG_PIN_U2RTS                  ( 0x01cc )
 350 #define  REG_PIN_SCL2                   ( 0x01d0 )
 351 #define  REG_PIN_SDA2                   ( 0x01d4 )
 352 #define  REG_PIN_EXTINT0                ( 0x01d8 )
 353 #define  REG_PIN_EXTINT1                ( 0x01dc )
 354 #define  REG_PIN_SCL1                   ( 0x01e0 )
 355 #define  REG_PIN_SDA1                   ( 0x01e4 )
 356 #define  REG_PIN_SIMCLK0                ( 0x01e8 )
 357 #define  REG_PIN_SIMDA0                 ( 0x01ec )
 358 #define  REG_PIN_SIMRST0                ( 0x01f0 )
 359 #define  REG_PIN_SIMCLK1                ( 0x01f4 )
 360 #define  REG_PIN_SIMDA1                 ( 0x01f8 )
 361 #define  REG_PIN_SIMRST1                ( 0x01fc )
 362 #define  REG_PIN_SIMCLK2                ( 0x0200 )
 363 #define  REG_PIN_SIMDA2                 ( 0x0204 )
 364 #define  REG_PIN_SIMRST2                ( 0x0208 )
 365 #define  REG_PIN_SD1_CLK                ( 0x020c )
 366 #define  REG_PIN_SD1_CMD                ( 0x0210 )
 367 #define  REG_PIN_SD1_D0                 ( 0x0214 )
 368 #define  REG_PIN_SD1_D1                 ( 0x0218 )
 369 #define  REG_PIN_SD1_D2                 ( 0x021c )
 370 #define  REG_PIN_SD1_D3                 ( 0x0220 )
 371 #define  REG_PIN_SD0_D3                 ( 0x0224 )
 372 #define  REG_PIN_SD0_D2                 ( 0x0228 )
 373 #define  REG_PIN_SD0_CMD                ( 0x022c )
 374 #define  REG_PIN_SD0_D0                 ( 0x0230 )
 375 #define  REG_PIN_SD0_D1                 ( 0x0234 )
 376 #define  REG_PIN_SD0_CLK0               ( 0x0238 )
 377 #define  REG_PIN_RF_ADC_ON              ( 0x023c )
 378 #define  REG_PIN_RF_DAC_ON              ( 0x0240 )
 379 #define  REG_PIN_EMD4                   ( 0x0244 )
 380 #define  REG_PIN_EMD7                   ( 0x0248 )
 381 #define  REG_PIN_EMD5                   ( 0x024c )
 382 #define  REG_PIN_EMDQS0                 ( 0x0250 )
 383 #define  REG_PIN_EMDQS_N0               ( 0x0254 )
 384 #define  REG_PIN_EMD2                   ( 0x0258 )
 385 #define  REG_PIN_EMD1                   ( 0x025c )
 386 #define  REG_PIN_EMD0                   ( 0x0260 )
 387 #define  REG_PIN_EMD6                   ( 0x0264 )
 388 #define  REG_PIN_EMD3                   ( 0x0268 )
 389 #define  REG_PIN_EMDQM0                 ( 0x026c )
 390 #define  REG_PIN_EMD13                  ( 0x0270 )
 391 #define  REG_PIN_EMD12                  ( 0x0274 )
 392 #define  REG_PIN_EMD15                  ( 0x0278 )
 393 #define  REG_PIN_EMDQS1                 ( 0x027c )
 394 #define  REG_PIN_EMDQS_N1               ( 0x0280 )
 395 #define  REG_PIN_EMD9                   ( 0x0284 )
 396 #define  REG_PIN_EMD11                  ( 0x0288 )
 397 #define  REG_PIN_EMD10                  ( 0x028c )
 398 #define  REG_PIN_EMD8                   ( 0x0290 )
 399 #define  REG_PIN_EMD14                  ( 0x0294 )
 400 #define  REG_PIN_EMDQM1                 ( 0x0298 )
 401 #define  REG_PIN_EMZQ                   ( 0x029c )
 402 #define  REG_PIN_EMA3                   ( 0x02a0 )
 403 #define  REG_PIN_EMA2                   ( 0x02a4 )
 404 #define  REG_PIN_EMA1                   ( 0x02a8 )
 405 #define  REG_PIN_EMA6                   ( 0x02ac )
 406 #define  REG_PIN_CLKDPMEM               ( 0x02b0 )
 407 #define  REG_PIN_CLKDMMEM               ( 0x02b4 )
 408 #define  REG_PIN_EMCKE1                 ( 0x02b8 )
 409 #define  REG_PIN_EMCKE0                 ( 0x02bc )
 410 #define  REG_PIN_EMA8                   ( 0x02c0 )
 411 #define  REG_PIN_EMA7                   ( 0x02c4 )
 412 #define  REG_PIN_EMA5                   ( 0x02c8 )
 413 #define  REG_PIN_EMA4                   ( 0x02cc )
 414 #define  REG_PIN_EMA9                   ( 0x02d0 )
 415 #define  REG_PIN_EMA0                   ( 0x02d4 )
 416 #define  REG_PIN_EMCS_N1                ( 0x02d8 )
 417 #define  REG_PIN_EMCS_N0                ( 0x02dc )
 418 #define  REG_PIN_EMD22                  ( 0x02e0 )
 419 #define  REG_PIN_EMD21                  ( 0x02e4 )
 420 #define  REG_PIN_EMD23                  ( 0x02e8 )
 421 #define  REG_PIN_EMDQS2                 ( 0x02ec )
 422 #define  REG_PIN_EMDQS_N2               ( 0x02f0 )
 423 #define  REG_PIN_EMD20                  ( 0x02f4 )
 424 #define  REG_PIN_EMD18                  ( 0x02f8 )
 425 #define  REG_PIN_EMD16                  ( 0x02fc )
 426 #define  REG_PIN_EMD19                  ( 0x0300 )
 427 #define  REG_PIN_EMD17                  ( 0x0304 )
 428 #define  REG_PIN_EMDQM2                 ( 0x0308 )
 429 #define  REG_PIN_EMD28                  ( 0x030c )
 430 #define  REG_PIN_EMD29                  ( 0x0310 )
 431 #define  REG_PIN_EMD31                  ( 0x0314 )
 432 #define  REG_PIN_EMDQS3                 ( 0x0318 )
 433 #define  REG_PIN_EMDQS_N3               ( 0x031c )
 434 #define  REG_PIN_EMD30                  ( 0x0320 )
 435 #define  REG_PIN_EMD26                  ( 0x0324 )
 436 #define  REG_PIN_EMD27                  ( 0x0328 )
 437 #define  REG_PIN_EMD25                  ( 0x032c )
 438 #define  REG_PIN_EMD24                  ( 0x0330 )
 439 #define  REG_PIN_EMDQM3                 ( 0x0334 )
 440 #define  REG_PIN_CP2_RFCTL0             ( 0x0338 )
 441 #define  REG_PIN_CP2_RFCTL1             ( 0x033c )
 442 #define  REG_PIN_CP2_RFCTL2             ( 0x0340 )
 443
 444 #elif defined(CONFIG_SPX30G)
 445 /* registers definitions for controller CTL_PIN */
 446 #define REG_PIN_CTRL0                   ( 0x0000 )
 447 #define REG_PIN_CTRL1                   ( 0x0004 )
 448 #define REG_PIN_CTRL2                   ( 0x0008 )
 449 #define REG_PIN_CTRL3                   ( 0x000c )
 450 #define REG_PIN_CTRL4                   ( 0x0010 )
 451 #define REG_PIN_CTRL5                   ( 0x0014 )
 452
 453 #define REG_PIN_TRACECLK                ( 0x0020 )
 454 #define REG_PIN_TRACECTRL               ( 0x0024 )
 455 #define REG_PIN_TRACEDAT0               ( 0x0028 )
 456 #define REG_PIN_TRACEDAT1               ( 0x002c )
 457 #define REG_PIN_TRACEDAT2               ( 0x0030 )
 458 #define REG_PIN_TRACEDAT3               ( 0x0034 )
 459 #define REG_PIN_TRACEDAT4               ( 0x0038 )
 460 #define REG_PIN_TRACEDAT5               ( 0x003c )
 461 #define REG_PIN_TRACEDAT6               ( 0x0040 )
 462 #define REG_PIN_TRACEDAT7               ( 0x0044 )
 463 #define REG_PIN_U0TXD                   ( 0x0048 )
 464 #define REG_PIN_U0RXD                   ( 0x004c )
 465 #define REG_PIN_U0CTS                   ( 0x0050 )
 466 #define REG_PIN_U0RTS                   ( 0x0054 )
 467 #define REG_PIN_U1TXD                   ( 0x0058 )
 468 #define REG_PIN_U1RXD                   ( 0x005c )
 469 #define REG_PIN_U2TXD                   ( 0x0060 )
 470 #define REG_PIN_U2RXD                   ( 0x0064 )
 471 #define REG_PIN_U3TXD                   ( 0x0068 )
 472 #define REG_PIN_U3RXD                   ( 0x006c )
 473 #define REG_PIN_U3CTS                   ( 0x0070 )
 474 #define REG_PIN_U3RTS                   ( 0x0074 )
 475 #define REG_PIN_CP2_RFCTL0              ( 0x0078 )
 476 #define REG_PIN_CP2_RFCTL1              ( 0x007c )
 477 #define REG_PIN_CP2_RFCTL2              ( 0x0080 )
 478 #define REG_PIN_WIFI_AGCGAIN3           ( 0x0084 )
 479 #define REG_PIN_WIFI_AGCGAIN4           ( 0x0088 )
 480 #define REG_PIN_WIFI_AGCGAIN5           ( 0x008c )
 481 #define REG_PIN_WIFI_AGCGAIN6           ( 0x0090 )
 482 #define REG_PIN_RFSDA0                  ( 0x0094 )
 483 #define REG_PIN_RFSCK0                  ( 0x0098 )
 484 #define REG_PIN_RFSEN0                  ( 0x009c )
 485 #define REG_PIN_RFSDA1                  ( 0x00a0 )
 486 #define REG_PIN_RFSCK1                  ( 0x00a4 )
 487 #define REG_PIN_RFSEN1                  ( 0x00a8 )
 488 #define REG_PIN_CP1_RFCTL0              ( 0x00ac )
 489 #define REG_PIN_CP1_RFCTL1              ( 0x00b0 )
 490 #define REG_PIN_CP1_RFCTL2              ( 0x00b4 )
 491 #define REG_PIN_CP1_RFCTL3              ( 0x00b8 )
 492 #define REG_PIN_CP1_RFCTL4              ( 0x00bc )
 493 #define REG_PIN_CP1_RFCTL5              ( 0x00c0 )
 494 #define REG_PIN_CP1_RFCTL6              ( 0x00c4 )
 495 #define REG_PIN_CP1_RFCTL7              ( 0x00c8 )
 496 #define REG_PIN_CP1_RFCTL8              ( 0x00cc )
 497 #define REG_PIN_CP1_RFCTL9              ( 0x00d0 )
 498 #define REG_PIN_CP1_RFCTL10             ( 0x00d4 )
 499 #define REG_PIN_CP1_RFCTL11             ( 0x00d8 )
 500 #define REG_PIN_CP1_RFCTL12             ( 0x00dc )
 501 #define REG_PIN_CP1_RFCTL13             ( 0x00e0 )
 502 #define REG_PIN_CP1_RFCTL14             ( 0x00e4 )
 503 #define REG_PIN_CP1_RFCTL15             ( 0x00e8 )
 504 #define REG_PIN_CP0_RFCTL0              ( 0x00ec )
 505 #define REG_PIN_CP0_RFCTL1              ( 0x00f0 )
 506 #define REG_PIN_CP0_RFCTL2              ( 0x00f4 )
 507 #define REG_PIN_CP0_RFCTL3              ( 0x00f8 )
 508 #define REG_PIN_CP0_RFCTL4              ( 0x00fc )
 509 #define REG_PIN_CP0_RFCTL5              ( 0x0100 )
 510 #define REG_PIN_CP0_RFCTL6              ( 0x0104 )
 511 #define REG_PIN_CP0_RFCTL7              ( 0x0108 )
 512 #define REG_PIN_XTLEN                   ( 0x010c )
 513 #define REG_PIN_SCL3                    ( 0x0110 )
 514 #define REG_PIN_SDA3                    ( 0x0114 )
 515 #define REG_PIN_SPI0_CSN                ( 0x0118 )
 516 #define REG_PIN_SPI0_DO                 ( 0x011c )
 517 #define REG_PIN_SPI0_DI                 ( 0x0120 )
 518 #define REG_PIN_SPI0_CLK                ( 0x0124 )
 519 #define REG_PIN_EXTINT0                 ( 0x0128 )
 520 #define REG_PIN_EXTINT1                 ( 0x012c )
 521 #define REG_PIN_SCL1                    ( 0x0130 )
 522 #define REG_PIN_SDA1                    ( 0x0134 )
 523 #define REG_PIN_SIMCLK0                 ( 0x0138 )
 524 #define REG_PIN_SIMDA0                  ( 0x013c )
 525 #define REG_PIN_SIMRST0                 ( 0x0140 )
 526 #define REG_PIN_SIMCLK1                 ( 0x0144 )
 527 #define REG_PIN_SIMDA1                  ( 0x0148 )
 528 #define REG_PIN_SIMRST1                 ( 0x014c )
 529 #define REG_PIN_SIMCLK2                 ( 0x0150 )
 530 #define REG_PIN_SIMDA2                  ( 0x0154 )
 531 #define REG_PIN_SIMRST2                 ( 0x0158 )
 532 #define REG_PIN_MEMS_MIC_CLK0           ( 0x015c )
 533 #define REG_PIN_MEMS_MIC_DATA0          ( 0x0160 )
 534 #define REG_PIN_MEMS_MIC_CLK1           ( 0x0164 )
 535 #define REG_PIN_MEMS_MIC_DATA1          ( 0x0168 )
 536 #define REG_PIN_SD1_CLK                 ( 0x016c )
 537 #define REG_PIN_SD1_CMD                 ( 0x0170 )
 538 #define REG_PIN_SD1_D0                  ( 0x0174 )
 539 #define REG_PIN_SD1_D1                  ( 0x0178 )
 540 #define REG_PIN_SD1_D2                  ( 0x017c )
 541 #define REG_PIN_SD1_D3                  ( 0x0180 )
 542 #define REG_PIN_SD0_D3                  ( 0x0184 )
 543 #define REG_PIN_SD0_D2                  ( 0x0188 )
 544 #define REG_PIN_SD0_CMD                 ( 0x018c )
 545 #define REG_PIN_SD0_D0                  ( 0x0190 )
 546 #define REG_PIN_SD0_D1                  ( 0x0194 )
 547 #define REG_PIN_SD0_CLK1                ( 0x0198 )
 548 #define REG_PIN_SD0_CLK0                ( 0x019c )
 549 #define REG_PIN_PTEST                   ( 0x01a0 )
 550 #define REG_PIN_ANA_INT                 ( 0x01a4 )
 551 #define REG_PIN_EXT_RST_B               ( 0x01a8 )
 552 #define REG_PIN_CHIP_SLEEP              ( 0x01ac )
 553 #define REG_PIN_XTL_BUF_EN0             ( 0x01b0 )
 554 #define REG_PIN_XTL_BUF_EN1             ( 0x01b4 )
 555 #define REG_PIN_XTL_BUF_EN2             ( 0x01b8 )
 556 #define REG_PIN_CLK_32K                 ( 0x01bc )
 557 #define REG_PIN_AUD_SCLK                ( 0x01c0 )
 558 #define REG_PIN_AUD_DANGL               ( 0x01c4 )
 559 #define REG_PIN_AUD_DANGR               ( 0x01c8 )
 560 #define REG_PIN_AUD_ADD0                ( 0x01cc )
 561 #define REG_PIN_AUD_ADSYNC              ( 0x01d0 )
 562 #define REG_PIN_AUD_DAD1                ( 0x01d4 )
 563 #define REG_PIN_AUD_DAD0                ( 0x01d8 )
 564 #define REG_PIN_AUD_DASYNC              ( 0x01dc )
 565 #define REG_PIN_ADI_D                   ( 0x01e0 )
 566 #define REG_PIN_ADI_SYNC                ( 0x01e4 )
 567 #define REG_PIN_ADI_SCLK                ( 0x01e8 )
 568 #define REG_PIN_LCD_CSN1                ( 0x01ec )
 569 #define REG_PIN_LCD_CSN0                ( 0x01f0 )
 570 #define REG_PIN_LCD_RSTN                ( 0x01f4 )
 571 #define REG_PIN_LCD_CD                  ( 0x01f8 )
 572 #define REG_PIN_LCD_FMARK               ( 0x01fc )
 573 #define REG_PIN_LCD_WRN                 ( 0x0200 )
 574 #define REG_PIN_LCD_RDN                 ( 0x0204 )
 575 #define REG_PIN_LCD_D0                  ( 0x0208 )
 576 #define REG_PIN_LCD_D1                  ( 0x020c )
 577 #define REG_PIN_LCD_D2                  ( 0x0210 )
 578 #define REG_PIN_LCD_D3                  ( 0x0214 )
 579 #define REG_PIN_LCD_D4                  ( 0x0218 )
 580 #define REG_PIN_LCD_D5                  ( 0x021c )
 581 #define REG_PIN_LCD_D6                  ( 0x0220 )
 582 #define REG_PIN_LCD_D7                  ( 0x0224 )
 583 #define REG_PIN_LCD_D8                  ( 0x0228 )
 584 #define REG_PIN_LCD_D9                  ( 0x022c )
 585 #define REG_PIN_LCD_D10                 ( 0x0230 )
 586 #define REG_PIN_LCD_D11                 ( 0x0234 )
 587 #define REG_PIN_LCD_D12                 ( 0x0238 )
 588 #define REG_PIN_LCD_D13                 ( 0x023c )
 589 #define REG_PIN_LCD_D14                 ( 0x0240 )
 590 #define REG_PIN_LCD_D15                 ( 0x0244 )
 591 #define REG_PIN_LCD_D16                 ( 0x0248 )
 592 #define REG_PIN_LCD_D17                 ( 0x024c )
 593 #define REG_PIN_LCD_D18                 ( 0x0250 )
 594 #define REG_PIN_LCD_D19                 ( 0x0254 )
 595 #define REG_PIN_LCD_D20                 ( 0x0258 )
 596 #define REG_PIN_LCD_D21                 ( 0x025c )
 597 #define REG_PIN_LCD_D22                 ( 0x0260 )
 598 #define REG_PIN_LCD_D23                 ( 0x0264 )
 599 #define REG_PIN_SPI2_CSN                ( 0x0268 )
 600 #define REG_PIN_SPI2_DO                 ( 0x026c )
 601 #define REG_PIN_SPI2_DI                 ( 0x0270 )
 602 #define REG_PIN_SPI2_CLK                ( 0x0274 )
 603 #define REG_PIN_EMMC_CLK                ( 0x0278 )
 604 #define REG_PIN_EMMC_CMD                ( 0x027c )
 605 #define REG_PIN_EMMC_D0                 ( 0x0280 )
 606 #define REG_PIN_EMMC_D1                 ( 0x0284 )
 607 #define REG_PIN_EMMC_D2                 ( 0x0288 )
 608 #define REG_PIN_EMMC_D3                 ( 0x028c )
 609 #define REG_PIN_EMMC_D4                 ( 0x0290 )
 610 #define REG_PIN_EMMC_D5                 ( 0x0294 )
 611 #define REG_PIN_EMMC_D6                 ( 0x0298 )
 612 #define REG_PIN_EMMC_D7                 ( 0x029c )
 613 #define REG_PIN_EMMC_RST                ( 0x02a0 )
 614 #define REG_PIN_NFWPN                   ( 0x02a4 )
 615 #define REG_PIN_NFRB                    ( 0x02a8 )
 616 #define REG_PIN_NFCLE                   ( 0x02ac )
 617 #define REG_PIN_NFALE                   ( 0x02b0 )
 618 #define REG_PIN_NFCEN0                  ( 0x02b4 )
 619 #define REG_PIN_NFCEN1                  ( 0x02b8 )
 620 #define REG_PIN_NFREN                   ( 0x02bc )
 621 #define REG_PIN_NFWEN                   ( 0x02c0 )
 622 #define REG_PIN_NFD0                    ( 0x02c4 )
 623 #define REG_PIN_NFD1                    ( 0x02c8 )
 624 #define REG_PIN_NFD2                    ( 0x02cc )
 625 #define REG_PIN_NFD3                    ( 0x02d0 )
 626 #define REG_PIN_NFD4                    ( 0x02d4 )
 627 #define REG_PIN_NFD5                    ( 0x02d8 )
 628 #define REG_PIN_NFD6                    ( 0x02dc )
 629 #define REG_PIN_NFD7                    ( 0x02e0 )
 630 #define REG_PIN_NFD8                    ( 0x02e4 )
 631 #define REG_PIN_NFD9                    ( 0x02e8 )
 632 #define REG_PIN_NFD10                   ( 0x02ec )
 633 #define REG_PIN_NFD11                   ( 0x02f0 )
 634 #define REG_PIN_NFD12                   ( 0x02f4 )
 635 #define REG_PIN_NFD13                   ( 0x02f8 )
 636 #define REG_PIN_NFD14                   ( 0x02fc )
 637 #define REG_PIN_NFD15                   ( 0x0300 )
 638 #define REG_PIN_CCIRCK0                 ( 0x0304 )
 639 #define REG_PIN_CCIRCK1                 ( 0x0308 )
 640 #define REG_PIN_CCIRMCLK                ( 0x030c )
 641 #define REG_PIN_CCIRHS                  ( 0x0310 )
 642 #define REG_PIN_CCIRVS                  ( 0x0314 )
 643 #define REG_PIN_CCIRD0                  ( 0x0318 )
 644 #define REG_PIN_CCIRD1                  ( 0x031c )
 645 #define REG_PIN_CCIRD2                  ( 0x0320 )
 646 #define REG_PIN_CCIRD3                  ( 0x0324 )
 647 #define REG_PIN_CCIRD4                  ( 0x0328 )
 648 #define REG_PIN_CCIRD5                  ( 0x032c )
 649 #define REG_PIN_CCIRD6                  ( 0x0330 )
 650 #define REG_PIN_CCIRD7                  ( 0x0334 )
 651 #define REG_PIN_CCIRD8                  ( 0x0338 )
 652 #define REG_PIN_CCIRD9                  ( 0x033c )
 653 #define REG_PIN_CCIRRST                 ( 0x0340 )
 654 #define REG_PIN_CCIRPD1                 ( 0x0344 )
 655 #define REG_PIN_CCIRPD0                 ( 0x0348 )
 656 #define REG_PIN_SCL0                    ( 0x034c )
 657 #define REG_PIN_SDA0                    ( 0x0350 )
 658 #define REG_PIN_KEYOUT0                 ( 0x0354 )
 659 #define REG_PIN_KEYOUT1                 ( 0x0358 )
 660 #define REG_PIN_KEYOUT2                 ( 0x035c )
 661 #define REG_PIN_KEYIN0                  ( 0x0360 )
 662 #define REG_PIN_KEYIN1                  ( 0x0364 )
 663 #define REG_PIN_KEYIN2                  ( 0x0368 )
 664 #define REG_PIN_SCL2                    ( 0x036c )
 665 #define REG_PIN_SDA2                    ( 0x0370 )
 666 #define REG_PIN_CLK_AUX0                ( 0x0374 )
 667 #define REG_PIN_IIS0DI                  ( 0x0378 )
 668 #define REG_PIN_IIS0DO                  ( 0x037c )
 669 #define REG_PIN_IIS0CLK                 ( 0x0380 )
 670 #define REG_PIN_IIS0LRCK                ( 0x0384 )
 671 #define REG_PIN_IIS0MCK                 ( 0x0388 )
 672 #define REG_PIN_IIS1DI                  ( 0x038c )
 673 #define REG_PIN_IIS1DO                  ( 0x0390 )
 674 #define REG_PIN_IIS1CLK                 ( 0x0394 )
 675 #define REG_PIN_IIS1LRCK                ( 0x0398 )
 676 #define REG_PIN_IIS1MCK                 ( 0x039c )
 677 #define REG_PIN_MTDO                    ( 0x03a0 )
 678 #define REG_PIN_MTDI                    ( 0x03a4 )
 679 #define REG_PIN_MTCK                    ( 0x03a8 )
 680 #define REG_PIN_MTMS                    ( 0x03ac )
 681 #define REG_PIN_MTRST_N                 ( 0x03b0 )
 682
 683 #else
 684 /* registers definitions for controller CTL_PIN */
 685 #define REG_PIN_CTRL0                   ( 0x0000 )
 686 #define REG_PIN_CTRL1                   ( 0x0004 )
 687 #define REG_PIN_CTRL2                   ( 0x0008 )
 688 #define REG_PIN_CTRL3                   ( 0x000c )
 689 #define REG_PIN_TRACECLK                ( 0x0010 )
 690 #define REG_PIN_TRACECTRL               ( 0x0014 )
 691 #define REG_PIN_TRACEDAT0               ( 0x0018 )
 692 #define REG_PIN_TRACEDAT1               ( 0x001c )
 693 #define REG_PIN_TRACEDAT2               ( 0x0020 )
 694 #define REG_PIN_TRACEDAT3               ( 0x0024 )
 695 #define REG_PIN_TRACEDAT4               ( 0x0028 )
 696 #define REG_PIN_TRACEDAT5               ( 0x002c )
 697 #define REG_PIN_TRACEDAT6               ( 0x0030 )
 698 #define REG_PIN_TRACEDAT7               ( 0x0034 )
 699 #define REG_PIN_U0TXD                   ( 0x0038 )
 700 #define REG_PIN_U0RXD                   ( 0x003c )
 701 #define REG_PIN_U0CTS                   ( 0x0040 )
 702 #define REG_PIN_U0RTS                   ( 0x0044 )
 703 #define REG_PIN_U1TXD                   ( 0x0048 )
 704 #define REG_PIN_U1RXD                   ( 0x004c )
 705 #define REG_PIN_U2TXD                   ( 0x0050 )
 706 #define REG_PIN_U2RXD                   ( 0x0054 )
 707 #define REG_PIN_U3TXD                   ( 0x0058 )
 708 #define REG_PIN_U3RXD                   ( 0x005c )
 709 #define REG_PIN_U3CTS                   ( 0x0060 )
 710 #define REG_PIN_U3RTS                   ( 0x0064 )
 711 #define REG_PIN_EXTINT2                 ( 0x0068 )
 712 #define REG_PIN_EXTINT3                 ( 0x006c )
 713 #define REG_PIN_RFSDA2                  ( 0x0070 )
 714 #define REG_PIN_RFSCK2                  ( 0x0074 )
 715 #define REG_PIN_RFSEN2                  ( 0x0078 )
 716 #define REG_PIN_CP2_RFCTL0              ( 0x007c )
 717 #define REG_PIN_CP2_RFCTL1              ( 0x0080 )
 718 #define REG_PIN_CP2_RFCTL2              ( 0x0084 )
 719 #define REG_PIN_FM_RXIQD0               ( 0x0088 )
 720 #define REG_PIN_FM_RXIQD1               ( 0x008c )
 721 #define REG_PIN_WIFI_AGCGAIN0           ( 0x0090 )
 722 #define REG_PIN_WIFI_AGCGAIN1           ( 0x0094 )
 723 #define REG_PIN_WIFI_AGCGAIN2           ( 0x0098 )
 724 #define REG_PIN_WIFI_AGCGAIN3           ( 0x009c )
 725 #define REG_PIN_WIFI_AGCGAIN4           ( 0x00a0 )
 726 #define REG_PIN_WIFI_AGCGAIN5           ( 0x00a4 )
 727 #define REG_PIN_WIFI_AGCGAIN6           ( 0x00a8 )
 728 #define REG_PIN_WBENA                   ( 0x00ac )
 729 #define REG_PIN_WBENB                   ( 0x00b0 )
 730 #define REG_PIN_GPSREAL                 ( 0x00b4 )
 731 #define REG_PIN_GPSIMAG                 ( 0x00b8 )
 732 #define REG_PIN_GPSCLK                  ( 0x00bc )
 733 #define REG_PIN_RFSDA0                  ( 0x00c0 )
 734 #define REG_PIN_RFSCK0                  ( 0x00c4 )
 735 #define REG_PIN_RFSEN0                  ( 0x00c8 )
 736 #define REG_PIN_RFSDA1                  ( 0x00cc )
 737 #define REG_PIN_RFSCK1                  ( 0x00d0 )
 738 #define REG_PIN_RFSEN1                  ( 0x00d4 )
 739 #define REG_PIN_CP1_RFCTL0              ( 0x00d8 )
 740 #define REG_PIN_CP1_RFCTL1              ( 0x00dc )
 741 #define REG_PIN_CP1_RFCTL2              ( 0x00e0 )
 742 #define REG_PIN_CP1_RFCTL3              ( 0x00e4 )
 743 #define REG_PIN_CP1_RFCTL4              ( 0x00e8 )
 744 #define REG_PIN_CP1_RFCTL5              ( 0x00ec )
 745 #define REG_PIN_CP1_RFCTL6              ( 0x00f0 )
 746 #define REG_PIN_CP1_RFCTL7              ( 0x00f4 )
 747 #define REG_PIN_CP1_RFCTL8              ( 0x00f8 )
 748 #define REG_PIN_CP1_RFCTL9              ( 0x00fc )
 749 #define REG_PIN_CP1_RFCTL10             ( 0x0100 )
 750 #define REG_PIN_CP1_RFCTL11             ( 0x0104 )
 751 #define REG_PIN_CP1_RFCTL12             ( 0x0108 )
 752 #define REG_PIN_CP1_RFCTL13             ( 0x010c )
 753 #define REG_PIN_CP1_RFCTL14             ( 0x0110 )
 754 #define REG_PIN_CP1_RFCTL15             ( 0x0114 )
 755 #define REG_PIN_CP0_RFCTL0              ( 0x0118 )
 756 #define REG_PIN_CP0_RFCTL1              ( 0x011c )
 757 #define REG_PIN_CP0_RFCTL2              ( 0x0120 )
 758 #define REG_PIN_CP0_RFCTL3              ( 0x0124 )
 759 #define REG_PIN_CP0_RFCTL4              ( 0x0128 )
 760 #define REG_PIN_CP0_RFCTL5              ( 0x012c )
 761 #define REG_PIN_CP0_RFCTL6              ( 0x0130 )
 762 #define REG_PIN_CP0_RFCTL7              ( 0x0134 )
 763 #define REG_PIN_XTLEN                   ( 0x0138 )
 764 #define REG_PIN_GPIO6                   ( 0x013c )
 765 #define REG_PIN_GPIO7                   ( 0x0140 )
 766 #define REG_PIN_GPIO8                   ( 0x0144 )
 767 #define REG_PIN_GPIO9                   ( 0x0148 )
 768 #define REG_PIN_U4TXD                   ( 0x014c )
 769 #define REG_PIN_U4RXD                   ( 0x0150 )
 770 #define REG_PIN_U4CTS                   ( 0x0154 )
 771 #define REG_PIN_U4RTS                   ( 0x0158 )
 772 #define REG_PIN_SCL3                    ( 0x015C )
 773 #define REG_PIN_SDA3                    ( 0x0160 )
 774 #define REG_PIN_SPI0_CSN                ( 0x0164 )
 775 #define REG_PIN_SPI0_DO                 ( 0x0168 )
 776 #define REG_PIN_SPI0_DI                 ( 0x016c )
 777 #define REG_PIN_SPI0_CLK                ( 0x0170 )
 778 #define REG_PIN_EXTINT0                 ( 0x0174 )
 779 #define REG_PIN_EXTINT1                 ( 0x0178 )
 780 #define REG_PIN_SCL1                    ( 0x017c )
 781 #define REG_PIN_SDA1                    ( 0x0180 )
 782 #define REG_PIN_GPIO0                   ( 0x0184 )
 783 #define REG_PIN_GPIO1                   ( 0x0188 )
 784 #define REG_PIN_GPIO2                   ( 0x018c )
 785 #define REG_PIN_GPIO3                   ( 0x0190 )
 786 #define REG_PIN_SIMCLK0                 ( 0x0194 )
 787 #define REG_PIN_SIMDA0                  ( 0x0198 )
 788 #define REG_PIN_SIMRST0                 ( 0x019c )
 789 #define REG_PIN_SIMCLK1                 ( 0x01a0 )
 790 #define REG_PIN_SIMDA1                  ( 0x01a4 )
 791 #define REG_PIN_SIMRST1                 ( 0x01a8 )
 792 #define REG_PIN_SIMCLK2                 ( 0x01ac )
 793 #define REG_PIN_SIMDA2                  ( 0x01b0 )
 794 #define REG_PIN_SIMRST2                 ( 0x01b4 )
 795 #define REG_PIN_MEMS_MIC_CLK0           ( 0x01b8 )
 796 #define REG_PIN_MEMS_MIC_DATA0          ( 0x01bc )
 797 #define REG_PIN_MEMS_MIC_CLK1           ( 0x01c0 )
 798 #define REG_PIN_MEMS_MIC_DATA1          ( 0x01c4 )
 799 #define REG_PIN_SD1_CLK                 ( 0x01c8 )
 800 #define REG_PIN_SD1_CMD                 ( 0x01cc )
 801 #define REG_PIN_SD1_D0                  ( 0x01d0 )
 802 #define REG_PIN_SD1_D1                  ( 0x01d4 )
 803 #define REG_PIN_SD1_D2                  ( 0x01d8 )
 804 #define REG_PIN_SD1_D3                  ( 0x01dc )
 805 #define REG_PIN_SD0_D3                  ( 0x01e0 )
 806 #define REG_PIN_SD0_D2                  ( 0x01e4 )
 807 #define REG_PIN_SD0_CMD                 ( 0x01e8 )
 808 #define REG_PIN_SD0_D0                  ( 0x01ec )
 809 #define REG_PIN_SD0_D1                  ( 0x01f0 )
 810 #define REG_PIN_SD0_CLK1                ( 0x01f4 )
 811 #define REG_PIN_SD0_CLK0                ( 0x01f8 )
 812 #define REG_PIN_PTEST                   ( 0x01fc )
 813 #define REG_PIN_ANA_INT                 ( 0x0200 )
 814 #define REG_PIN_EXT_RST_B               ( 0x0204 )
 815 #define REG_PIN_CHIP_SLEEP              ( 0x0208 )
 816 #define REG_PIN_XTL_BUF_EN0             ( 0x020C )
 817 #define REG_PIN_XTL_BUF_EN1             ( 0x0210 )
 818 #define REG_PIN_XTL_BUF_EN2             ( 0x0214 )
 819 #define REG_PIN_CLK_32K                 ( 0x0218 )
 820 #define REG_PIN_AUD_SCLK                ( 0x021c )
 821 #define REG_PIN_AUD_DANGL               ( 0x0220 )
 822 #define REG_PIN_AUD_DANGR               ( 0x0224 )
 823 #define REG_PIN_AUD_ADD0                ( 0x0228 )
 824 #define REG_PIN_AUD_ADSYNC              ( 0x022c )
 825 #define REG_PIN_AUD_DAD1                ( 0x0230 )
 826 #define REG_PIN_AUD_DAD0                ( 0x0234 )
 827 #define REG_PIN_AUD_DASYNC              ( 0x0238 )
 828 #define REG_PIN_ADI_D                   ( 0x023c )
 829 #define REG_PIN_ADI_SYNC                ( 0x0240 )
 830 #define REG_PIN_ADI_SCLK                ( 0x0244 )
 831 #define REG_PIN_LCD_CSN1                ( 0x0248 )
 832 #define REG_PIN_LCD_CSN0                ( 0x024c )
 833 #define REG_PIN_LCD_RSTN                ( 0x0250 )
 834 #define REG_PIN_LCD_WRN                 ( 0x025c )
 835 #define REG_PIN_LCD_RDN                 ( 0x0260 )
 836 #define REG_PIN_LCD_CD                  ( 0x0254 )
 837 #define REG_PIN_LCD_FMARK               ( 0x0258 )
 838 #define REG_PIN_LCD_D0                  ( 0x0264 )
 839 #define REG_PIN_LCD_D1                  ( 0x0268 )
 840 #define REG_PIN_LCD_D2                  ( 0x026c )
 841 #define REG_PIN_LCD_D3                  ( 0x0270 )
 842 #define REG_PIN_LCD_D4                  ( 0x0274 )
 843 #define REG_PIN_LCD_D5                  ( 0x0278 )
 844 #define REG_PIN_LCD_D6                  ( 0x027c )
 845 #define REG_PIN_LCD_D7                  ( 0x0280 )
 846 #define REG_PIN_LCD_D8                  ( 0x0284 )
 847 #define REG_PIN_LCD_D9                  ( 0x0288 )
 848 #define REG_PIN_LCD_D10                 ( 0x028c )
 849 #define REG_PIN_LCD_D11                 ( 0x0290 )
 850 #define REG_PIN_LCD_D12                 ( 0x0294 )
 851 #define REG_PIN_LCD_D13                 ( 0x0298 )
 852 #define REG_PIN_LCD_D14                 ( 0x029c )
 853 #define REG_PIN_LCD_D15                 ( 0x02a0 )
 854 #define REG_PIN_LCD_D16                 ( 0x02a4 )
 855 #define REG_PIN_LCD_D17                 ( 0x02a8 )
 856 #define REG_PIN_LCD_D18                 ( 0x02ac )
 857 #define REG_PIN_LCD_D19                 ( 0x02b0 )
 858 #define REG_PIN_LCD_D20                 ( 0x02b4 )
 859 #define REG_PIN_LCD_D21                 ( 0x02b8 )
 860 #define REG_PIN_LCD_D22                 ( 0x02bc )
 861 #define REG_PIN_LCD_D23                 ( 0x02c0 )
 862 #define REG_PIN_SPI2_CSN                ( 0x02c4 )
 863 #define REG_PIN_SPI2_DO                 ( 0x02c8 )
 864 #define REG_PIN_SPI2_DI                 ( 0x02cc )
 865 #define REG_PIN_SPI2_CLK                ( 0x02d0 )
 866 #define REG_PIN_EMMC_CLK                ( 0x02d4 )
 867 #define REG_PIN_EMMC_CMD                ( 0x02d8 )
 868 #define REG_PIN_EMMC_D0                 ( 0x02dc )
 869 #define REG_PIN_EMMC_D1                 ( 0x02e0 )
 870 #define REG_PIN_EMMC_D2                 ( 0x02e4 )
 871 #define REG_PIN_EMMC_D3                 ( 0x02e8 )
 872 #define REG_PIN_EMMC_D4                 ( 0x02ec )
 873 #define REG_PIN_EMMC_D5                 ( 0x02f0 )
 874 #define REG_PIN_EMMC_D6                 ( 0x02f4 )
 875 #define REG_PIN_EMMC_D7                 ( 0x02f8 )
 876 #define REG_PIN_EMMC_RST                ( 0x02fc )
 877 #define REG_PIN_NFWPN                   ( 0x0300 )
 878 #define REG_PIN_NFRB                    ( 0x0304 )
 879 #define REG_PIN_NFCLE                   ( 0x0308 )
 880 #define REG_PIN_NFALE                   ( 0x030c )
 881 #define REG_PIN_NFCEN0                  ( 0x0310 )
 882 #define REG_PIN_NFCEN1                  ( 0x0314 )
 883 #define REG_PIN_NFREN                   ( 0x0318 )
 884 #define REG_PIN_NFWEN                   ( 0x031c )
 885 #define REG_PIN_NFD0                    ( 0x0320 )
 886 #define REG_PIN_NFD1                    ( 0x0324 )
 887 #define REG_PIN_NFD2                    ( 0x0328 )
 888 #define REG_PIN_NFD3                    ( 0x032c )
 889 #define REG_PIN_NFD4                    ( 0x0330 )
 890 #define REG_PIN_NFD5                    ( 0x0334 )
 891 #define REG_PIN_NFD6                    ( 0x0338 )
 892 #define REG_PIN_NFD7                    ( 0x033c )
 893 #define REG_PIN_NFD8                    ( 0x0340 )
 894 #define REG_PIN_NFD9                    ( 0x0344 )
 895 #define REG_PIN_NFD10                   ( 0x0348 )
 896 #define REG_PIN_NFD11                   ( 0x034c )
 897 #define REG_PIN_NFD12                   ( 0x0350 )
 898 #define REG_PIN_NFD13                   ( 0x0354 )
 899 #define REG_PIN_NFD14                   ( 0x0358 )
 900 #define REG_PIN_NFD15                   ( 0x035c )
 901 #define REG_PIN_CCIRCK0                 ( 0x0360 )
 902 #define REG_PIN_CCIRCK1                 ( 0x0364 )
 903 #define REG_PIN_CCIRMCLK                ( 0x0368 )
 904 #define REG_PIN_CCIRHS                  ( 0x036c )
 905 #define REG_PIN_CCIRVS                  ( 0x0370 )
 906 #define REG_PIN_CCIRD0                  ( 0x0374 )
 907 #define REG_PIN_CCIRD1                  ( 0x0378 )
 908 #define REG_PIN_CCIRD2                  ( 0x037c )
 909 #define REG_PIN_CCIRD3                  ( 0x0380 )
 910 #define REG_PIN_CCIRD4                  ( 0x0384 )
 911 #define REG_PIN_CCIRD5                  ( 0x0388 )
 912 #define REG_PIN_CCIRD6                  ( 0x038c )
 913 #define REG_PIN_CCIRD7                  ( 0x0390 )
 914 #define REG_PIN_CCIRD8                  ( 0x0394 )
 915 #define REG_PIN_CCIRD9                  ( 0x0398 )
 916 #define REG_PIN_CCIRRST                 ( 0x039c )
 917 #define REG_PIN_CCIRPD1                 ( 0x03a0 )
 918 #define REG_PIN_CCIRPD0                 ( 0x03a4 )
 919 #define REG_PIN_SCL0                    ( 0x03a8 )
 920 #define REG_PIN_SDA0                    ( 0x03ac )
 921 #define REG_PIN_KEYOUT0                 ( 0x03b0 )
 922 #define REG_PIN_KEYOUT1                 ( 0x03b4 )
 923 #define REG_PIN_KEYOUT2                 ( 0x03b8 )
 924 #define REG_PIN_KEYOUT3                 ( 0x03bc )
 925 #define REG_PIN_KEYOUT4                 ( 0x03c0 )
 926 #define REG_PIN_KEYOUT5                 ( 0x03c4 )
 927 #define REG_PIN_KEYOUT6                 ( 0x03c8 )
 928 #define REG_PIN_KEYOUT7                 ( 0x03cc )
 929 #define REG_PIN_KEYIN0                  ( 0x03d0 )
 930 #define REG_PIN_KEYIN1                  ( 0x03d4 )
 931 #define REG_PIN_KEYIN2                  ( 0x03d8 )
 932 #define REG_PIN_KEYIN3                  ( 0x03dc )
 933 #define REG_PIN_KEYIN4                  ( 0x03e0 )
 934 #define REG_PIN_KEYIN5                  ( 0x03e4 )
 935 #define REG_PIN_KEYIN6                  ( 0x03e8 )
 936 #define REG_PIN_KEYIN7                  ( 0x03ec )
 937 #define REG_PIN_GPIO4                   ( 0x03f0 )
 938 #define REG_PIN_GPIO5                   ( 0x03f4 )
 939 #define REG_PIN_SCL2                    ( 0x03f8 )
 940 #define REG_PIN_SDA2                    ( 0x03fc )
 941 #define REG_PIN_CLK_AUX0                ( 0x0400 )
 942 #define REG_PIN_IIS0DI                  ( 0x0404 )
 943 #define REG_PIN_IIS0DO                  ( 0x0408 )
 944 #define REG_PIN_IIS0CLK                 ( 0x040c )
 945 #define REG_PIN_IIS0LRCK                ( 0x0410 )
 946 #define REG_PIN_IIS0MCK                 ( 0x0414 )
 947 #define REG_PIN_IIS1DI                  ( 0x0418 )
 948 #define REG_PIN_IIS1DO                  ( 0x041c )
 949 #define REG_PIN_IIS1CLK                 ( 0x0420 )
 950 #define REG_PIN_IIS1LRCK                ( 0x0424 )
 951 #define REG_PIN_IIS1MCK                 ( 0x0428 )
 952 #define REG_PIN_IIS2DI                  ( 0x042c )
 953 #define REG_PIN_IIS2DO                  ( 0x0430 )
 954 #define REG_PIN_IIS2CLK                 ( 0x0434 )
 955 #define REG_PIN_IIS2LRCK                ( 0x0438 )
 956 #define REG_PIN_IIS2MCK                 ( 0x043c )
 957 #define REG_PIN_MTDO                    ( 0x0440 )
 958 #define REG_PIN_MTDI                    ( 0x0444 )
 959 #define REG_PIN_MTCK                    ( 0x0448 )
 960 #define REG_PIN_MTMS                    ( 0x044c )
 961 #define REG_PIN_MTRST_N                 ( 0x0450 )
 962 #endif
 963
 964 #if defined(CONFIG_SPX30G)
 965 /* bits definitions for register REG_PIN_XXX */
 966 #define BITS_PIN_DS(_x_)                ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) )
 967 #define BIT_PIN_SLP_AP                  ( BIT_13 )
 968 #define BIT_PIN_SLP_CP0                 ( BIT_14 )
 969 #define BIT_PIN_SLP_CP1                 ( BIT_15 )
 970 #define BIT_PIN_SLP_CP2                 ( BIT_16 )
 971 #define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
 972 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
 973 #define BIT_PIN_WPU                     ( BIT_7 )
 974 #define BIT_PIN_WPD                     ( BIT_6 )
 975 #define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
 976 #define BIT_PIN_SLP_WPU                 ( BIT_3 )
 977 #define BIT_PIN_SLP_WPD                 ( BIT_2 )
 978 #define BIT_PIN_SLP_IE                  ( BIT_1 )
 979 #define BIT_PIN_SLP_OE                  ( BIT_0 )
 980
 981 /* vars definitions for controller CTL_PIN */
 982 #define BIT_PIN_NUL                     ( 0 )
 983 #define BIT_PIN_SLP_NUL                 ( 0 )
 984 #define BIT_PIN_SLP_Z                   ( 0 )
 985 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
 986 #define BIT_PIN_WPUS                    ( BIT_12 )
 987 #define BIT_PIN_NULL                    ( 0 )
 988
 989 #else
 990 /* bits definitions for register REG_PIN_XXX */
 991 #define BIT_PIN_SLP_AP                  ( BIT_13 )
 992 #define BIT_PIN_SLP_CP0                 ( BIT_14 )
 993 #define BIT_PIN_SLP_CP1                 ( BIT_15 )
 994 #define BIT_PIN_SLP_CP2                 ( BIT_16 )
 995 #define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
 996 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
 997 #define BITS_PIN_DS(_x_)                ( ((_x_) << 8) & (BIT_8|BIT_9|BIT_10) )
 998 #define BIT_PIN_WPU                     ( BIT_7 )
 999 #define BIT_PIN_WPD                     ( BIT_6 )
1000 #define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
1001 #define BIT_PIN_SLP_WPU                 ( BIT_3 )
1002 #define BIT_PIN_SLP_WPD                 ( BIT_2 )
1003 #define BIT_PIN_SLP_IE                  ( BIT_1 )
1004 #define BIT_PIN_SLP_OE                  ( BIT_0 )
1005
1006 /* vars definitions for controller CTL_PIN */
1007 #define BIT_PIN_NUL                     ( 0 )
1008 #define BIT_PIN_SLP_NUL                 ( 0 )
1009 #define BIT_PIN_SLP_Z                   ( 0 )
1010 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
1011 #define BIT_PIN_WPUS                    ( BIT_12 )
1012 #define BIT_PIN_NULL                    ( 0 )
1013 #endif
1014
1015 #if defined(CONFIG_SPX30G2)
1016 /*here is the pinmap info of adie such as 2723*/
1017 #define CTL_ANA_PIN_BASE                        (SPRD_ANA_PIN_PHYS)
1018 /* registers definitions for controller CTL_PIN */
1019 #define REG_PIN_ANA_EXT_XTL_EN0                 ( 0x04 )
1020 #define REG_PIN_ANA_PBINT                       ( 0x08 )
1021 #define REG_PIN_ANA_PBINT2                      ( 0x0C )
1022 #define REG_PIN_ANA_ADI_SCLK                    ( 0x10 )
1023 #define REG_PIN_ANA_ADI_SYNC                    ( 0x14 )
1024 #define REG_PIN_ANA_ADI_D                       ( 0x18 )
1025 #define REG_PIN_ANA_AUD_DASYNC                  ( 0x1C )
1026 #define REG_PIN_ANA_AUD_DAD0                    ( 0x20 )
1027 #define REG_PIN_ANA_AUD_DAD1                    ( 0x24 )
1028 #define REG_PIN_ANA_AUD_ADSYNC                  ( 0x28 )
1029 #define REG_PIN_ANA_AUD_ADD0                    ( 0x2C )
1030 #define REG_PIN_ANA_AUD_SCLK                    ( 0x30 )
1031 #define REG_PIN_ANA_CLK_32K                     ( 0x34 )
1032 #define REG_PIN_ANA_XTL_BUF_EN1                 ( 0x38 )
1033 #define REG_PIN_ANA_XTL_BUF_EN0                 ( 0x3C )
1034 #define REG_PIN_ANA_CHIP_SLEEP                  ( 0x40 )
1035 #define REG_PIN_ANA_EXT_RST_B                   ( 0x44 )
1036 #define REG_PIN_ANA_ANA_INT                     ( 0x48 )
1037 #define REG_PIN_ANA_PTEST                       ( 0x4C )
1038
1039 /* bits definitions for register REG_PIN_XXX */
1040 #define BITS_ANA_PIN_DS(_x_)                ( ((_x_) << 8) & (BIT_8|BIT_9) )
1041 #define BIT_ANA_PIN_WPU                     ( BIT_7 )
1042 #define BIT_ANA_PIN_WPD                     ( BIT_6 )
1043 #define BITS_ANA_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
1044 #define BIT_ANA_PIN_SLP_WPU                 ( BIT_3 )
1045 #define BIT_ANA_PIN_SLP_WPD                 ( BIT_2 )
1046 #define BIT_ANA_PIN_SLP_IE                  ( BIT_1 )
1047 #define BIT_ANA_PIN_SLP_OE                  ( BIT_0 )
1048 #endif
1049 #endif //_PINMAP_H_
1050