2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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11 //#ifndef __SCI_GLB_REGS_H__
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12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
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16 #ifndef __H_REGS_PMU_APB_HEADFILE_H__
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17 #define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
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19 #define REGS_PMU_APB
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21 /* registers definitions for PMU_APB */
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22 #define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)
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23 #define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)
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24 #define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)
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25 #define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)
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26 #define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)
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27 #define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)
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28 #define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)
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29 #define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)
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30 #define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)
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31 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)
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32 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)
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33 #define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)
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34 #define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)
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35 #define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)
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36 #define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)
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37 #define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)
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38 #define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)
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39 #define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)
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40 #define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)
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41 #define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)
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42 #define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)
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43 #define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)
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44 #define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)
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45 #define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)
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46 #define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)
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47 #define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)
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48 #define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)
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49 #define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)
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50 #define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)
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51 #define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)
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52 #define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)
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53 #define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)
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54 #define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)
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55 #define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)
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56 #define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)
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57 #define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)
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58 #define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)
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59 #define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)
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60 #define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)
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61 #define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)
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62 #define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)
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63 #define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)
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64 #define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)
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65 #define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)
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66 #define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)
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67 #define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)
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68 #define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)
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69 #define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)
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70 #define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)
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71 #define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)
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72 #define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)
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73 #define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)
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74 #define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)
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75 #define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)
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76 #define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)
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77 #define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)
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78 #define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)
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79 #define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)
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80 #define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)
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81 #define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)
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82 #define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)
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83 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)
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84 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)
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85 #define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)
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86 #define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)
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87 #define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)
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88 #define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)
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89 #define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)
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90 #define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)
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91 #define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)
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92 #define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)
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93 #define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)
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94 #define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)
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95 #define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)
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96 #define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)
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97 #define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)
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98 #define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)
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99 #define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)
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100 #define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)
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101 #define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)
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102 #define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)
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103 #define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)
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107 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
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108 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) )
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109 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) )
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110 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
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111 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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112 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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113 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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115 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
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116 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) )
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117 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) )
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118 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) )
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119 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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120 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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121 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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123 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
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124 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) )
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125 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) )
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126 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) )
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127 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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128 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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129 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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131 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
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132 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) )
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133 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) )
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134 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) )
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135 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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136 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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137 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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139 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
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140 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) )
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141 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) )
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142 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) )
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143 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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144 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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145 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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147 /* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
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149 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
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150 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) )
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151 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
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152 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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153 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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154 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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156 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
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157 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) )
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158 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
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159 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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160 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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161 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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163 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
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164 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) )
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165 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
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166 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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167 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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168 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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170 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
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171 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) )
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172 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) )
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173 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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174 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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175 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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177 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
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178 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) )
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179 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) )
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180 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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181 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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182 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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184 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
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185 #define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN ( BIT(25) )
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186 #define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN ( BIT(24) )
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187 #define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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188 #define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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189 #define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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191 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
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192 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) )
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193 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) )
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194 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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195 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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196 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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198 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
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199 #define BIT_PD_CP0_GSM_FORCE_SHUTDOWN ( BIT(25) )
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200 #define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
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201 #define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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202 #define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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203 #define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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205 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
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206 #define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) )
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207 #define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
208 #define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
209 #define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
210 #define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
212 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */
\r
213 #define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN ( BIT(25) )
\r
214 #define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
215 #define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
216 #define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
217 #define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
219 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
\r
220 #define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(28) )
\r
221 #define BIT_PD_CP0_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
222 #define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
223 #define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
224 #define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
226 /* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
\r
227 #define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN ( BIT(25) )
\r
228 #define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
229 #define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
230 #define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
231 #define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
233 /* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
\r
234 #define BIT_PD_CP1_GSM_FORCE_SHUTDOWN ( BIT(25) )
\r
235 #define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
236 #define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
237 #define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
238 #define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
240 /* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
\r
241 #define BIT_PD_CP1_TD_FORCE_SHUTDOWN ( BIT(25) )
\r
242 #define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
243 #define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
244 #define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
245 #define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
247 /* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
\r
248 #define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN ( BIT(25) )
\r
249 #define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
250 #define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
251 #define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
252 #define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
254 /* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
\r
255 #define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(28) )
\r
256 #define BIT_PD_CP1_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
257 #define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
258 #define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
259 #define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
261 /* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
\r
262 #define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN ( BIT(25) )
\r
263 #define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
264 #define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
265 #define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
266 #define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
268 /* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
\r
269 #define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN ( BIT(25) )
\r
270 #define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
271 #define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
272 #define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
273 #define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
275 /* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
\r
276 #define BIT_AP_WAKEUP_POR_N ( BIT(0) )
\r
278 /* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
\r
279 #define BIT_CP2_FORCE_DEEP_SLEEP ( BIT(28) )
\r
280 #define BIT_PD_CP2_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
281 #define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
282 #define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
283 #define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
285 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
\r
286 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) )
\r
287 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
288 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
289 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
290 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
292 /* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
\r
293 #define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
294 #define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
296 /* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
\r
297 #define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
298 #define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
300 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
\r
301 #define BITS_WPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
302 #define BITS_TDPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
303 #define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
304 #define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
306 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
\r
307 #define BITS_WIFIPLL2_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
308 #define BITS_WIFIPLL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
309 #define BITS_CPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
311 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
\r
312 #define BIT_XTL0_CP2_SEL ( BIT(3) )
\r
313 #define BIT_XTL0_CP1_SEL ( BIT(2) )
\r
314 #define BIT_XTL0_CP0_SEL ( BIT(1) )
\r
315 #define BIT_XTL0_AP_SEL ( BIT(0) )
\r
317 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
\r
318 #define BIT_XTL1_CP2_SEL ( BIT(3) )
\r
319 #define BIT_XTL1_CP1_SEL ( BIT(2) )
\r
320 #define BIT_XTL1_CP0_SEL ( BIT(1) )
\r
321 #define BIT_XTL1_AP_SEL ( BIT(0) )
\r
323 /* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
\r
324 #define BIT_XTL2_CP2_SEL ( BIT(3) )
\r
325 #define BIT_XTL2_CP1_SEL ( BIT(2) )
\r
326 #define BIT_XTL2_CP0_SEL ( BIT(1) )
\r
327 #define BIT_XTL2_AP_SEL ( BIT(0) )
\r
329 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
\r
330 #define BIT_XTLBUF0_CP2_SEL ( BIT(3) )
\r
331 #define BIT_XTLBUF0_CP1_SEL ( BIT(2) )
\r
332 #define BIT_XTLBUF0_CP0_SEL ( BIT(1) )
\r
333 #define BIT_XTLBUF0_AP_SEL ( BIT(0) )
\r
335 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
\r
336 #define BIT_XTLBUF1_CP2_SEL ( BIT(3) )
\r
337 #define BIT_XTLBUF1_CP1_SEL ( BIT(2) )
\r
338 #define BIT_XTLBUF1_CP0_SEL ( BIT(1) )
\r
339 #define BIT_XTLBUF1_AP_SEL ( BIT(0) )
\r
341 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
\r
342 #define BIT_MPLL_REF_SEL ( BIT(4) )
\r
343 #define BIT_MPLL_CP2_SEL ( BIT(3) )
\r
344 #define BIT_MPLL_CP1_SEL ( BIT(2) )
\r
345 #define BIT_MPLL_CP0_SEL ( BIT(1) )
\r
346 #define BIT_MPLL_AP_SEL ( BIT(0) )
\r
348 /* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
\r
349 #define BIT_DPLL_REF_SEL ( BIT(4) )
\r
350 #define BIT_DPLL_CP2_SEL ( BIT(3) )
\r
351 #define BIT_DPLL_CP1_SEL ( BIT(2) )
\r
352 #define BIT_DPLL_CP0_SEL ( BIT(1) )
\r
353 #define BIT_DPLL_AP_SEL ( BIT(0) )
\r
355 /* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
\r
356 #define BIT_TDPLL_REF_SEL ( BIT(4) )
\r
357 #define BIT_TDPLL_CP2_SEL ( BIT(3) )
\r
358 #define BIT_TDPLL_CP1_SEL ( BIT(2) )
\r
359 #define BIT_TDPLL_CP0_SEL ( BIT(1) )
\r
360 #define BIT_TDPLL_AP_SEL ( BIT(0) )
\r
362 /* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
\r
363 #define BIT_WPLL_REF_SEL ( BIT(4) )
\r
364 #define BIT_WPLL_CP2_SEL ( BIT(3) )
\r
365 #define BIT_WPLL_CP1_SEL ( BIT(2) )
\r
366 #define BIT_WPLL_CP0_SEL ( BIT(1) )
\r
367 #define BIT_WPLL_AP_SEL ( BIT(0) )
\r
369 /* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
\r
370 #define BIT_CPLL_REF_SEL ( BIT(4) )
\r
371 #define BIT_CPLL_CP2_SEL ( BIT(3) )
\r
372 #define BIT_CPLL_CP1_SEL ( BIT(2) )
\r
373 #define BIT_CPLL_CP0_SEL ( BIT(1) )
\r
374 #define BIT_CPLL_AP_SEL ( BIT(0) )
\r
376 /* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
\r
377 #define BIT_WIFIPLL1_REF_SEL ( BIT(4) )
\r
378 #define BIT_WIFIPLL1_CP2_SEL ( BIT(3) )
\r
379 #define BIT_WIFIPLL1_CP1_SEL ( BIT(2) )
\r
380 #define BIT_WIFIPLL1_CP0_SEL ( BIT(1) )
\r
381 #define BIT_WIFIPLL1_AP_SEL ( BIT(0) )
\r
383 /* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
\r
384 #define BIT_WIFIPLL2_REF_SEL ( BIT(4) )
\r
385 #define BIT_WIFIPLL2_CP2_SEL ( BIT(3) )
\r
386 #define BIT_WIFIPLL2_CP1_SEL ( BIT(2) )
\r
387 #define BIT_WIFIPLL2_CP0_SEL ( BIT(1) )
\r
388 #define BIT_WIFIPLL2_AP_SEL ( BIT(0) )
\r
390 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
\r
391 #define BIT_PUB_SOFT_RST ( BIT(6) )
\r
392 #define BIT_AP_SOFT_RST ( BIT(5) )
\r
393 #define BIT_GPU_SOFT_RST ( BIT(4) )
\r
394 #define BIT_MM_SOFT_RST ( BIT(3) )
\r
395 #define BIT_CP2_SOFT_RST ( BIT(2) )
\r
396 #define BIT_CP1_SOFT_RST ( BIT(1) )
\r
397 #define BIT_CP0_SOFT_RST ( BIT(0) )
\r
399 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
\r
400 #define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
401 #define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
403 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
\r
404 #define BITS_CP2_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
406 /* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
\r
407 #define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
408 #define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
409 #define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
410 #define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
411 #define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
412 #define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
413 #define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
415 /* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
\r
416 #define BITS_PD_CP0_SYS_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
417 #define BITS_PD_CP0_GSM_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
418 #define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
419 #define BITS_PD_CP0_ARM9_2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
420 #define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
421 #define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
422 #define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
424 /* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
\r
425 #define BITS_PD_CP2_WIFI_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
426 #define BITS_PD_CP2_ARM9_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
427 #define BITS_PD_CP1_SYS_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
428 #define BITS_PD_CP1_L1RAM_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
429 #define BITS_PD_CP1_TD_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
430 #define BITS_PD_CP1_GSM_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
431 #define BITS_PD_CP1_ARM9_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
433 /* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
\r
434 #define BITS_PD_CP0_CEVA_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
435 #define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
436 #define BITS_PD_DDR_PHY_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
437 #define BITS_PD_DDR_PUBL_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
438 #define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
439 #define BITS_PD_CP2_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
441 /* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
\r
442 #define BIT_CP0_FORCE_SLEEP ( BIT(12) )
\r
443 #define BIT_CP2_SLEEP_XTL_ON ( BIT(11) )
\r
444 #define BIT_CP1_SLEEP_XTL_ON ( BIT(10) )
\r
445 #define BIT_CP0_SLEEP_XTL_ON ( BIT(9) )
\r
446 #define BIT_AP_SLEEP_XTL_ON ( BIT(8) )
\r
447 #define BIT_DISP_DEEP_SLEEP ( BIT(6) )
\r
448 #define BIT_GPU_DEEP_SLEEP ( BIT(5) )
\r
449 #define BIT_MM_DEEP_SLEEP ( BIT(4) )
\r
450 #define BIT_CP2_DEEP_SLEEP ( BIT(3) )
\r
451 #define BIT_CP1_DEEP_SLEEP ( BIT(2) )
\r
452 #define BIT_CP0_DEEP_SLEEP ( BIT(1) )
\r
453 #define BIT_AP_DEEP_SLEEP ( BIT(0) )
\r
455 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
\r
456 #define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) )
\r
457 #define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) )
\r
458 #define BIT_DDR_PUBL_SOFT_RST ( BIT(10) )
\r
459 #define BIT_DDR_PHY_SOFT_RST ( BIT(8) )
\r
460 #define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) )
\r
461 #define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) )
\r
462 #define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) )
\r
463 #define BIT_DDR_PHY_EB ( BIT(2) )
\r
464 #define BIT_DDR_UMCTL_EB ( BIT(1) )
\r
465 #define BIT_DDR_PUBL_EB ( BIT(0) )
\r
467 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
\r
468 #define BITS_CP2_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
469 #define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
470 #define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
471 #define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
473 /* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
\r
474 #define BIT_WIFIPLL2_DIV_AUTO_GATE_EN ( BIT(6) )
\r
475 #define BIT_WIFIPLL1_DIV_AUTO_GATE_EN ( BIT(5) )
\r
476 #define BIT_WPLL_DIV_AUTO_GATE_EN ( BIT(4) )
\r
477 #define BIT_TDPLL_DIV_AUTO_GATE_EN ( BIT(3) )
\r
478 #define BIT_CPLL_DIV_AUTO_GATE_EN ( BIT(2) )
\r
479 #define BIT_DPLL_DIV_AUTO_GATE_EN ( BIT(1) )
\r
480 #define BIT_MPLL_DIV_AUTO_GATE_EN ( BIT(0) )
\r
482 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
\r
483 #define BIT_WIFIPLL2_80M_EN ( BIT(31) )
\r
484 #define BIT_WIFIPLL2_160M_EN ( BIT(30) )
\r
485 #define BIT_WIFIPLL2_120M_EN ( BIT(29) )
\r
486 #define BIT_WIFIPLL1_20M_EN ( BIT(28) )
\r
487 #define BIT_WIFIPLL1_40M_EN ( BIT(27) )
\r
488 #define BIT_WIFIPLL1_80M_EN ( BIT(26) )
\r
489 #define BIT_WIFIPLL1_44M_EN ( BIT(25) )
\r
490 #define BIT_WPLL_76M8_EN ( BIT(24) )
\r
491 #define BIT_WPLL_51M2_EN ( BIT(23) )
\r
492 #define BIT_WPLL_102M4_EN ( BIT(22) )
\r
493 #define BIT_WPLL_307M2_EN ( BIT(21) )
\r
494 #define BIT_WPLL_460M8_EN ( BIT(20) )
\r
495 #define BIT_CPLL_52M_EN ( BIT(19) )
\r
496 #define BIT_CPLL_104M_EN ( BIT(18) )
\r
497 #define BIT_CPLL_208M_EN ( BIT(17) )
\r
498 #define BIT_CPLL_312M_EN ( BIT(16) )
\r
499 #define BIT_TDPLL_38M4_EN ( BIT(15) )
\r
500 #define BIT_TDPLL_76M8_EN ( BIT(14) )
\r
501 #define BIT_TDPLL_51M2_EN ( BIT(13) )
\r
502 #define BIT_TDPLL_153M6_EN ( BIT(12) )
\r
503 #define BIT_TDPLL_64M_EN ( BIT(11) )
\r
504 #define BIT_TDPLL_128M_EN ( BIT(10) )
\r
505 #define BIT_TDPLL_256M_EN ( BIT(9) )
\r
506 #define BIT_TDPLL_12M_EN ( BIT(8) )
\r
507 #define BIT_TDPLL_24M_EN ( BIT(7) )
\r
508 #define BIT_TDPLL_48M_EN ( BIT(6) )
\r
509 #define BIT_TDPLL_96M_EN ( BIT(5) )
\r
510 #define BIT_TDPLL_192M_EN ( BIT(4) )
\r
511 #define BIT_TDPLL_384M_EN ( BIT(3) )
\r
512 #define BIT_DPLL_44M_EN ( BIT(2) )
\r
513 #define BIT_MPLL_37M5_EN ( BIT(1) )
\r
514 #define BIT_MPLL_300M_EN ( BIT(0) )
\r
516 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
\r
517 #define BIT_DPLL_533M_EN ( BIT(2) )
\r
518 #define BIT_WIFIPLL2_20M_EN ( BIT(1) )
\r
519 #define BIT_WIFIPLL2_40M_EN ( BIT(0) )
\r
521 /* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
\r
522 #define BIT_CA7_L2RSTDISABLE ( BIT(0) )
\r
524 /* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
\r
525 #define BIT_CA7_VINITHI_C0 ( BIT(0) )
\r
527 /* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
\r
528 #define BIT_CA7_VINITHI_C1 ( BIT(0) )
\r
530 /* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
\r
531 #define BIT_CA7_VINITHI_C2 ( BIT(0) )
\r
533 /* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
\r
534 #define BIT_CA7_VINITHI_C3 ( BIT(0) )
\r
536 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
\r
537 #define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) )
\r
538 #define BIT_DDR_CTRL_CGM_SEL ( BIT(30) )
\r
539 #define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) )
\r
540 #define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) )
\r
541 #define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) )
\r
542 #define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) )
\r
543 #define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) )
\r
544 #define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) )
\r
545 #define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) )
\r
546 #define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) )
\r
547 #define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) )
\r
548 #define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) )
\r
549 #define BIT_DDR_CHN9_CGM_SEL ( BIT(9) )
\r
550 #define BIT_DDR_CHN8_CGM_SEL ( BIT(8) )
\r
551 #define BIT_DDR_CHN7_CGM_SEL ( BIT(7) )
\r
552 #define BIT_DDR_CHN6_CGM_SEL ( BIT(6) )
\r
553 #define BIT_DDR_CHN5_CGM_SEL ( BIT(5) )
\r
554 #define BIT_DDR_CHN4_CGM_SEL ( BIT(4) )
\r
555 #define BIT_DDR_CHN3_CGM_SEL ( BIT(3) )
\r
556 #define BIT_DDR_CHN2_CGM_SEL ( BIT(2) )
\r
557 #define BIT_DDR_CHN1_CGM_SEL ( BIT(1) )
\r
558 #define BIT_DDR_CHN0_CGM_SEL ( BIT(0) )
\r
560 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
\r
561 #define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) )
\r
562 #define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) )
\r
563 #define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) )
\r
564 #define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) )
\r
565 #define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) )
\r
566 #define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) )
\r
567 #define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) )
\r
568 #define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) )
\r
569 #define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) )
\r
570 #define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) )
\r
572 /* bits definitions for register REG_PMU_APB_BISR_CFG */
\r
573 #define BIT_PD_CP0_CEVA_BISR_DONE ( BIT(31) )
\r
574 #define BIT_PD_CP0_TD_BISR_DONE ( BIT(30) )
\r
575 #define BIT_PD_CP1_TD_BISR_DONE ( BIT(29) )
\r
576 #define BIT_PD_CP1_SYS_BISR_DONE ( BIT(28) )
\r
577 #define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(27) )
\r
578 #define BIT_PD_CP0_SYS_BISR_DONE ( BIT(26) )
\r
579 #define BIT_PD_MM_TOP_BISR_DONE ( BIT(25) )
\r
580 #define BIT_PD_GPU_TOP_BISR_DONE ( BIT(24) )
\r
581 #define BIT_PD_CP0_CEVA_BISR_BUSY ( BIT(23) )
\r
582 #define BIT_PD_CP0_TD_BISR_BUSY ( BIT(22) )
\r
583 #define BIT_PD_CP1_TD_BISR_BUSY ( BIT(21) )
\r
584 #define BIT_PD_CP1_SYS_BISR_BUSY ( BIT(20) )
\r
585 #define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(19) )
\r
586 #define BIT_PD_CP0_SYS_BISR_BUSY ( BIT(18) )
\r
587 #define BIT_PD_MM_TOP_BISR_BUSY ( BIT(17) )
\r
588 #define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(16) )
\r
589 #define BIT_PD_CP0_CEVA_BISR_FORCE_EN ( BIT(15) )
\r
590 #define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) )
\r
591 #define BIT_PD_CP1_TD_BISR_FORCE_EN ( BIT(13) )
\r
592 #define BIT_PD_CP1_SYS_BISR_FORCE_EN ( BIT(12) )
\r
593 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(11) )
\r
594 #define BIT_PD_CP0_SYS_BISR_FORCE_EN ( BIT(10) )
\r
595 #define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(9) )
\r
596 #define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(8) )
\r
597 #define BIT_PD_CP1_TD_BISR_FORCE_BYP ( BIT(7) )
\r
598 #define BIT_PD_CP0_CEVA_BISR_FORCE_BYP ( BIT(6) )
\r
599 #define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(5) )
\r
600 #define BIT_PD_CP1_SYS_BISR_FORCE_BYP ( BIT(4) )
\r
601 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(3) )
\r
602 #define BIT_PD_CP0_SYS_BISR_FORCE_BYP ( BIT(2) )
\r
603 #define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(1) )
\r
604 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(0) )
\r
606 /* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
\r
607 #define BIT_CGM_208M_AP_AUTO_GATE_EN ( BIT(20) )
\r
608 #define BIT_CGM_12M_AP_AUTO_GATE_EN ( BIT(19) )
\r
609 #define BIT_CGM_24M_AP_AUTO_GATE_EN ( BIT(18) )
\r
610 #define BIT_CGM_48M_AP_AUTO_GATE_EN ( BIT(17) )
\r
611 #define BIT_CGM_51M2_AP_AUTO_GATE_EN ( BIT(16) )
\r
612 #define BIT_CGM_64M_AP_AUTO_GATE_EN ( BIT(15) )
\r
613 #define BIT_CGM_76M8_AP_AUTO_GATE_EN ( BIT(14) )
\r
614 #define BIT_CGM_96M_AP_AUTO_GATE_EN ( BIT(13) )
\r
615 #define BIT_CGM_128M_AP_AUTO_GATE_EN ( BIT(12) )
\r
616 #define BIT_CGM_153M6_AP_AUTO_GATE_EN ( BIT(11) )
\r
617 #define BIT_CGM_192M_AP_AUTO_GATE_EN ( BIT(10) )
\r
618 #define BIT_CGM_256M_AP_AUTO_GATE_EN ( BIT(9) )
\r
619 #define BIT_CGM_384M_AP_AUTO_GATE_EN ( BIT(8) )
\r
620 #define BIT_CGM_312M_AP_AUTO_GATE_EN ( BIT(7) )
\r
621 #define BIT_CGM_MPLL_AP_AUTO_GATE_EN ( BIT(6) )
\r
622 #define BIT_CGM_WPLL_AP_AUTO_GATE_EN ( BIT(5) )
\r
623 #define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN ( BIT(4) )
\r
624 #define BIT_CGM_TDPLL_AP_AUTO_GATE_EN ( BIT(3) )
\r
625 #define BIT_CGM_CPLL_AP_AUTO_GATE_EN ( BIT(2) )
\r
626 #define BIT_CGM_DPLL_AP_AUTO_GATE_EN ( BIT(1) )
\r
627 #define BIT_CGM_26M_AP_AUTO_GATE_EN ( BIT(0) )
\r
629 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
\r
630 #define BIT_CGM_312M_MM_AUTO_GATE_EN ( BIT(27) )
\r
631 #define BIT_CGM_12M_MM_AUTO_GATE_EN ( BIT(26) )
\r
632 #define BIT_CGM_24M_MM_AUTO_GATE_EN ( BIT(25) )
\r
633 #define BIT_CGM_48M_MM_AUTO_GATE_EN ( BIT(24) )
\r
634 #define BIT_CGM_64M_MM_AUTO_GATE_EN ( BIT(23) )
\r
635 #define BIT_CGM_76M8_MM_AUTO_GATE_EN ( BIT(22) )
\r
636 #define BIT_CGM_96M_MM_AUTO_GATE_EN ( BIT(21) )
\r
637 #define BIT_CGM_128M_MM_AUTO_GATE_EN ( BIT(20) )
\r
638 #define BIT_CGM_153M6_MM_AUTO_GATE_EN ( BIT(19) )
\r
639 #define BIT_CGM_192M_MM_AUTO_GATE_EN ( BIT(18) )
\r
640 #define BIT_CGM_256M_MM_AUTO_GATE_EN ( BIT(17) )
\r
641 #define BIT_CGM_26M_MM_AUTO_GATE_EN ( BIT(16) )
\r
642 #define BIT_CGM_153_6M_GPU_AUTO_GATE_EN ( BIT(6) )
\r
643 #define BIT_CGM_384M_GPU_AUTO_GATE_EN ( BIT(5) )
\r
644 #define BIT_CGM_460_8M_GPU_AUTO_GATE_EN ( BIT(4) )
\r
645 #define BIT_CGM_256M_GPU_AUTO_GATE_EN ( BIT(3) )
\r
646 #define BIT_CGM_208M_GPU_AUTO_GATE_EN ( BIT(2) )
\r
647 #define BIT_CGM_312M_GPU_AUTO_GATE_EN ( BIT(1) )
\r
648 #define BIT_CGM_300M_GPU_AUTO_GATE_EN ( BIT(0) )
\r
650 /* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
\r
651 #define BIT_CGM_312M_CP0_AUTO_GATE_EN ( BIT(16) )
\r
652 #define BIT_CGM_208M_CP0_AUTO_GATE_EN ( BIT(15) )
\r
653 #define BIT_CGM_256M_CP0_AUTO_GATE_EN ( BIT(14) )
\r
654 #define BIT_CGM_460M8_CP0W_AUTO_GATE_EN ( BIT(13) )
\r
655 #define BIT_CGM_307M2_CP0W_AUTO_GATE_EN ( BIT(12) )
\r
656 #define BIT_CGM_51M2_CP0W_AUTO_GATE_EN ( BIT(11) )
\r
657 #define BIT_CGM_76M8_CP0W_AUTO_GATE_EN ( BIT(10) )
\r
658 #define BIT_CGM_102M4_CP0W_AUTO_GATE_EN ( BIT(9) )
\r
659 #define BIT_CGM_192M_CP0_AUTO_GATE_EN ( BIT(8) )
\r
660 #define BIT_CGM_51M2_CP0_AUTO_GATE_EN ( BIT(7) )
\r
661 #define BIT_CGM_76M8_CP0_AUTO_GATE_EN ( BIT(6) )
\r
662 #define BIT_CGM_153M6_CP0_AUTO_GATE_EN ( BIT(5) )
\r
663 #define BIT_CGM_48M_CP0_AUTO_GATE_EN ( BIT(4) )
\r
664 #define BIT_CGM_64M_CP0_AUTO_GATE_EN ( BIT(3) )
\r
665 #define BIT_CGM_96M_CP0_AUTO_GATE_EN ( BIT(2) )
\r
666 #define BIT_CGM_128M_CP0_AUTO_GATE_EN ( BIT(1) )
\r
667 #define BIT_CGM_26M_CP0_AUTO_GATE_EN ( BIT(0) )
\r
669 /* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
\r
670 #define BIT_CGM_312M_CP1_AUTO_GATE_EN ( BIT(10) )
\r
671 #define BIT_CGM_256M_CP1_AUTO_GATE_EN ( BIT(9) )
\r
672 #define BIT_CGM_192M_CP1_AUTO_GATE_EN ( BIT(8) )
\r
673 #define BIT_CGM_51M2_CP1_AUTO_GATE_EN ( BIT(7) )
\r
674 #define BIT_CGM_76M8_CP1_AUTO_GATE_EN ( BIT(6) )
\r
675 #define BIT_CGM_153M6_CP1_AUTO_GATE_EN ( BIT(5) )
\r
676 #define BIT_CGM_48M_CP1_AUTO_GATE_EN ( BIT(4) )
\r
677 #define BIT_CGM_96M_CP1_AUTO_GATE_EN ( BIT(3) )
\r
678 #define BIT_CGM_64M_CP1_AUTO_GATE_EN ( BIT(2) )
\r
679 #define BIT_CGM_128M_CP1_AUTO_GATE_EN ( BIT(1) )
\r
680 #define BIT_CGM_26M_CP1_AUTO_GATE_EN ( BIT(0) )
\r
682 /* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
\r
683 #define BIT_CGM_153M6_CP2_AUTO_GATE_EN ( BIT(12) )
\r
684 #define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN ( BIT(11) )
\r
685 #define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN ( BIT(10) )
\r
686 #define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN ( BIT(9) )
\r
687 #define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN ( BIT(8) )
\r
688 #define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN ( BIT(7) )
\r
689 #define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN ( BIT(6) )
\r
690 #define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN ( BIT(5) )
\r
691 #define BIT_CGM_256M_CP2_AUTO_GATE_EN ( BIT(4) )
\r
692 #define BIT_CGM_104M_CP2_AUTO_GATE_EN ( BIT(3) )
\r
693 #define BIT_CGM_208M_CP2_AUTO_GATE_EN ( BIT(2) )
\r
694 #define BIT_CGM_312M_CP2_AUTO_GATE_EN ( BIT(1) )
\r
695 #define BIT_CGM_26M_CP2_AUTO_GATE_EN ( BIT(0) )
\r
697 /* bits definitions for register REG_PMU_APB_CGM_AP_EN */
\r
698 #define BIT_CGM_208M_AP_EN ( BIT(20) )
\r
699 #define BIT_CGM_12M_AP_EN ( BIT(19) )
\r
700 #define BIT_CGM_24M_AP_EN ( BIT(18) )
\r
701 #define BIT_CGM_48M_AP_EN ( BIT(17) )
\r
702 #define BIT_CGM_51M2_AP_EN ( BIT(16) )
\r
703 #define BIT_CGM_64M_AP_EN ( BIT(15) )
\r
704 #define BIT_CGM_76M8_AP_EN ( BIT(14) )
\r
705 #define BIT_CGM_96M_AP_EN ( BIT(13) )
\r
706 #define BIT_CGM_128M_AP_EN ( BIT(12) )
\r
707 #define BIT_CGM_153M6_AP_EN ( BIT(11) )
\r
708 #define BIT_CGM_192M_AP_EN ( BIT(10) )
\r
709 #define BIT_CGM_256M_AP_EN ( BIT(9) )
\r
710 #define BIT_CGM_384M_AP_EN ( BIT(8) )
\r
711 #define BIT_CGM_312M_AP_EN ( BIT(7) )
\r
712 #define BIT_CGM_MPLL_AP_EN ( BIT(6) )
\r
713 #define BIT_CGM_WPLL_AP_EN ( BIT(5) )
\r
714 #define BIT_CGM_WIFIPLL1_AP_EN ( BIT(4) )
\r
715 #define BIT_CGM_TDPLL_AP_EN ( BIT(3) )
\r
716 #define BIT_CGM_CPLL_AP_EN ( BIT(2) )
\r
717 #define BIT_CGM_DPLL_AP_EN ( BIT(1) )
\r
718 #define BIT_CGM_26M_AP_EN ( BIT(0) )
\r
720 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
\r
721 #define BIT_CGM_312M_MM_EN ( BIT(27) )
\r
722 #define BIT_CGM_12M_MM_EN ( BIT(26) )
\r
723 #define BIT_CGM_24M_MM_EN ( BIT(25) )
\r
724 #define BIT_CGM_48M_MM_EN ( BIT(24) )
\r
725 #define BIT_CGM_64M_MM_EN ( BIT(23) )
\r
726 #define BIT_CGM_76M8_MM_EN ( BIT(22) )
\r
727 #define BIT_CGM_96M_MM_EN ( BIT(21) )
\r
728 #define BIT_CGM_128M_MM_EN ( BIT(20) )
\r
729 #define BIT_CGM_153M6_MM_EN ( BIT(19) )
\r
730 #define BIT_CGM_192M_MM_EN ( BIT(18) )
\r
731 #define BIT_CGM_256M_MM_EN ( BIT(17) )
\r
732 #define BIT_CGM_26M_MM_EN ( BIT(16) )
\r
733 #define BIT_CGM_153_6M_GPU_EN ( BIT(6) )
\r
734 #define BIT_CGM_384M_GPU_EN ( BIT(5) )
\r
735 #define BIT_CGM_460_8M_GPU_EN ( BIT(4) )
\r
736 #define BIT_CGM_256M_GPU_EN ( BIT(3) )
\r
737 #define BIT_CGM_208M_GPU_EN ( BIT(2) )
\r
738 #define BIT_CGM_312M_GPU_EN ( BIT(1) )
\r
739 #define BIT_CGM_300M_GPU_EN ( BIT(0) )
\r
741 /* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
\r
742 #define BIT_CGM_312M_CP0_EN ( BIT(16) )
\r
743 #define BIT_CGM_208M_CP0_EN ( BIT(15) )
\r
744 #define BIT_CGM_256M_CP0_EN ( BIT(14) )
\r
745 #define BIT_CGM_460M8_CP0W_EN ( BIT(13) )
\r
746 #define BIT_CGM_307M2_CP0W_EN ( BIT(12) )
\r
747 #define BIT_CGM_51M2_CP0W_EN ( BIT(11) )
\r
748 #define BIT_CGM_76M8_CP0W_EN ( BIT(10) )
\r
749 #define BIT_CGM_102M4_CP0W_EN ( BIT(9) )
\r
750 #define BIT_CGM_192M_CP0_EN ( BIT(8) )
\r
751 #define BIT_CGM_51M2_CP0_EN ( BIT(7) )
\r
752 #define BIT_CGM_76M8_CP0_EN ( BIT(6) )
\r
753 #define BIT_CGM_153M6_CP0_EN ( BIT(5) )
\r
754 #define BIT_CGM_48M_CP0_EN ( BIT(4) )
\r
755 #define BIT_CGM_64M_CP0_EN ( BIT(3) )
\r
756 #define BIT_CGM_96M_CP0_EN ( BIT(2) )
\r
757 #define BIT_CGM_128M_CP0_EN ( BIT(1) )
\r
758 #define BIT_CGM_26M_CP0_EN ( BIT(0) )
\r
760 /* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
\r
761 #define BIT_CGM_312M_CP1_EN ( BIT(10) )
\r
762 #define BIT_CGM_256M_CP1_EN ( BIT(9) )
\r
763 #define BIT_CGM_192M_CP1_EN ( BIT(8) )
\r
764 #define BIT_CGM_51M2_CP1_EN ( BIT(7) )
\r
765 #define BIT_CGM_76M8_CP1_EN ( BIT(6) )
\r
766 #define BIT_CGM_153M6_CP1_EN ( BIT(5) )
\r
767 #define BIT_CGM_48M_CP1_EN ( BIT(4) )
\r
768 #define BIT_CGM_96M_CP1_EN ( BIT(3) )
\r
769 #define BIT_CGM_64M_CP1_EN ( BIT(2) )
\r
770 #define BIT_CGM_128M_CP1_EN ( BIT(1) )
\r
771 #define BIT_CGM_26M_CP1_EN ( BIT(0) )
\r
773 /* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
\r
774 #define BIT_CGM_153M6_CP2_EN ( BIT(12) )
\r
775 #define BIT_CGM_20M_CP2WF2_EN ( BIT(11) )
\r
776 #define BIT_CGM_80M_CP2WF2_EN ( BIT(10) )
\r
777 #define BIT_CGM_120M_CP2WF2_EN ( BIT(9) )
\r
778 #define BIT_CGM_160M_CP2WF2_EN ( BIT(8) )
\r
779 #define BIT_CGM_20M_CP2WF1_EN ( BIT(7) )
\r
780 #define BIT_CGM_44M_CP2WF1_EN ( BIT(6) )
\r
781 #define BIT_CGM_80M_CP2WF1_EN ( BIT(5) )
\r
782 #define BIT_CGM_256M_CP2_EN ( BIT(4) )
\r
783 #define BIT_CGM_104M_CP2_EN ( BIT(3) )
\r
784 #define BIT_CGM_208M_CP2_EN ( BIT(2) )
\r
785 #define BIT_CGM_312M_CP2_EN ( BIT(1) )
\r
786 #define BIT_CGM_26M_CP2_EN ( BIT(0) )
\r
788 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
\r
789 #define BIT_DDR_PHY_RET_EN ( BIT(28) )
\r
790 #define BIT_DDR_PUBL_RET_EN ( BIT(27) )
\r
791 #define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) )
\r
792 #define BIT_DDR_UMCTL_RET_EN ( BIT(25) )
\r
793 #define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) )
\r
794 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
795 #define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
\r
796 #define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
\r
798 /* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
\r
799 #define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) )
\r
800 #define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) )
\r
802 /* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
\r
803 #define BIT_AON_MEM_PD_EN_CP2 ( BIT(9) )
\r
804 #define BIT_AON_MEM_PD_EN_CP0 ( BIT(8) )
\r
805 #define BIT_AON_MEM_PD_EN_AP ( BIT(7) )
\r
806 #define BIT_LPLL_REF_SEL ( BIT(6) )
\r
807 #define BIT_PUB_26M_SEL ( BIT(5) )
\r
808 #define BIT_AON_26M_SEL ( BIT(4) )
\r
809 #define BIT_CP2_26M_SEL ( BIT(3) )
\r
810 #define BIT_CP1_26M_SEL ( BIT(2) )
\r
811 #define BIT_CP0_26M_SEL ( BIT(1) )
\r
812 #define BIT_AP_26M_SEL ( BIT(0) )
\r
814 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */
\r
815 #define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
\r
816 #define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
\r
817 #define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
818 #define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
819 #define BITS_AON_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
\r
820 #define BITS_AON_MEM_PD_CFG_IMC3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
\r
821 #define BITS_AON_MEM_PD_CFG_IMC2(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
822 #define BITS_AON_MEM_PD_CFG_IMC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
823 #define BITS_AON_MEM_PD_CFG_IMC0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
\r
824 #define BITS_AON_MEM_PD_CFG_VBC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
\r
825 #define BITS_AON_MEM_PD_CFG_AUD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
826 #define BITS_AON_MEM_PD_CFG_FM(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
\r
828 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */
\r
829 #define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
830 #define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
\r
831 #define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
\r
832 #define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
833 #define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
834 #define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
\r
835 #define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
\r
836 #define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
837 #define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
838 #define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
\r
839 #define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
\r
840 #define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
841 #define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
\r
843 /* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */
\r
844 #define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN ( BIT(25) )
\r
845 #define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
846 #define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
847 #define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
848 #define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
850 /* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */
\r
851 #define BIT_PD_DDR_PHY_FORCE_SHUTDOWN ( BIT(25) )
\r
852 #define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN ( BIT(24) )
\r
853 #define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
854 #define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
855 #define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
857 /* bits definitions for register REG_PMU_APB_BISR_CFG2 */
\r
858 #define BIT_PD_CP2_WIFI_BISR_DONE ( BIT(7) )
\r
859 #define BIT_PD_AP_SYS_BISR_DONE ( BIT(6) )
\r
860 #define BIT_PD_CP2_WIFI_BISR_BUSY ( BIT(5) )
\r
861 #define BIT_PD_AP_SYS_BISR_BUSY ( BIT(4) )
\r
862 #define BIT_PD_CP2_WIFI_BISR_FORCE_EN ( BIT(3) )
\r
863 #define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(2) )
\r
864 #define BIT_PD_CP2_WIFI_BISR_FORCE_BYP ( BIT(1) )
\r
865 #define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(0) )
\r
projects / kernel / u-boot-tm1.git / blob