arch/arm/include/asm/arch-sc8830/chip_x30g/__regs_mm_ahb_rf_tshark2.h

   1 /*
   2  * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  */
  10
  11 //#ifndef __SCI_GLB_REGS_H__
  12 //#error  "Don't include this file directly, Pls include sci_glb_regs.h"
  13 //#endif
  14
  15
  16 #ifndef __H_REGS_MM_AHB_HEADFILE_H__
  17 #define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__
  18
  19 #define  REGS_MM_AHB
  20
  21 /* registers definitions for MM_AHB */
  22 #define REG_MM_AHB_AHB_EB                               SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/
  23 #define REG_MM_AHB_AHB_RST                              SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/
  24 #define REG_MM_AHB_GEN_CKG_CFG                          SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/
  25 #define REG_MM_AHB_MIPI_CSI2_CTRL                       SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/
  26 #define REG_MM_AHB_MM_QOS_CFG                           SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG*/
  27 #define REG_MM_AHB_MM_QOS_CFG_1                         SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG_1*/
  28
  29
  30
  31 /* bits definitions for register REG_MM_AHB_AHB_EB */
  32 #define BIT_VPP_EB                                              (BIT(8))
  33 #define BIT_MMU_EB                                              (BIT(7))
  34 #define BIT_MM_CKG_EB                                        (BIT(6))
  35 #define BIT_JPG_EB                                              (BIT(5))
  36 #define BIT_CSI_EB                                              (BIT(4))
  37 #define BIT_VSP_EB                                              (BIT(3))
  38 #define BIT_ISP_EB                                              (BIT(2))
  39 #define BIT_CCIR_EB                                             (BIT(1))
  40 #define BIT_DCAM_EB                                             (BIT(0))
  41
  42 /* bits definitions for register REG_MM_AHB_AHB_RST */
  43 #define BIT_VPP_SOFT_RST                                        (BIT(15))
  44 #define BIT_MMU_SOFT_RST                                        (BIT(14))
  45 #define BIT_MM_CKG_SOFT_RST                                  (BIT(13))
  46 #define BIT_MM_MTX_SOFT_RST                                     (BIT(12))
  47 #define BIT_OR1200_SOFT_RST                                     (BIT(11))
  48 #define BIT_ROT_SOFT_RST                                        (BIT(10))
  49 #define BIT_CAM2_SOFT_RST                                       (BIT(9))
  50 #define BIT_CAM1_SOFT_RST                                       (BIT(8))
  51 #define BIT_CAM0_SOFT_RST                                       (BIT(7))
  52 #define BIT_JPG_SOFT_RST                                        (BIT(6))
  53 #define BIT_CSI_SOFT_RST                                        (BIT(5))
  54 #define BIT_VSP_SOFT_RST                                        (BIT(4))
  55 #define BIT_ISP_CFG_SOFT_RST                                    (BIT(3))
  56 #define BIT_ISP_LOG_SOFT_RST                                    (BIT(2))
  57 #define BIT_CCIR_SOFT_RST                                       (BIT(1))
  58 #define BIT_DCAM_SOFT_RST                                       (BIT(0))
  59
  60 /* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */
  61 #define BIT_VPP_AXI_CKG_EN                                      (BIT(9))
  62 #define BIT_MM_MTX_AXI_CKG_EN                                   (BIT(8))
  63 #define BIT_MM_AXI_CKG_EN                                       (BIT(7))
  64 #define BIT_JPG_AXI_CKG_EN                                      (BIT(6))
  65 #define BIT_VSP_AXI_CKG_EN                                      (BIT(5))
  66 #define BIT_ISP_AXI_CKG_EN                                      (BIT(4))
  67 #define BIT_DCAM_AXI_CKG_EN                                     (BIT(3))
  68 #define BIT_SENSOR_CKG_EN                                       (BIT(2))
  69 #define BIT_MIPI_CSI_CKG_EN                                     (BIT(1))
  70 #define BIT_CPHY_CFG_CKG_EN                                     (BIT(0))
  71
  72 /* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */
  73 #define BIT_MIPI_CPHY_SEL_AB_C                                  (BIT(5))
  74 #define BITS_MIPI_CPHY_SAMPLE_SEL(_X_)                          ((_X_) << 3 & (BIT(3)|BIT(4)))
  75 #define BIT_MIPI_CPHY_SYNC_MODE                                 (BIT(2))
  76 #define BIT_MIPI_CPHY_TEST_CTL                                  (BIT(1))
  77 #define BIT_MIPI_CPHY_SEL                                       (BIT(0))
  78
  79 /* bits definitions for register REG_MM_AHB_MM_QOS_CFG */
  80 #define BITS_QOS_R_DCAM(_X_)                                    ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
  81 #define BITS_QOS_W_DCAM(_X_)                                    ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
  82 #define BITS_QOS_R_JPG(_X_)                                     ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
  83 #define BITS_QOS_W_JPG(_X_)                                     ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
  84 #define BITS_QOS_R_ISP(_X_)                                     ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
  85 #define BITS_QOS_W_ISP(_X_)                                     ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
  86 #define BITS_QOS_R_VSP(_X_)                                     ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
  87 #define BITS_QOS_W_VSP(_X_)                                     ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
  88
  89 /* bits definitions for register REG_MM_AHB_MM_QOS_CFG_1 */
  90 #define BITS_QOS_R_VPP(_X_)                                     ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
  91 #define BITS_QOS_W_VPP(_X_)                                     ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
  92 #define BITS_QOS_R_CODEC(_X_)                                   ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
  93 #define BITS_QOS_W_CODEC(_X_)                                   ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
  94
  95 #endif