2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
15 #ifndef __H_REGS_PMU_APB_HEADFILE_H__
16 #define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
20 /* registers definitions for PMU_APB */
21 #define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000) /*PD_CA7_TOP_CFG */
22 #define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004) /*PD_CA7_C0_CFG */
23 #define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008) /*PD_CA7_C1_CFG */
24 #define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C) /*PD_CA7_C2_CFG */
25 #define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010) /*PD_CA7_C3_CFG */
26 #define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014) /*PD_AP_DISP_CFG */
27 #define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018) /*PD_AP_SYS_CFG */
28 #define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C) /*PD_MM_TOP_CFG */
29 #define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020) /*PD_GPU_TOP_CFG */
30 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024) /*PD_CP0_ARM9_0_CFG */
31 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028) /*PD_CP0_ARM9_1_CFG */
32 #define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C) /*PD_CP0_ARM9_2_CFG */
33 #define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030) /*PD_CP0_HU3GE_CFG */
34 #define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034) /*PD_CP0_GSM_CFG */
35 #define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038) /*PD_CP0_TD_CFG */
36 #define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C) /*PD_CP0_CEVA_CFG */
37 #define REG_PMU_APB_PD_CP0_HARQ_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040) /*PD_CP0_HARQ_CFG */
38 #define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044) /*PD_CP0_SYS_CFG */
39 #define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048) /*PD_CP1_ARM9_CFG */
40 #define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C) /*PD_CP1_GSM_CFG */
41 #define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050) /*PD_CP1_TD_CFG */
42 #define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054) /*PD_CP1_L1RAM_CFG */
43 #define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058) /*PD_CP1_SYS_CFG */
44 #define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C) /*PD_CP2_ARM9_CFG */
45 #define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060) /*PD_CP2_WIFI_CFG */
46 #define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064) /*AP_WAKEUP_POR_CFG */
47 #define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068) /*PD_CP2_SYS_CFG */
48 #define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C) /*PD_PUB_SYS_CFG */
49 #define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070) /*XTL_WAIT_CNT */
50 #define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074) /*XTLBUF_WAIT_CNT */
51 #define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078) /*PLL_WAIT_CNT1 */
52 #define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C) /*PLL_WAIT_CNT2 */
53 #define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080) /*XTL0_REL_CFG */
54 #define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084) /*XTL1_REL_CFG */
55 #define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088) /*XTL1_REL_CFG */
56 #define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C) /*XTLBUF0_REL_CFG */
57 #define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090) /*XTLBUF1_REL_CFG */
58 #define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094) /*MPLL_REL_CFG */
59 #define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098) /*DPLL_REL_CFG */
60 #define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C) /*TDPLL_REL_CFG */
61 #define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0) /*WPLL_REL_CFG */
62 #define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4) /*CPLL_REL_CFG */
63 #define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8) /*WIFIPLL1_REL_CFG */
64 #define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC) /*WIFIPLL2_REL_CFG */
65 #define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0) /*CP_SOFT_RST */
66 #define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4) /*CP_SLP_STATUS_DBG0 */
67 #define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8) /*CP_SLP_STATUS_DBG1 */
68 #define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC) /*PWR_STATUS0_DBG */
69 #define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0) /*PWR_STATUS1_DBG */
70 #define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4) /*PWR_STATUS2_DBG */
71 #define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8) /*PWR_STATUS3_DBG */
72 #define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC) /*SLEEP_CTRL */
73 #define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0) /*DDR_SLEEP_CTRL */
74 #define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4) /*SLEEP_STATUS */
75 #define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8) /*PLL_DIV_AUTO_GATE_EN */
76 #define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC) /*PLL_DIV_EN1 */
77 #define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0) /*PLL_DIV_EN2 */
78 #define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4) /*CA7_TOP_CFG */
79 #define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8) /*CA7_C0_CFG */
80 #define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC) /*CA7_C1_CFG */
81 #define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0) /*CA7_C2_CFG */
82 #define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4) /*CA7_C3_CFG */
83 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8) /*DDR_CHN_SLEEP_CTRL0 */
84 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC) /*DDR_CHN_SLEEP_CTRL1 */
85 #define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100) /*BISR_CFG */
86 #define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104) /*CGM_AP_AUTO_GATE_EN */
87 #define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108) /*CGM_GPU_MM_AUTO_GATE_EN */
88 #define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C) /*CGM_CP0_AUTO_GATE_EN */
89 #define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110) /*CGM_CP1_AUTO_GATE_EN */
90 #define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114) /*CGM_CP2_AUTO_GATE_EN */
91 #define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118) /*CGM_AP_EN */
92 #define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C) /*CGM_GPU_MM_EN */
93 #define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120) /*CGM_CP0_EN */
94 #define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124) /*CGM_CP1_EN */
95 #define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128) /*CGM_CP2_EN */
96 #define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C) /*DDR_OP_MODE_CFG */
97 #define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130) /*DDR_PHY_RET_CFG */
98 #define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134) /*26M_SEL_CFG */
99 #define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138) /*MEM_PD_CFG0 */
100 #define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C) /*MEM_PD_CFG1 */
101 #define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140) /*PD_DDR_PUBL_CFG */
102 #define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144) /*PD_DDR_PHY_CFG */
103 #define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148) /*BISR_CFG2 */
104 #define REG_PMU_APB_DEBUG_PD0 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C) /*DEBUG_PD0 */
105 #define REG_PMU_APB_DEBUG_PD1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150) /*DEBUG_PD1 */
106 #define REG_PMU_APB_DEBUG_PD2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154) /*DEBUG_PD2 */
107 #define REG_PMU_APB_DEBUG_PD3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158) /*DEBUG_PD3 */
108 #define REG_PMU_APB_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x015C) /*INT_DIABLE */
109 #define REG_PMU_APB_PMU_DEBUG_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0160) /*PMU_DEBUG_CFG */
111 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
112 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) )
113 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) )
114 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
115 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
116 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
117 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
119 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
120 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) )
121 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) )
122 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) )
123 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
124 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
125 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
127 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
128 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) )
129 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) )
130 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) )
131 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
132 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
133 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
135 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
136 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) )
137 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) )
138 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) )
139 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
140 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
141 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
143 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
144 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) )
145 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) )
146 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) )
147 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
148 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
149 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
151 /* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
153 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
154 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) )
155 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
156 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
157 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
158 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
160 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
161 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) )
162 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
163 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
164 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
165 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
167 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
168 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) )
169 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
170 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
171 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
172 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
174 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
175 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) )
176 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) )
177 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
178 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
179 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
181 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
182 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) )
183 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) )
184 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
185 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
186 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
188 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
189 #define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN ( BIT(25) )
190 #define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN ( BIT(24) )
191 #define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
192 #define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
193 #define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
195 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
196 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) )
197 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) )
198 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
199 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
200 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
202 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
203 #define BIT_PD_CP0_GSM_FORCE_SHUTDOWN ( BIT(25) )
204 #define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
205 #define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
206 #define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
207 #define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
209 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
210 #define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) )
211 #define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
212 #define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
213 #define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
214 #define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
216 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */
217 #define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN ( BIT(25) )
218 #define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) )
219 #define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
220 #define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
221 #define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
223 /* bits definitions for register REG_PMU_APB_PD_CP0_HARQ_CFG */
224 #define BIT_PD_CP0_HARQ_FORCE_SHUTDOWN ( BIT(25) )
225 #define BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN ( BIT(24) )
226 #define BITS_PD_CP0_HARQ_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
227 #define BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
228 #define BITS_PD_CP0_HARQ_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
230 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
231 #define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(28) )
232 #define BIT_PD_CP0_SYS_FORCE_SHUTDOWN ( BIT(25) )
233 #define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
234 #define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
235 #define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
237 /* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
238 #define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN ( BIT(25) )
239 #define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
240 #define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
241 #define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
242 #define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
244 /* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
245 #define BIT_PD_CP1_GSM_FORCE_SHUTDOWN ( BIT(25) )
246 #define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
247 #define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
248 #define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
249 #define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
251 /* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
252 #define BIT_PD_CP1_TD_FORCE_SHUTDOWN ( BIT(25) )
253 #define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
254 #define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
255 #define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
256 #define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
258 /* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
259 #define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN ( BIT(25) )
260 #define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN ( BIT(24) )
261 #define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
262 #define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
263 #define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
265 /* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
266 #define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(28) )
267 #define BIT_PD_CP1_SYS_FORCE_SHUTDOWN ( BIT(25) )
268 #define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
269 #define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
270 #define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
272 /* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
273 #define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN ( BIT(25) )
274 #define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
275 #define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
276 #define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
277 #define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
279 /* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
280 #define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN ( BIT(25) )
281 #define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN ( BIT(24) )
282 #define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
283 #define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
284 #define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
286 /* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
287 #define BIT_AP_WAKEUP_POR_N ( BIT(0) )
289 /* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
290 #define BIT_CP2_FORCE_DEEP_SLEEP ( BIT(28) )
291 #define BIT_PD_CP2_SYS_FORCE_SHUTDOWN ( BIT(25) )
292 #define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
293 #define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
294 #define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
296 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
297 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) )
298 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
299 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
300 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
301 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
303 /* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
304 #define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
305 #define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
307 /* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
308 #define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
309 #define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
311 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
312 #define BITS_WPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
313 #define BITS_TDPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
314 #define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
315 #define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
317 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
318 #define BITS_WIFIPLL2_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
319 #define BITS_WIFIPLL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
320 #define BITS_CPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
322 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
323 #define BIT_XTL0_CP2_SEL ( BIT(3) )
324 #define BIT_XTL0_CP1_SEL ( BIT(2) )
325 #define BIT_XTL0_CP0_SEL ( BIT(1) )
326 #define BIT_XTL0_AP_SEL ( BIT(0) )
328 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
329 #define BIT_XTL1_CP2_SEL ( BIT(3) )
330 #define BIT_XTL1_CP1_SEL ( BIT(2) )
331 #define BIT_XTL1_CP0_SEL ( BIT(1) )
332 #define BIT_XTL1_AP_SEL ( BIT(0) )
334 /* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
335 #define BIT_XTL2_CP2_SEL ( BIT(3) )
336 #define BIT_XTL2_CP1_SEL ( BIT(2) )
337 #define BIT_XTL2_CP0_SEL ( BIT(1) )
338 #define BIT_XTL2_AP_SEL ( BIT(0) )
340 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
341 #define BIT_XTLBUF0_CP2_SEL ( BIT(3) )
342 #define BIT_XTLBUF0_CP1_SEL ( BIT(2) )
343 #define BIT_XTLBUF0_CP0_SEL ( BIT(1) )
344 #define BIT_XTLBUF0_AP_SEL ( BIT(0) )
346 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
347 #define BIT_XTLBUF1_CP2_SEL ( BIT(3) )
348 #define BIT_XTLBUF1_CP1_SEL ( BIT(2) )
349 #define BIT_XTLBUF1_CP0_SEL ( BIT(1) )
350 #define BIT_XTLBUF1_AP_SEL ( BIT(0) )
352 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
353 #define BIT_MPLL_REF_SEL ( BIT(4) )
354 #define BIT_MPLL_CP2_SEL ( BIT(3) )
355 #define BIT_MPLL_CP1_SEL ( BIT(2) )
356 #define BIT_MPLL_CP0_SEL ( BIT(1) )
357 #define BIT_MPLL_AP_SEL ( BIT(0) )
359 /* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
360 #define BIT_DPLL_REF_SEL ( BIT(4) )
361 #define BIT_DPLL_CP2_SEL ( BIT(3) )
362 #define BIT_DPLL_CP1_SEL ( BIT(2) )
363 #define BIT_DPLL_CP0_SEL ( BIT(1) )
364 #define BIT_DPLL_AP_SEL ( BIT(0) )
366 /* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
367 #define BIT_TDPLL_REF_SEL ( BIT(4) )
368 #define BIT_TDPLL_CP2_SEL ( BIT(3) )
369 #define BIT_TDPLL_CP1_SEL ( BIT(2) )
370 #define BIT_TDPLL_CP0_SEL ( BIT(1) )
371 #define BIT_TDPLL_AP_SEL ( BIT(0) )
373 /* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
374 #define BIT_WPLL_REF_SEL ( BIT(4) )
375 #define BIT_WPLL_CP2_SEL ( BIT(3) )
376 #define BIT_WPLL_CP1_SEL ( BIT(2) )
377 #define BIT_WPLL_CP0_SEL ( BIT(1) )
378 #define BIT_WPLL_AP_SEL ( BIT(0) )
380 /* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
381 #define BIT_CPLL_REF_SEL ( BIT(4) )
382 #define BIT_CPLL_CP2_SEL ( BIT(3) )
383 #define BIT_CPLL_CP1_SEL ( BIT(2) )
384 #define BIT_CPLL_CP0_SEL ( BIT(1) )
385 #define BIT_CPLL_AP_SEL ( BIT(0) )
387 /* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
388 #define BIT_WIFIPLL1_REF_SEL ( BIT(4) )
389 #define BIT_WIFIPLL1_CP2_SEL ( BIT(3) )
390 #define BIT_WIFIPLL1_CP1_SEL ( BIT(2) )
391 #define BIT_WIFIPLL1_CP0_SEL ( BIT(1) )
392 #define BIT_WIFIPLL1_AP_SEL ( BIT(0) )
394 /* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
395 #define BIT_WIFIPLL2_REF_SEL ( BIT(4) )
396 #define BIT_WIFIPLL2_CP2_SEL ( BIT(3) )
397 #define BIT_WIFIPLL2_CP1_SEL ( BIT(2) )
398 #define BIT_WIFIPLL2_CP0_SEL ( BIT(1) )
399 #define BIT_WIFIPLL2_AP_SEL ( BIT(0) )
401 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
402 #define BIT_PUB_SOFT_RST ( BIT(6) )
403 #define BIT_AP_SOFT_RST ( BIT(5) )
404 #define BIT_GPU_SOFT_RST ( BIT(4) )
405 #define BIT_MM_SOFT_RST ( BIT(3) )
406 #define BIT_CP2_SOFT_RST ( BIT(2) )
407 #define BIT_CP1_SOFT_RST ( BIT(1) )
408 #define BIT_CP0_SOFT_RST ( BIT(0) )
410 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
411 #define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
412 #define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
414 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
415 #define BITS_CP2_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
417 /* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
418 #define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
419 #define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
420 #define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
421 #define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
422 #define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
423 #define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
424 #define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
426 /* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
427 #define BITS_PD_CP0_SYS_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
428 #define BITS_PD_CP0_GSM_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
429 #define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
430 #define BITS_PD_CP0_ARM9_2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
431 #define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
432 #define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
433 #define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
435 /* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
436 #define BITS_PD_CP2_WIFI_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
437 #define BITS_PD_CP2_ARM9_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
438 #define BITS_PD_CP1_SYS_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
439 #define BITS_PD_CP1_L1RAM_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
440 #define BITS_PD_CP1_TD_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
441 #define BITS_PD_CP1_GSM_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
442 #define BITS_PD_CP1_ARM9_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
444 /* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
445 #define BITS_PD_CP0_HARQ_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
446 #define BITS_PD_CP0_CEVA_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
447 #define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
448 #define BITS_PD_DDR_PHY_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
449 #define BITS_PD_DDR_PUBL_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
450 #define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
451 #define BITS_PD_CP2_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
453 /* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
454 #define BIT_CP0_FORCE_SLEEP ( BIT(12) )
455 #define BIT_CP2_SLEEP_XTL_ON ( BIT(11) )
456 #define BIT_CP1_SLEEP_XTL_ON ( BIT(10) )
457 #define BIT_CP0_SLEEP_XTL_ON ( BIT(9) )
458 #define BIT_AP_SLEEP_XTL_ON ( BIT(8) )
459 #define BIT_DISP_DEEP_SLEEP ( BIT(6) )
460 #define BIT_GPU_DEEP_SLEEP ( BIT(5) )
461 #define BIT_MM_DEEP_SLEEP ( BIT(4) )
462 #define BIT_CP2_DEEP_SLEEP ( BIT(3) )
463 #define BIT_CP1_DEEP_SLEEP ( BIT(2) )
464 #define BIT_CP0_DEEP_SLEEP ( BIT(1) )
465 #define BIT_AP_DEEP_SLEEP ( BIT(0) )
467 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
468 #define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) )
469 #define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) )
470 #define BIT_DDR_PUBL_SOFT_RST ( BIT(10) )
471 #define BIT_DDR_UMCTL_SOFT_RST ( BIT(9) )
472 #define BIT_DDR_PHY_SOFT_RST ( BIT(8) )
473 #define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) )
474 #define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) )
475 #define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) )
476 #define BIT_DDR_PHY_EB ( BIT(2) )
477 #define BIT_DDR_UMCTL_EB ( BIT(1) )
478 #define BIT_DDR_PUBL_EB ( BIT(0) )
480 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
481 #define BITS_CP2_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
482 #define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
483 #define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
484 #define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
486 /* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
487 #define BIT_WIFIPLL2_DIV_AUTO_GATE_EN ( BIT(6) )
488 #define BIT_WIFIPLL1_DIV_AUTO_GATE_EN ( BIT(5) )
489 #define BIT_WPLL_DIV_AUTO_GATE_EN ( BIT(4) )
490 #define BIT_TDPLL_DIV_AUTO_GATE_EN ( BIT(3) )
491 #define BIT_CPLL_DIV_AUTO_GATE_EN ( BIT(2) )
492 #define BIT_DPLL_DIV_AUTO_GATE_EN ( BIT(1) )
493 #define BIT_MPLL_DIV_AUTO_GATE_EN ( BIT(0) )
495 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
496 #define BIT_WIFIPLL2_80M_EN ( BIT(31) )
497 #define BIT_WIFIPLL2_160M_EN ( BIT(30) )
498 #define BIT_WIFIPLL2_120M_EN ( BIT(29) )
499 #define BIT_WIFIPLL1_20M_EN ( BIT(28) )
500 #define BIT_WIFIPLL1_40M_EN ( BIT(27) )
501 #define BIT_WIFIPLL1_80M_EN ( BIT(26) )
502 #define BIT_WIFIPLL1_44M_EN ( BIT(25) )
503 #define BIT_WPLL_76M8_EN ( BIT(24) )
504 #define BIT_WPLL_51M2_EN ( BIT(23) )
505 #define BIT_WPLL_102M4_EN ( BIT(22) )
506 #define BIT_WPLL_307M2_EN ( BIT(21) )
507 #define BIT_WPLL_460M8_EN ( BIT(20) )
508 #define BIT_CPLL_52M_EN ( BIT(19) )
509 #define BIT_CPLL_104M_EN ( BIT(18) )
510 #define BIT_CPLL_208M_EN ( BIT(17) )
511 #define BIT_CPLL_312M_EN ( BIT(16) )
512 #define BIT_TDPLL_38M4_EN ( BIT(15) )
513 #define BIT_TDPLL_76M8_EN ( BIT(14) )
514 #define BIT_TDPLL_51M2_EN ( BIT(13) )
515 #define BIT_TDPLL_153M6_EN ( BIT(12) )
516 #define BIT_TDPLL_64M_EN ( BIT(11) )
517 #define BIT_TDPLL_128M_EN ( BIT(10) )
518 #define BIT_TDPLL_256M_EN ( BIT(9) )
519 #define BIT_TDPLL_12M_EN ( BIT(8) )
520 #define BIT_TDPLL_24M_EN ( BIT(7) )
521 #define BIT_TDPLL_48M_EN ( BIT(6) )
522 #define BIT_TDPLL_96M_EN ( BIT(5) )
523 #define BIT_TDPLL_192M_EN ( BIT(4) )
524 #define BIT_TDPLL_384M_EN ( BIT(3) )
525 #define BIT_DPLL_44M_EN ( BIT(2) )
526 #define BIT_MPLL_37M5_EN ( BIT(1) )
527 #define BIT_MPLL_300M_EN ( BIT(0) )
529 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
530 #define BIT_DPLL_533M_EN ( BIT(2) )
531 #define BIT_WIFIPLL2_20M_EN ( BIT(1) )
532 #define BIT_WIFIPLL2_40M_EN ( BIT(0) )
534 /* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
535 #define BIT_CA7_L2RSTDISABLE ( BIT(0) )
537 /* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
538 #define BIT_CA7_VINITHI_C0 ( BIT(0) )
540 /* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
541 #define BIT_CA7_VINITHI_C1 ( BIT(0) )
543 /* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
544 #define BIT_CA7_VINITHI_C2 ( BIT(0) )
546 /* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
547 #define BIT_CA7_VINITHI_C3 ( BIT(0) )
549 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
550 #define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) )
551 #define BIT_DDR_CTRL_CGM_SEL ( BIT(30) )
552 #define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) )
553 #define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) )
554 #define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) )
555 #define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) )
556 #define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) )
557 #define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) )
558 #define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) )
559 #define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) )
560 #define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) )
561 #define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) )
562 #define BIT_DDR_CHN9_CGM_SEL ( BIT(9) )
563 #define BIT_DDR_CHN8_CGM_SEL ( BIT(8) )
564 #define BIT_DDR_CHN7_CGM_SEL ( BIT(7) )
565 #define BIT_DDR_CHN6_CGM_SEL ( BIT(6) )
566 #define BIT_DDR_CHN5_CGM_SEL ( BIT(5) )
567 #define BIT_DDR_CHN4_CGM_SEL ( BIT(4) )
568 #define BIT_DDR_CHN3_CGM_SEL ( BIT(3) )
569 #define BIT_DDR_CHN2_CGM_SEL ( BIT(2) )
570 #define BIT_DDR_CHN1_CGM_SEL ( BIT(1) )
571 #define BIT_DDR_CHN0_CGM_SEL ( BIT(0) )
573 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
574 #define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) )
575 #define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) )
576 #define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) )
577 #define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) )
578 #define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) )
579 #define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) )
580 #define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) )
581 #define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) )
582 #define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) )
583 #define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) )
585 /* bits definitions for register REG_PMU_APB_BISR_CFG */
586 #define BIT_PD_CP0_CEVA_BISR_DONE ( BIT(31) )
587 #define BIT_PD_CP0_TD_BISR_DONE ( BIT(30) )
588 #define BIT_PD_CP1_TD_BISR_DONE ( BIT(29) )
589 #define BIT_PD_CP1_SYS_BISR_DONE ( BIT(28) )
590 #define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(27) )
591 #define BIT_PD_CP0_SYS_BISR_DONE ( BIT(26) )
592 #define BIT_PD_MM_TOP_BISR_DONE ( BIT(25) )
593 #define BIT_PD_GPU_TOP_BISR_DONE ( BIT(24) )
594 #define BIT_PD_CP0_CEVA_BISR_BUSY ( BIT(23) )
595 #define BIT_PD_CP0_TD_BISR_BUSY ( BIT(22) )
596 #define BIT_PD_CP1_TD_BISR_BUSY ( BIT(21) )
597 #define BIT_PD_CP1_SYS_BISR_BUSY ( BIT(20) )
598 #define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(19) )
599 #define BIT_PD_CP0_SYS_BISR_BUSY ( BIT(18) )
600 #define BIT_PD_MM_TOP_BISR_BUSY ( BIT(17) )
601 #define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(16) )
602 #define BIT_PD_CP0_CEVA_BISR_FORCE_EN ( BIT(15) )
603 #define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) )
604 #define BIT_PD_CP1_TD_BISR_FORCE_EN ( BIT(13) )
605 #define BIT_PD_CP1_SYS_BISR_FORCE_EN ( BIT(12) )
606 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(11) )
607 #define BIT_PD_CP0_SYS_BISR_FORCE_EN ( BIT(10) )
608 #define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(9) )
609 #define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(8) )
610 #define BIT_PD_CP1_TD_BISR_FORCE_BYP ( BIT(7) )
611 #define BIT_PD_CP0_CEVA_BISR_FORCE_BYP ( BIT(6) )
612 #define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(5) )
613 #define BIT_PD_CP1_SYS_BISR_FORCE_BYP ( BIT(4) )
614 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(3) )
615 #define BIT_PD_CP0_SYS_BISR_FORCE_BYP ( BIT(2) )
616 #define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(1) )
617 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(0) )
619 /* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
620 #define BIT_CGM_307M2_AP_AUTO_GATE_EN ( BIT(21) )
621 #define BIT_CGM_208M_AP_AUTO_GATE_EN ( BIT(20) )
622 #define BIT_CGM_12M_AP_AUTO_GATE_EN ( BIT(19) )
623 #define BIT_CGM_24M_AP_AUTO_GATE_EN ( BIT(18) )
624 #define BIT_CGM_48M_AP_AUTO_GATE_EN ( BIT(17) )
625 #define BIT_CGM_51M2_AP_AUTO_GATE_EN ( BIT(16) )
626 #define BIT_CGM_64M_AP_AUTO_GATE_EN ( BIT(15) )
627 #define BIT_CGM_76M8_AP_AUTO_GATE_EN ( BIT(14) )
628 #define BIT_CGM_96M_AP_AUTO_GATE_EN ( BIT(13) )
629 #define BIT_CGM_128M_AP_AUTO_GATE_EN ( BIT(12) )
630 #define BIT_CGM_153M6_AP_AUTO_GATE_EN ( BIT(11) )
631 #define BIT_CGM_192M_AP_AUTO_GATE_EN ( BIT(10) )
632 #define BIT_CGM_256M_AP_AUTO_GATE_EN ( BIT(9) )
633 #define BIT_CGM_384M_AP_AUTO_GATE_EN ( BIT(8) )
634 #define BIT_CGM_312M_AP_AUTO_GATE_EN ( BIT(7) )
635 #define BIT_CGM_MPLL_AP_AUTO_GATE_EN ( BIT(6) )
636 #define BIT_CGM_WPLL_AP_AUTO_GATE_EN ( BIT(5) )
637 #define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN ( BIT(4) )
638 #define BIT_CGM_TDPLL_AP_AUTO_GATE_EN ( BIT(3) )
639 #define BIT_CGM_CPLL_AP_AUTO_GATE_EN ( BIT(2) )
640 #define BIT_CGM_DPLL_AP_AUTO_GATE_EN ( BIT(1) )
641 #define BIT_CGM_26M_AP_AUTO_GATE_EN ( BIT(0) )
643 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
644 #define BIT_CGM_312M_MM_AUTO_GATE_EN ( BIT(27) )
645 #define BIT_CGM_12M_MM_AUTO_GATE_EN ( BIT(26) )
646 #define BIT_CGM_24M_MM_AUTO_GATE_EN ( BIT(25) )
647 #define BIT_CGM_48M_MM_AUTO_GATE_EN ( BIT(24) )
648 #define BIT_CGM_64M_MM_AUTO_GATE_EN ( BIT(23) )
649 #define BIT_CGM_76M8_MM_AUTO_GATE_EN ( BIT(22) )
650 #define BIT_CGM_96M_MM_AUTO_GATE_EN ( BIT(21) )
651 #define BIT_CGM_128M_MM_AUTO_GATE_EN ( BIT(20) )
652 #define BIT_CGM_153M6_MM_AUTO_GATE_EN ( BIT(19) )
653 #define BIT_CGM_192M_MM_AUTO_GATE_EN ( BIT(18) )
654 #define BIT_CGM_256M_MM_AUTO_GATE_EN ( BIT(17) )
655 #define BIT_CGM_26M_MM_AUTO_GATE_EN ( BIT(16) )
656 #define BIT_CGM_153_6M_GPU_AUTO_GATE_EN ( BIT(6) )
657 #define BIT_CGM_384M_GPU_AUTO_GATE_EN ( BIT(5) )
658 #define BIT_CGM_460_8M_GPU_AUTO_GATE_EN ( BIT(4) )
659 #define BIT_CGM_256M_GPU_AUTO_GATE_EN ( BIT(3) )
660 #define BIT_CGM_208M_GPU_AUTO_GATE_EN ( BIT(2) )
661 #define BIT_CGM_312M_GPU_AUTO_GATE_EN ( BIT(1) )
662 #define BIT_CGM_512M_GPU_AUTO_GATE_EN ( BIT(0) )
664 /* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
665 #define BIT_CGM_312M_CP0_AUTO_GATE_EN ( BIT(16) )
666 #define BIT_CGM_208M_CP0_AUTO_GATE_EN ( BIT(15) )
667 #define BIT_CGM_256M_CP0_AUTO_GATE_EN ( BIT(14) )
668 #define BIT_CGM_460M8_CP0W_AUTO_GATE_EN ( BIT(13) )
669 #define BIT_CGM_307M2_CP0W_AUTO_GATE_EN ( BIT(12) )
670 #define BIT_CGM_51M2_CP0W_AUTO_GATE_EN ( BIT(11) )
671 #define BIT_CGM_76M8_CP0W_AUTO_GATE_EN ( BIT(10) )
672 #define BIT_CGM_102M4_CP0W_AUTO_GATE_EN ( BIT(9) )
673 #define BIT_CGM_192M_CP0_AUTO_GATE_EN ( BIT(8) )
674 #define BIT_CGM_51M2_CP0_AUTO_GATE_EN ( BIT(7) )
675 #define BIT_CGM_76M8_CP0_AUTO_GATE_EN ( BIT(6) )
676 #define BIT_CGM_153M6_CP0_AUTO_GATE_EN ( BIT(5) )
677 #define BIT_CGM_48M_CP0_AUTO_GATE_EN ( BIT(4) )
678 #define BIT_CGM_64M_CP0_AUTO_GATE_EN ( BIT(3) )
679 #define BIT_CGM_96M_CP0_AUTO_GATE_EN ( BIT(2) )
680 #define BIT_CGM_128M_CP0_AUTO_GATE_EN ( BIT(1) )
681 #define BIT_CGM_26M_CP0_AUTO_GATE_EN ( BIT(0) )
683 /* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
684 #define BIT_CGM_312M_CP1_AUTO_GATE_EN ( BIT(10) )
685 #define BIT_CGM_256M_CP1_AUTO_GATE_EN ( BIT(9) )
686 #define BIT_CGM_192M_CP1_AUTO_GATE_EN ( BIT(8) )
687 #define BIT_CGM_51M2_CP1_AUTO_GATE_EN ( BIT(7) )
688 #define BIT_CGM_76M8_CP1_AUTO_GATE_EN ( BIT(6) )
689 #define BIT_CGM_153M6_CP1_AUTO_GATE_EN ( BIT(5) )
690 #define BIT_CGM_48M_CP1_AUTO_GATE_EN ( BIT(4) )
691 #define BIT_CGM_96M_CP1_AUTO_GATE_EN ( BIT(3) )
692 #define BIT_CGM_64M_CP1_AUTO_GATE_EN ( BIT(2) )
693 #define BIT_CGM_128M_CP1_AUTO_GATE_EN ( BIT(1) )
694 #define BIT_CGM_26M_CP1_AUTO_GATE_EN ( BIT(0) )
696 /* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
697 #define BIT_CGM_153M6_CP2_AUTO_GATE_EN ( BIT(12) )
698 #define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN ( BIT(11) )
699 #define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN ( BIT(10) )
700 #define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN ( BIT(9) )
701 #define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN ( BIT(8) )
702 #define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN ( BIT(7) )
703 #define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN ( BIT(6) )
704 #define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN ( BIT(5) )
705 #define BIT_CGM_256M_CP2_AUTO_GATE_EN ( BIT(4) )
706 #define BIT_CGM_104M_CP2_AUTO_GATE_EN ( BIT(3) )
707 #define BIT_CGM_208M_CP2_AUTO_GATE_EN ( BIT(2) )
708 #define BIT_CGM_312M_CP2_AUTO_GATE_EN ( BIT(1) )
709 #define BIT_CGM_26M_CP2_AUTO_GATE_EN ( BIT(0) )
711 /* bits definitions for register REG_PMU_APB_CGM_AP_EN */
712 #define BIT_CGM_307M2_AP_EN ( BIT(21) )
713 #define BIT_CGM_208M_AP_EN ( BIT(20) )
714 #define BIT_CGM_12M_AP_EN ( BIT(19) )
715 #define BIT_CGM_24M_AP_EN ( BIT(18) )
716 #define BIT_CGM_48M_AP_EN ( BIT(17) )
717 #define BIT_CGM_51M2_AP_EN ( BIT(16) )
718 #define BIT_CGM_64M_AP_EN ( BIT(15) )
719 #define BIT_CGM_76M8_AP_EN ( BIT(14) )
720 #define BIT_CGM_96M_AP_EN ( BIT(13) )
721 #define BIT_CGM_128M_AP_EN ( BIT(12) )
722 #define BIT_CGM_153M6_AP_EN ( BIT(11) )
723 #define BIT_CGM_192M_AP_EN ( BIT(10) )
724 #define BIT_CGM_256M_AP_EN ( BIT(9) )
725 #define BIT_CGM_384M_AP_EN ( BIT(8) )
726 #define BIT_CGM_312M_AP_EN ( BIT(7) )
727 #define BIT_CGM_MPLL_AP_EN ( BIT(6) )
728 #define BIT_CGM_WPLL_AP_EN ( BIT(5) )
729 #define BIT_CGM_WIFIPLL1_AP_EN ( BIT(4) )
730 #define BIT_CGM_TDPLL_AP_EN ( BIT(3) )
731 #define BIT_CGM_CPLL_AP_EN ( BIT(2) )
732 #define BIT_CGM_DPLL_AP_EN ( BIT(1) )
733 #define BIT_CGM_26M_AP_EN ( BIT(0) )
735 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
736 #define BIT_CGM_312M_MM_EN ( BIT(27) )
737 #define BIT_CGM_12M_MM_EN ( BIT(26) )
738 #define BIT_CGM_24M_MM_EN ( BIT(25) )
739 #define BIT_CGM_48M_MM_EN ( BIT(24) )
740 #define BIT_CGM_64M_MM_EN ( BIT(23) )
741 #define BIT_CGM_76M8_MM_EN ( BIT(22) )
742 #define BIT_CGM_96M_MM_EN ( BIT(21) )
743 #define BIT_CGM_128M_MM_EN ( BIT(20) )
744 #define BIT_CGM_153M6_MM_EN ( BIT(19) )
745 #define BIT_CGM_192M_MM_EN ( BIT(18) )
746 #define BIT_CGM_256M_MM_EN ( BIT(17) )
747 #define BIT_CGM_26M_MM_EN ( BIT(16) )
748 #define BIT_CGM_153_6M_GPU_EN ( BIT(6) )
749 #define BIT_CGM_384M_GPU_EN ( BIT(5) )
750 #define BIT_CGM_460_8M_GPU_EN ( BIT(4) )
751 #define BIT_CGM_256M_GPU_EN ( BIT(3) )
752 #define BIT_CGM_208M_GPU_EN ( BIT(2) )
753 #define BIT_CGM_312M_GPU_EN ( BIT(1) )
754 #define BIT_CGM_512M_GPU_EN ( BIT(0) )
756 /* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
757 #define BIT_CGM_312M_CP0_EN ( BIT(16) )
758 #define BIT_CGM_208M_CP0_EN ( BIT(15) )
759 #define BIT_CGM_256M_CP0_EN ( BIT(14) )
760 #define BIT_CGM_460M8_CP0W_EN ( BIT(13) )
761 #define BIT_CGM_307M2_CP0W_EN ( BIT(12) )
762 #define BIT_CGM_51M2_CP0W_EN ( BIT(11) )
763 #define BIT_CGM_76M8_CP0W_EN ( BIT(10) )
764 #define BIT_CGM_102M4_CP0W_EN ( BIT(9) )
765 #define BIT_CGM_192M_CP0_EN ( BIT(8) )
766 #define BIT_CGM_51M2_CP0_EN ( BIT(7) )
767 #define BIT_CGM_76M8_CP0_EN ( BIT(6) )
768 #define BIT_CGM_153M6_CP0_EN ( BIT(5) )
769 #define BIT_CGM_48M_CP0_EN ( BIT(4) )
770 #define BIT_CGM_64M_CP0_EN ( BIT(3) )
771 #define BIT_CGM_96M_CP0_EN ( BIT(2) )
772 #define BIT_CGM_128M_CP0_EN ( BIT(1) )
773 #define BIT_CGM_26M_CP0_EN ( BIT(0) )
775 /* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
776 #define BIT_CGM_312M_CP1_EN ( BIT(10) )
777 #define BIT_CGM_256M_CP1_EN ( BIT(9) )
778 #define BIT_CGM_192M_CP1_EN ( BIT(8) )
779 #define BIT_CGM_51M2_CP1_EN ( BIT(7) )
780 #define BIT_CGM_76M8_CP1_EN ( BIT(6) )
781 #define BIT_CGM_153M6_CP1_EN ( BIT(5) )
782 #define BIT_CGM_48M_CP1_EN ( BIT(4) )
783 #define BIT_CGM_96M_CP1_EN ( BIT(3) )
784 #define BIT_CGM_64M_CP1_EN ( BIT(2) )
785 #define BIT_CGM_128M_CP1_EN ( BIT(1) )
786 #define BIT_CGM_26M_CP1_EN ( BIT(0) )
788 /* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
789 #define BIT_CGM_153M6_CP2_EN ( BIT(12) )
790 #define BIT_CGM_20M_CP2WF2_EN ( BIT(11) )
791 #define BIT_CGM_80M_CP2WF2_EN ( BIT(10) )
792 #define BIT_CGM_120M_CP2WF2_EN ( BIT(9) )
793 #define BIT_CGM_160M_CP2WF2_EN ( BIT(8) )
794 #define BIT_CGM_20M_CP2WF1_EN ( BIT(7) )
795 #define BIT_CGM_44M_CP2WF1_EN ( BIT(6) )
796 #define BIT_CGM_80M_CP2WF1_EN ( BIT(5) )
797 #define BIT_CGM_256M_CP2_EN ( BIT(4) )
798 #define BIT_CGM_104M_CP2_EN ( BIT(3) )
799 #define BIT_CGM_208M_CP2_EN ( BIT(2) )
800 #define BIT_CGM_312M_CP2_EN ( BIT(1) )
801 #define BIT_CGM_26M_CP2_EN ( BIT(0) )
803 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
804 #define BIT_DDR_PHY_RET_EN ( BIT(28) )
805 #define BIT_DDR_PUBL_RET_EN ( BIT(27) )
806 #define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) )
807 #define BIT_DDR_UMCTL_RET_EN ( BIT(25) )
808 #define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) )
809 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
810 #define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
811 #define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
813 /* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
814 #define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) )
816 /* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
817 #define BIT_CLK26MHZ_REF_1_SEL ( BIT(10) )
818 #define BIT_AON_MEM_PD_EN_CP2 ( BIT(9) )
819 #define BIT_AON_MEM_PD_EN_CP0 ( BIT(8) )
820 #define BIT_AON_MEM_PD_EN_AP ( BIT(7) )
821 #define BIT_LPLL_REF_SEL ( BIT(6) )
822 #define BIT_PUB_26M_SEL ( BIT(5) )
823 #define BIT_AON_26M_SEL ( BIT(4) )
824 #define BIT_CP2_26M_SEL ( BIT(3) )
825 #define BIT_CP1_26M_SEL ( BIT(2) )
826 #define BIT_CP0_26M_SEL ( BIT(1) )
827 #define BIT_AP_26M_SEL ( BIT(0) )
829 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */
830 #define BITS_CP0_W_MEM_PD_CFG_HARQ(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
831 #define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
832 #define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
833 #define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
834 #define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
835 #define BITS_AON_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
836 #define BITS_AON_MEM_PD_CFG_IMC3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
837 #define BITS_AON_MEM_PD_CFG_IMC2(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
838 #define BITS_AON_MEM_PD_CFG_IMC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
839 #define BITS_AON_MEM_PD_CFG_IMC0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
840 #define BITS_AON_MEM_PD_CFG_VBC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
841 #define BITS_AON_MEM_PD_CFG_AUD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
842 #define BITS_AON_MEM_PD_CFG_FM(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
844 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */
845 #define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
846 #define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
847 #define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
848 #define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
849 #define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
850 #define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
851 #define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
852 #define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
853 #define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
854 #define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
855 #define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
856 #define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
857 #define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
859 /* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */
860 #define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN ( BIT(25) )
861 #define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN ( BIT(24) )
862 #define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
863 #define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
864 #define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
866 /* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */
867 #define BIT_PD_DDR_PHY_FORCE_SHUTDOWN ( BIT(25) )
868 #define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN ( BIT(24) )
869 #define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
870 #define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
871 #define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
873 /* bits definitions for register REG_PMU_APB_BISR_CFG2 */
874 #define BIT_PD_CA7_TOP_BISR_DONE ( BIT(15) )
875 #define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(14) )
876 #define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(13) )
877 #define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(12) )
878 #define BIT_PD_CP0_HARQ_BISR_DONE ( BIT(11) )
879 #define BIT_PD_CP0_HARQ_BISR_BUSY ( BIT(10) )
880 #define BIT_PD_CP0_HARQ_BISR_FORCE_EN ( BIT(9) )
881 #define BIT_PD_CP0_HARQ_BISR_FORCE_BYP ( BIT(8) )
882 #define BIT_PD_CP2_WIFI_BISR_DONE ( BIT(7) )
883 #define BIT_PD_AP_SYS_BISR_DONE ( BIT(6) )
884 #define BIT_PD_CP2_WIFI_BISR_BUSY ( BIT(5) )
885 #define BIT_PD_AP_SYS_BISR_BUSY ( BIT(4) )
886 #define BIT_PD_CP2_WIFI_BISR_FORCE_EN ( BIT(3) )
887 #define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(2) )
888 #define BIT_PD_CP2_WIFI_BISR_FORCE_BYP ( BIT(1) )
889 #define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(0) )
891 /* bits definitions for register REG_PMU_APB_DEBUG_PD0 */
892 #define BIT_PD_DDR_PHY_SHUTDOWN_D_B ( BIT(27) )
893 #define BIT_PD_DDR_PUBL_SHUTDOWN_D_B ( BIT(26) )
894 #define BIT_PD_PUB_SYS_SHUTDOWN_D_B ( BIT(25) )
895 #define BIT_PD_CP2_WIFI_SHUTDOWN_D_B ( BIT(24) )
896 #define BIT_PD_CP2_ARM9_SHUTDOWN_D_B ( BIT(23) )
897 #define BIT_PD_CP2_SYS_SHUTDOWN_D_B ( BIT(22) )
898 #define BIT_PD_CP1_L1RAM_SHUTDOWN_D_B ( BIT(21) )
899 #define BIT_PD_CP1_TD_SHUTDOWN_D_B ( BIT(20) )
900 #define BIT_PD_CP1_GSM_SHUTDOWN_D_B ( BIT(19) )
901 #define BIT_PD_CP1_ARM9_SHUTDOWN_D_B ( BIT(18) )
902 #define BIT_PD_CP1_SYS_SHUTDOWN_D_B ( BIT(17) )
903 #define BIT_PD_CP0_CEVA_SHUTDOWN_D_B ( BIT(16) )
904 #define BIT_PD_CP0_TD_SHUTDOWN_D_B ( BIT(15) )
905 #define BIT_PD_CP0_GSM_SHUTDOWN_D_B ( BIT(14) )
906 #define BIT_PD_CP0_HARQ_SHUTDOWN_D_B ( BIT(13) )
907 #define BIT_PD_CP0_HU3GE_SHUTDOWN_D_B ( BIT(12) )
908 #define BIT_PD_CP0_ARM9_2_SHUTDOWN_D_B ( BIT(11) )
909 #define BIT_PD_CP0_ARM9_1_SHUTDOWN_D_B ( BIT(10) )
910 #define BIT_PD_CP0_ARM9_0_SHUTDOWN_D_B ( BIT(9) )
911 #define BIT_PD_CP0_SYS_SHUTDOWN_D_B ( BIT(8) )
912 #define BIT_PD_GPU_TOP_SHUTDOWN_D_B ( BIT(7) )
913 #define BIT_PD_MM_TOP_SHUTDOWN_D_B ( BIT(6) )
914 #define BIT_PD_CA7_C3_SHUTDOWN_D_B ( BIT(5) )
915 #define BIT_PD_CA7_C2_SHUTDOWN_D_B ( BIT(4) )
916 #define BIT_PD_CA7_C1_SHUTDOWN_D_B ( BIT(3) )
917 #define BIT_PD_CA7_C0_SHUTDOWN_D_B ( BIT(2) )
918 #define BIT_PD_CA7_TOP_SHUTDOWN_D_B ( BIT(1) )
919 #define BIT_PD_AP_SYS_SHUTDOWN_D_B ( BIT(0) )
921 /* bits definitions for register REG_PMU_APB_DEBUG_PD1 */
922 #define BIT_PD_DDR_PHY_SHUTDOWN_M_B ( BIT(27) )
923 #define BIT_PD_DDR_PUBL_SHUTDOWN_M_B ( BIT(26) )
924 #define BIT_PD_PUB_SYS_SHUTDOWN_M_B ( BIT(25) )
925 #define BIT_PD_CP2_WIFI_SHUTDOWN_M_B ( BIT(24) )
926 #define BIT_PD_CP2_ARM9_SHUTDOWN_M_B ( BIT(23) )
927 #define BIT_PD_CP2_SYS_SHUTDOWN_M_B ( BIT(22) )
928 #define BIT_PD_CP1_L1RAM_SHUTDOWN_M_B ( BIT(21) )
929 #define BIT_PD_CP1_TD_SHUTDOWN_M_B ( BIT(20) )
930 #define BIT_PD_CP1_GSM_SHUTDOWN_M_B ( BIT(19) )
931 #define BIT_PD_CP1_ARM9_SHUTDOWN_M_B ( BIT(18) )
932 #define BIT_PD_CP1_SYS_SHUTDOWN_M_B ( BIT(17) )
933 #define BIT_PD_CP0_CEVA_SHUTDOWN_M_B ( BIT(16) )
934 #define BIT_PD_CP0_TD_SHUTDOWN_M_B ( BIT(15) )
935 #define BIT_PD_CP0_GSM_SHUTDOWN_M_B ( BIT(14) )
936 #define BIT_PD_CP0_HARQ_SHUTDOWN_M_B ( BIT(13) )
937 #define BIT_PD_CP0_HU3GE_SHUTDOWN_M_B ( BIT(12) )
938 #define BIT_PD_CP0_ARM9_2_SHUTDOWN_M_B ( BIT(11) )
939 #define BIT_PD_CP0_ARM9_1_SHUTDOWN_M_B ( BIT(10) )
940 #define BIT_PD_CP0_ARM9_0_SHUTDOWN_M_B ( BIT(9) )
941 #define BIT_PD_CP0_SYS_SHUTDOWN_M_B ( BIT(8) )
942 #define BIT_PD_GPU_TOP_SHUTDOWN_M_B ( BIT(7) )
943 #define BIT_PD_MM_TOP_SHUTDOWN_M_B ( BIT(6) )
944 #define BIT_PD_CA7_C3_SHUTDOWN_M_B ( BIT(5) )
945 #define BIT_PD_CA7_C2_SHUTDOWN_M_B ( BIT(4) )
946 #define BIT_PD_CA7_C1_SHUTDOWN_M_B ( BIT(3) )
947 #define BIT_PD_CA7_C0_SHUTDOWN_M_B ( BIT(2) )
948 #define BIT_PD_CA7_TOP_SHUTDOWN_M_B ( BIT(1) )
949 #define BIT_PD_AP_SYS_SHUTDOWN_M_B ( BIT(0) )
951 /* bits definitions for register REG_PMU_APB_DEBUG_PD2 */
952 #define BIT_PD_DDR_PHY_ACK_M ( BIT(27) )
953 #define BIT_PD_DDR_PUBL_ACK_M ( BIT(26) )
954 #define BIT_PD_PUB_SYS_ACK_M ( BIT(25) )
955 #define BIT_PD_CP2_WIFI_ACK_M ( BIT(24) )
956 #define BIT_PD_CP2_ARM9_ACK_M ( BIT(23) )
957 #define BIT_PD_CP2_SYS_ACK_M ( BIT(22) )
958 #define BIT_PD_CP1_L1RAM_ACK_M ( BIT(21) )
959 #define BIT_PD_CP1_TD_ACK_M ( BIT(20) )
960 #define BIT_PD_CP1_GSM_ACK_M ( BIT(19) )
961 #define BIT_PD_CP1_ARM9_ACK_M ( BIT(18) )
962 #define BIT_PD_CP1_SYS_ACK_M ( BIT(17) )
963 #define BIT_PD_CP0_CEVA_ACK_M ( BIT(16) )
964 #define BIT_PD_CP0_TD_ACK_M ( BIT(15) )
965 #define BIT_PD_CP0_GSM_ACK_M ( BIT(14) )
966 #define BIT_PD_CP0_HARQ_ACK_M ( BIT(13) )
967 #define BIT_PD_CP0_HU3GE_ACK_M ( BIT(12) )
968 #define BIT_PD_CP0_ARM9_2_ACK_M ( BIT(11) )
969 #define BIT_PD_CP0_ARM9_1_ACK_M ( BIT(10) )
970 #define BIT_PD_CP0_ARM9_0_ACK_M ( BIT(9) )
971 #define BIT_PD_CP0_SYS_ACK_M ( BIT(8) )
972 #define BIT_PD_GPU_TOP_ACK_M ( BIT(7) )
973 #define BIT_PD_MM_TOP_ACK_M ( BIT(6) )
974 #define BIT_PD_CA7_C3_ACK_M ( BIT(5) )
975 #define BIT_PD_CA7_C2_ACK_M ( BIT(4) )
976 #define BIT_PD_CA7_C1_ACK_M ( BIT(3) )
977 #define BIT_PD_CA7_C0_ACK_M ( BIT(2) )
978 #define BIT_PD_CA7_TOP_ACK_M ( BIT(1) )
979 #define BIT_PD_AP_SYS_ACK_M ( BIT(0) )
981 /* bits definitions for register REG_PMU_APB_DEBUG_PD3 */
982 #define BIT_PD_DDR_PHY_ACK_D ( BIT(27) )
983 #define BIT_PD_DDR_PUBL_ACK_D ( BIT(26) )
984 #define BIT_PD_PUB_SYS_ACK_D ( BIT(25) )
985 #define BIT_PD_CP2_WIFI_ACK_D ( BIT(24) )
986 #define BIT_PD_CP2_ARM9_ACK_D ( BIT(23) )
987 #define BIT_PD_CP2_SYS_ACK_D ( BIT(22) )
988 #define BIT_PD_CP1_L1RAM_ACK_D ( BIT(21) )
989 #define BIT_PD_CP1_TD_ACK_D ( BIT(20) )
990 #define BIT_PD_CP1_GSM_ACK_D ( BIT(19) )
991 #define BIT_PD_CP1_ARM9_ACK_D ( BIT(18) )
992 #define BIT_PD_CP1_SYS_ACK_D ( BIT(17) )
993 #define BIT_PD_CP0_CEVA_ACK_D ( BIT(16) )
994 #define BIT_PD_CP0_TD_ACK_D ( BIT(15) )
995 #define BIT_PD_CP0_GSM_ACK_D ( BIT(14) )
996 #define BIT_PD_CP0_HARQ_ACK_D ( BIT(13) )
997 #define BIT_PD_CP0_HU3GE_ACK_D ( BIT(12) )
998 #define BIT_PD_CP0_ARM9_2_ACK_D ( BIT(11) )
999 #define BIT_PD_CP0_ARM9_1_ACK_D ( BIT(10) )
1000 #define BIT_PD_CP0_ARM9_0_ACK_D ( BIT(9) )
1001 #define BIT_PD_CP0_SYS_ACK_D ( BIT(8) )
1002 #define BIT_PD_GPU_TOP_ACK_D ( BIT(7) )
1003 #define BIT_PD_MM_TOP_ACK_D ( BIT(6) )
1004 #define BIT_PD_CA7_C3_ACK_D ( BIT(5) )
1005 #define BIT_PD_CA7_C2_ACK_D ( BIT(4) )
1006 #define BIT_PD_CA7_C1_ACK_D ( BIT(3) )
1007 #define BIT_PD_CA7_C0_ACK_D ( BIT(2) )
1008 #define BIT_PD_CA7_TOP_ACK_D ( BIT(1) )
1009 #define BIT_PD_AP_SYS_ACK_D ( BIT(0) )
1011 /* bits definitions for register REG_PMU_APB_INT_DISABLE */
1012 #define BIT_CP2_INT_DISABLE ( BIT(2) )
1013 #define BIT_CP0_INT_DISABLE ( BIT(1) )
1014 #define BIT_AP_INT_DISABLE ( BIT(0) )
1016 /* bits definitions for register REG_PMU_APB_PMU_DEBUG_CFG */
1017 #define BITS_PMU_DEBUG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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