2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
15 #ifndef __H_REGS_AON_APB_HEADFILE_H__
16 #define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
20 /* registers definitions for AON_APB */
21 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000) /*AHB_EB0 */
22 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004) /*AHB_EB1 */
23 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008) /*AHB_RST0 */
24 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C) /*AHB_RST1 */
25 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010) /*APB_RTC_EB */
26 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014) /*REC_26MHZ_BUF_CFG */
27 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018) /*SINDRV_CTRL */
28 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C) /*ADA_SEL_CTRL */
29 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020) /*VBC_CTRL */
30 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024) /*PWR_CTRL */
31 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028) /*TS_CFG */
32 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C) /*BOOT_MODE */
33 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030) /*BB_BG_CTRL */
34 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034) /*CP_ARM_JTAG_CTRL */
35 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038) /*PLL_SOFT_CNT_DONE */
36 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C) /*DCXO_LC_REG0 */
37 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040) /*DCXO_LC_REG1 */
38 #define REG_AON_APB_DSI_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0048) /*DSI_PHY_CTRL */
39 #define REG_AON_APB_CSI0_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x004C) /*CSI0_PHY_CTRL */
40 #define REG_AON_APB_CSI1_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0050) /*CSI1_PHY_CTRL */
41 #define REG_AON_APB_FUNC_TEST_BOOT_ADDR SCI_ADDR(REGS_AON_APB_BASE, 0x0054) /*FUNC_TEST_BOOT_ADDR */
42 #define REG_AON_APB_RINGOSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0058) /*RINGOSC_CTRL */
43 #define REG_AON_APB_RINGOSC_OBS_CNT SCI_ADDR(REGS_AON_APB_BASE, 0x005C) /*RINGOSC_OBS_CNT */
44 #define REG_AON_APB_DDR_ZQ_CONTROL SCI_ADDR(REGS_AON_APB_BASE, 0x0060) /*DDR_ZQ_CONTROL */
45 #define REG_AON_APB_WBT_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0064) /*WBT_BG_CTRL */
46 #define REG_AON_APB_CLK_DMC_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0080) /*CLK_DMC_CFG */
47 #define REG_AON_APB_SOFT_DFS_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0084) /*SOFT_DFS_CTRL */
48 #define REG_AON_APB_CLK26M_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088) /*CLK26M_CFG */
49 #define REG_AON_APB_HARD_DFS_CTRL_LO SCI_ADDR(REGS_AON_APB_BASE, 0x0090) /*HARD_DFS_CTRL_LO */
50 #define REG_AON_APB_HARD_DFS_CTRL_HI SCI_ADDR(REGS_AON_APB_BASE, 0x0094) /*HARD_DFS_CTRL_HI */
51 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC) /*AON_CHIP_ID */
52 #define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000) /*MPLL_CFG */
53 #define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004) /*DPLL_CFG */
54 #define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008) /*TDPLL_CFG */
55 #define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C) /*CPLL_CFG */
56 #define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010) /*WIFIPLL0_CFG */
57 #define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014) /*WIFIPLL1_CFG */
58 #define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018) /*WPLL_CFG0 */
59 #define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C) /*WPLL_CFG1 */
60 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020) /*AON_CGM_CFG */
61 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024) /*CP0_ADDR_REMAP_CTRL0 */
62 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028) /*CP0_ADDR_REMAP_CTRL1 */
63 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C) /*CP1_ADDR_REMAP_CTRL0 */
64 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030) /*CP1_ADDR_REMAP_CTRL1 */
65 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034) /*CP2_ADDR_REMAP_CTRL0 */
66 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038) /*CP2_ADDR_REMAP_CTRL1 */
67 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C) /*IO_DLY_CTRL */
68 #define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040) /*AP_WPROT_EN */
69 #define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044) /*CP0_WPROT_EN */
70 #define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048) /*CP1_WPROT_EN */
71 #define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C) /*CP2_WPROT_EN */
72 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050) /*PMU_RST_MONITOR */
73 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054) /*THM_RST_MONITOR */
74 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058) /*AP_RST_MONITOR */
75 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C) /*CA7_RST_MONITOR */
76 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060) /*BOND_OPT0 */
77 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064) /*BOND_OPT1 */
78 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068) /*RES_REG0 */
79 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C) /*RES_REG1 */
80 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070) /*MPLL_CFG1 */
81 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074) /*DPLL_CFG1 */
82 #define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078) /*TDPLL_CFG1 */
83 #define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C) /*CPLL_CFG1 */
84 #define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080) /*WIFIPLL1_CFG1 */
85 #define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084) /*WIFIPLL2_CFG1 */
86 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088) /*AON_QOS_CFG */
87 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C) /*BB_LDO_CAL_START */
88 #define REG_AON_APB_WBT_BG_LDO SCI_ADDR(REGS_AON_APB_BASE, 0x3090) /*WBT_BG_LDO */
89 #define REG_AON_APB_ANA_BB_MISC SCI_ADDR(REGS_AON_APB_BASE, 0x3094) /*ANA_BB_MISC */
90 #define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3098) /*DJTAG_MUX_SEL */
91 #define REG_AON_APB_BBPLL_RESERVED_0 SCI_ADDR(REGS_AON_APB_BASE, 0x309C) /*BBPLL_RESERVED_0 */
92 #define REG_AON_APB_BBPLL_RESERVED_1 SCI_ADDR(REGS_AON_APB_BASE, 0x30A0) /*BBPLL_RESERVED_1 */
93 #define REG_AON_APB_RPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x30A4) /*RPLL_CFG0 */
94 #define REG_AON_APB_AON_DEBUG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x30A8) /*AON_DEBUG_CFG */
96 /* bits definitions for register REG_AON_APB_APB_EB0 */
97 #define BIT_I2C_EB ( BIT(31) )
98 #define BIT_CA7_DAP_EB ( BIT(30) )
99 #define BIT_CA7_TS1_EB ( BIT(29) )
100 #define BIT_CA7_TS0_EB ( BIT(28) )
101 #define BIT_GPU_EB ( BIT(27) )
102 #define BIT_AON_CKG_EB ( BIT(26) )
103 #define BIT_MM_EB ( BIT(25) )
104 #define BIT_AP_WDG_EB ( BIT(24) )
105 #define BIT_MSPI_EB ( BIT(23) )
106 #define BIT_SPLK_EB ( BIT(22) )
107 #define BIT_IPI_EB ( BIT(21) )
108 #define BIT_PIN_EB ( BIT(20) )
109 #define BIT_VBC_EB ( BIT(19) )
110 #define BIT_AUD_EB ( BIT(18) )
111 #define BIT_AUDIF_EB ( BIT(17) )
112 #define BIT_ADI_EB ( BIT(16) )
113 #define BIT_INTC_EB ( BIT(15) )
114 #define BIT_EIC_EB ( BIT(14) )
115 #define BIT_EFUSE_EB ( BIT(13) )
116 #define BIT_AP_TMR0_EB ( BIT(12) )
117 #define BIT_AON_TMR_EB ( BIT(11) )
118 #define BIT_AP_SYST_EB ( BIT(10) )
119 #define BIT_AON_SYST_EB ( BIT(9) )
120 #define BIT_KPD_EB ( BIT(8) )
121 #define BIT_PWM3_EB ( BIT(7) )
122 #define BIT_PWM2_EB ( BIT(6) )
123 #define BIT_PWM1_EB ( BIT(5) )
124 #define BIT_PWM0_EB ( BIT(4) )
125 #define BIT_GPIO_EB ( BIT(3) )
126 #define BIT_TPC_EB ( BIT(2) )
127 #define BIT_FM_EB ( BIT(1) )
128 #define BIT_ADC_EB ( BIT(0) )
130 /* bits definitions for register REG_AON_APB_APB_EB1 */
131 #define BIT_EMC_REF_CKG_EN ( BIT(20) )
132 #define BIT_DJTAG_EB ( BIT(19) )
133 #define BIT_RINGOSC_EB ( BIT(18) )
134 #define BIT_PUB_REG_EB ( BIT(17) )
135 #define BIT_DMC_EB ( BIT(16) )
136 #define BIT_RFTI_SBI_EB ( BIT(15) )
137 #define BIT_MDAR_EB ( BIT(14) )
138 #define BIT_GSP_EMC_EB ( BIT(13) )
139 #define BIT_ZIP_EMC_EB ( BIT(12) )
140 #define BIT_DISP_EMC_EB ( BIT(11) )
141 #define BIT_AP_TMR2_EB ( BIT(10) )
142 #define BIT_AP_TMR1_EB ( BIT(9) )
143 #define BIT_CA7_WDG_EB ( BIT(8) )
144 #define BIT_AVS1_EB ( BIT(7) )
145 #define BIT_AVS0_EB ( BIT(6) )
146 #define BIT_PROBE_EB ( BIT(5) )
147 #define BIT_AUX2_EB ( BIT(4) )
148 #define BIT_AUX1_EB ( BIT(3) )
149 #define BIT_AUX0_EB ( BIT(2) )
150 #define BIT_THM_EB ( BIT(1) )
151 #define BIT_PMU_EB ( BIT(0) )
153 /* bits definitions for register REG_AON_APB_APB_RST0 */
154 #define BIT_I2C_SOFT_RST ( BIT(30) )
155 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
156 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
157 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
158 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
159 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
160 #define BIT_SPLK_SOFT_RST ( BIT(24) )
161 #define BIT_IPI_SOFT_RST ( BIT(23) )
162 #define BIT_AON_CKG_SOFT_RST ( BIT(22) )
163 #define BIT_PIN_SOFT_RST ( BIT(21) )
164 #define BIT_VBC_SOFT_RST ( BIT(20) )
165 #define BIT_AUD_SOFT_RST ( BIT(19) )
166 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
167 #define BIT_ADI_SOFT_RST ( BIT(17) )
168 #define BIT_INTC_SOFT_RST ( BIT(16) )
169 #define BIT_EIC_SOFT_RST ( BIT(15) )
170 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
171 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
172 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
173 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
174 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
175 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
176 #define BIT_KPD_SOFT_RST ( BIT(8) )
177 #define BIT_PWM3_SOFT_RST ( BIT(7) )
178 #define BIT_PWM2_SOFT_RST ( BIT(6) )
179 #define BIT_PWM1_SOFT_RST ( BIT(5) )
180 #define BIT_PWM0_SOFT_RST ( BIT(4) )
181 #define BIT_GPIO_SOFT_RST ( BIT(3) )
182 #define BIT_TPC_SOFT_RST ( BIT(2) )
183 #define BIT_FM_SOFT_RST ( BIT(1) )
184 #define BIT_ADC_SOFT_RST ( BIT(0) )
186 /* bits definitions for register REG_AON_APB_APB_RST1 */
187 #define BIT_PUB_DJTAG_SOFT_RST ( BIT(23) )
188 #define BIT_GPU_DJTAG_SOFT_RST ( BIT(22) )
189 #define BIT_MM_DJTAG_SOFT_RST ( BIT(21) )
190 #define BIT_CP2_DJTAG_SOFT_RST ( BIT(20) )
191 #define BIT_CP0_DJTAG_SOFT_RST ( BIT(19) )
192 #define BIT_AP_DJTAG_SOFT_RST ( BIT(18) )
193 #define BIT_AON_DJTAG_SOFT_RST ( BIT(17) )
194 #define BIT_LVDSRF_CALI_SOFT_RST ( BIT(16) )
195 #define BIT_LTH_SOFT_RST ( BIT(15) )
196 #define BIT_RINGOSC_SOFT_RST ( BIT(14) )
197 #define BIT_RFTI_SBI_SOFT_RST ( BIT(13) )
198 #define BIT_MDAR_SOFT_RST ( BIT(12) )
199 #define BIT_BB_CAL_SOFT_RST ( BIT(11) )
200 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
201 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
202 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
203 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
204 #define BIT_AVS1_SOFT_RST ( BIT(6) )
205 #define BIT_AVS0_SOFT_RST ( BIT(5) )
206 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
207 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
208 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
209 #define BIT_THM_SOFT_RST ( BIT(1) )
210 #define BIT_PMU_SOFT_RST ( BIT(0) )
212 /* bits definitions for register REG_AON_APB_APB_RTC_EB */
213 #define BIT_BB_CAL_RTC_EB ( BIT(18) )
214 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
215 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
216 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
217 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
218 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
219 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
220 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
221 #define BIT_THM_RTC_EB ( BIT(10) )
222 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
223 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
224 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
225 #define BIT_EIC_RTC_EB ( BIT(6) )
226 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
227 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
228 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
229 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
230 #define BIT_KPD_RTC_EB ( BIT(1) )
231 #define BIT_ARCH_RTC_EB ( BIT(0) )
233 /* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
234 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
235 #define BIT_REC_26MHZ_1_FORCE_PD ( BIT(5) )
236 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
237 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
239 /* bits definitions for register REG_AON_APB_SINDRV_CTRL */
240 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
241 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
242 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
243 #define BIT_SINDRV_ENA ( BIT(0) )
245 /* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
246 #define BIT_RAM_TD_MODE_SEL ( BIT(4) )
247 #define BIT_TW_MODE_SEL ( BIT(3) )
248 #define BIT_WGADC_DIV_EN ( BIT(2) )
249 #define BIT_AFCDAC_SYS_SEL ( BIT(1) )
250 #define BIT_APCDAC_SYS_SEL ( BIT(0) )
252 /* bits definitions for register REG_AON_APB_VBC_CTRL */
253 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
254 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
255 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
256 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
257 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
258 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
259 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
260 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
261 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
262 #define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
263 #define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
264 #define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
265 #define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
267 /* bits definitions for register REG_AON_APB_PWR_CTRL */
268 #define BIT_DSI_PHY_PD_S ( BIT(15) )
269 #define BIT_CSI1_PHY_PD_S ( BIT(14) )
270 #define BIT_CSI0_PHY_PD_S ( BIT(13) )
271 #define BIT_DSI_PHY_PD ( BIT(12) )
272 #define BIT_CSI1_PHY_PD ( BIT(11) )
273 #define BIT_CSI0_PHY_PD ( BIT(10) )
274 #define BIT_CA7_TS1_STOP ( BIT(9) )
275 #define BIT_CA7_TS0_STOP ( BIT(8) )
276 #define BIT_EFUSE_BIST_PWR_ON ( BIT(3) )
277 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
278 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
279 #define BIT_USB_PHY_PD ( BIT(0) )
281 /* bits definitions for register REG_AON_APB_TS_CFG */
282 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
283 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
284 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
285 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
286 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
287 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
288 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
289 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
290 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
292 /* bits definitions for register REG_AON_APB_BOOT_MODE */
293 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
294 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
295 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
296 #define BIT_PTEST_FUNC_DMA_MODE ( BIT(6) )
297 #define BIT_USB_DLOAD_EN ( BIT(4) )
298 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
299 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
300 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
301 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
303 /* bits definitions for register REG_AON_APB_BB_BG_CTRL */
304 #define BIT_BB_CON_BG ( BIT(22) )
305 #define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
306 #define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
307 #define BIT_BB_BG_RBIAS_EN ( BIT(15) )
308 #define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
309 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
310 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
311 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
312 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
313 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
314 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
315 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
316 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
317 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
319 /* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
320 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
322 /* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
323 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
324 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
325 #define BIT_WIFIPLL2_SOFT_CNT_DONE ( BIT(6) )
326 #define BIT_WIFIPLL1_SOFT_CNT_DONE ( BIT(5) )
327 #define BIT_CPLL_SOFT_CNT_DONE ( BIT(4) )
328 #define BIT_WPLL_SOFT_CNT_DONE ( BIT(3) )
329 #define BIT_TDPLL_SOFT_CNT_DONE ( BIT(2) )
330 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
331 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
333 /* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
334 #define BIT_DCXO_LC_FLAG ( BIT(8) )
335 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
336 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
338 /* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
339 #define BITS_DCXO_LC_CNT(_X_) (_X_)
341 /* bits definitions for register REG_AON_APB_DSI_PHY_CTRL */
342 #define BIT_DSI_PHY_IF_SEL ( BIT(24) )
343 #define BITS_DSI_PHY_TRIMBG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
344 #define BITS_DSI_PHY_TX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
345 #define BITS_DSI_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
347 /* bits definitions for register REG_AON_APB_CSI0_PHY_CTRL */
348 #define BIT_CSI0_PHY_IF_SEL ( BIT(24) )
349 #define BITS_CSI0_PHY_RX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
350 #define BITS_CSI0_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
352 /* bits definitions for register REG_AON_APB_CSI1_PHY_CTRL */
353 #define BIT_CSI1_PHY_IF_SEL ( BIT(24) )
354 #define BITS_CSI1_PHY_RX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
355 #define BITS_CSI1_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
357 /* bits definitions for register REG_AON_APB_FUNC_TEST_BOOT_ADDR */
358 #define BITS_FUNC_TEST_BOOT_ADDR(_X_) (_X_)
360 /* bits definitions for register REG_AON_APB_RINGOSC_CTRL */
361 #define BITS_RINGOSC_CNT_CLK_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
362 #define BIT_AP_RINGOSC_EN_CA7_TOP ( BIT(15) )
363 #define BIT_AP_RINGOSC_EN_AP_TOP ( BIT(14) )
364 #define BITS_AP_RINGOSC_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
365 #define BITS_RINGOSC_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
367 /* bits definitions for register REG_AON_APB_RINGOSC_OBS_CNT */
368 #define BIT_RINGOSC_OBS_CNT_OVERFLOW ( BIT(16) )
369 #define BITS_RINGOSC_OBS_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
371 /* bits definitions for register REG_AON_APB_DDR_ZQ_CONTROL */
372 #define BIT_DDR_ZQ_CALOVER ( BIT(17) )
373 #define BIT_DDR_ZQ_PD ( BIT(16) )
374 #define BIT_DDR_ZQ_CAL ( BIT(15) )
375 #define BITS_DDR_ZQ_ZPROG(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
376 #define BITS_DDR_ZQ_DRVP(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
377 #define BITS_DDR_ZQ_DRVN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
379 /* bits definitions for register REG_AON_APB_WBT_BG_CTRL */
380 #define BIT_WBT_LDO_CAL_RST ( BIT(25) )
381 #define BIT_WBT_LDO_CAL_START ( BIT(24) )
382 #define BIT_WBT_LDO_CAL_CLK ( BIT(23) )
383 #define BIT_WBT_CON_BG ( BIT(22) )
384 #define BITS_WBT_LDO_V(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
385 #define BIT_WBT_BG_RBIAS_EN ( BIT(17) )
386 #define BIT_WBT_BG_IEXT_IB_EN ( BIT(16) )
387 #define BIT_WBT_LDO_AUTO_PD_EN ( BIT(11) )
388 #define BIT_WBT_LDO_SLP_PD_EN ( BIT(10) )
389 #define BIT_WBT_LDO_FORCE_ON ( BIT(9) )
390 #define BIT_WBT_LDO_FORCE_PD ( BIT(8) )
391 #define BIT_WBT_BG_AUTO_PD_EN ( BIT(3) )
392 #define BIT_WBT_BG_SLP_PD_EN ( BIT(2) )
393 #define BIT_WBT_BG_FORCE_ON ( BIT(1) )
394 #define BIT_WBT_BG_FORCE_PD ( BIT(0) )
396 /* bits definitions for register REG_AON_APB_CLK_DMC_CFG */
397 #define BITS_CLK_DMC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
398 #define BITS_CLK_DMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
400 /* bits definitions for register REG_AON_APB_SOFT_DFS_CTRL */
401 #define BITS_PUB_DFS_SW_SWITCH_PERIOD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
402 #define BITS_PUB_DFS_SW_RATIO(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
403 #define BITS_PUB_DFS_SW_FRQ_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
404 #define BIT_PUB_DFS_SW_RESP ( BIT(3) )
405 #define BIT_PUB_DFS_SW_ACK ( BIT(2) )
406 #define BIT_PUB_DFS_SW_REQ ( BIT(1) )
407 #define BIT_PUB_DFS_SW_ENABLE ( BIT(0) )
409 /* bits definitions for register REG_AON_APB_CLK26M_CFG */
410 #define BIT_CLKBAK_EN ( BIT(4) )
411 #define BIT_CLK26MHZ_A2D_1_SEL ( BIT(3) )
412 #define BIT_CLK26MHZ_A2D_0_SEL ( BIT(2) )
413 #define BITS_CLK26M_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
415 /* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_LO */
416 #define BITS_PUB_DFS_HW_INITIAL_FREQ(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
417 #define BIT_PUB_DFS_HW_STOP ( BIT(2) )
418 #define BIT_PUB_DFS_HW_START ( BIT(1) )
419 #define BIT_PUB_DFS_HW_ENABLE ( BIT(0) )
421 /* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_HI */
422 #define BITS_PUB_DFS_HW_SWITCH_PERIOD(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
423 #define BITS_PUB_DFS_HW_F3_RATIO(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
424 #define BITS_PUB_DFS_HW_F2_RATIO(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
425 #define BITS_PUB_DFS_HW_F1_RATIO(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
426 #define BITS_PUB_DFS_HW_F0_RATIO(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
428 /* bits definitions for register REG_AON_APB_AON_CHIP_ID */
429 #define BITS_AON_CHIP_ID(_X_) (_X_)
431 /* bits definitions for register REG_AON_APB_MPLL_CFG */
432 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
433 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
434 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
435 #define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
437 /* bits definitions for register REG_AON_APB_DPLL_CFG */
438 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
439 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
440 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
441 #define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
443 /* bits definitions for register REG_AON_APB_TDPLL_CFG */
444 #define BIT_TDPLL_DIV5_FORCE_PD ( BIT(31) )
445 #define BIT_TDPLL_DIV3_FORCE_PD ( BIT(30) )
446 #define BIT_TDPLL_DIV2_FORCE_PD ( BIT(29) )
447 #define BIT_TDPLL_DIV5_PD_AUTO ( BIT(28) )
448 #define BIT_TDPLL_DIV3_PD_AUTO ( BIT(27) )
449 #define BIT_TDPLL_DIV2_PD_AUTO ( BIT(26) )
450 #define BITS_TDPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
451 #define BITS_TDPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
452 #define BITS_TDPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
453 #define BITS_TDPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
455 /* bits definitions for register REG_AON_APB_CPLL_CFG */
456 #define BITS_CPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
457 #define BITS_CPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
458 #define BITS_CPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
459 #define BITS_CPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
461 /* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
462 #define BITS_WIFIPLL1_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
463 #define BITS_WIFIPLL1_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
464 #define BITS_WIFIPLL1_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
465 #define BITS_WIFIPLL1_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
467 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
468 #define BITS_WIFIPLL2_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
469 #define BITS_WIFIPLL2_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
470 #define BITS_WIFIPLL2_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
471 #define BITS_WIFIPLL2_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
473 /* bits definitions for register REG_AON_APB_WPLL_CFG0 */
474 #define BITS_WPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
475 #define BITS_WPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
476 #define BITS_WPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
477 #define BITS_WPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
479 /* bits definitions for register REG_AON_APB_WPLL_CFG1 */
480 #define BITS_WPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
481 #define BIT_WPLL_DIV_S ( BIT(10) )
482 #define BITS_WPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
483 #define BIT_WPLL_MOD_EN ( BIT(7) )
484 #define BIT_WPLL_SDM_EN ( BIT(6) )
485 #define BITS_WPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
487 /* bits definitions for register REG_AON_APB_AON_CGM_CFG */
488 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
489 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
490 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
491 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
492 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
493 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
494 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
495 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
497 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
498 #define BITS_CP0_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
499 #define BITS_CP0_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
500 #define BITS_CP0_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
501 #define BITS_CP0_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
502 #define BITS_CP0_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
503 #define BITS_CP0_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
504 #define BITS_CP0_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
505 #define BITS_CP0_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
507 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
508 #define BIT_CP0_PUB_IRAM_B8_PROT_EN ( BIT(12) )
509 #define BIT_CP0_PUB_IRAM_B7_PROT_EN ( BIT(11) )
510 #define BIT_CP0_PUB_IRAM_B6_PROT_EN ( BIT(10) )
511 #define BIT_CP0_PUB_IRAM_B5_PROT_EN ( BIT(9) )
512 #define BIT_CP0_PUB_IRAM_B4_PROT_EN ( BIT(8) )
513 #define BIT_CP0_PUB_IRAM_B3_PROT_EN ( BIT(7) )
514 #define BIT_CP0_PUB_IRAM_B2_PROT_EN ( BIT(6) )
515 #define BIT_CP0_PUB_IRAM_B1_PROT_EN ( BIT(5) )
516 #define BIT_CP0_PUB_IRAM_B0_PROT_EN ( BIT(4) )
517 #define BITS_CP0_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
519 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
520 #define BITS_CP1_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
521 #define BITS_CP1_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
522 #define BITS_CP1_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
523 #define BITS_CP1_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
524 #define BITS_CP1_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
525 #define BITS_CP1_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
526 #define BITS_CP1_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
527 #define BITS_CP1_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
529 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
530 #define BIT_CP1_PUB_IRAM_B8_PROT_EN ( BIT(12) )
531 #define BIT_CP1_PUB_IRAM_B7_PROT_EN ( BIT(11) )
532 #define BIT_CP1_PUB_IRAM_B6_PROT_EN ( BIT(10) )
533 #define BIT_CP1_PUB_IRAM_B5_PROT_EN ( BIT(9) )
534 #define BIT_CP1_PUB_IRAM_B4_PROT_EN ( BIT(8) )
535 #define BIT_CP1_PUB_IRAM_B3_PROT_EN ( BIT(7) )
536 #define BIT_CP1_PUB_IRAM_B2_PROT_EN ( BIT(6) )
537 #define BIT_CP1_PUB_IRAM_B1_PROT_EN ( BIT(5) )
538 #define BIT_CP1_PUB_IRAM_B0_PROT_EN ( BIT(4) )
539 #define BITS_CP1_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
541 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
542 #define BITS_CP2_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
543 #define BITS_CP2_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
544 #define BITS_CP2_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
545 #define BITS_CP2_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
546 #define BITS_CP2_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
547 #define BITS_CP2_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
548 #define BITS_CP2_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
549 #define BITS_CP2_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
551 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
552 #define BIT_CP2_PUB_IRAM_B8_PROT_EN ( BIT(12) )
553 #define BIT_CP2_PUB_IRAM_B7_PROT_EN ( BIT(11) )
554 #define BIT_CP2_PUB_IRAM_B6_PROT_EN ( BIT(10) )
555 #define BIT_CP2_PUB_IRAM_B5_PROT_EN ( BIT(9) )
556 #define BIT_CP2_PUB_IRAM_B4_PROT_EN ( BIT(8) )
557 #define BIT_CP2_PUB_IRAM_B3_PROT_EN ( BIT(7) )
558 #define BIT_CP2_PUB_IRAM_B2_PROT_EN ( BIT(6) )
559 #define BIT_CP2_PUB_IRAM_B1_PROT_EN ( BIT(5) )
560 #define BIT_CP2_PUB_IRAM_B0_PROT_EN ( BIT(4) )
561 #define BITS_CP2_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
563 /* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
564 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
565 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
566 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
568 /* bits definitions for register REG_AON_APB_AP_WPROT_EN */
569 #define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_)
571 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
572 #define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_)
574 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
575 #define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_)
577 /* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
578 #define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_)
580 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
581 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
583 /* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
584 #define BITS_THM_RST_MONITOR(_X_) (_X_)
586 /* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
587 #define BITS_AP_RST_MONITOR(_X_) (_X_)
589 /* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
590 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
592 /* bits definitions for register REG_AON_APB_BOND_OPT0 */
593 #define BITS_BOND_OPTION0(_X_) (_X_)
595 /* bits definitions for register REG_AON_APB_BOND_OPT1 */
596 #define BITS_BOND_OPTION1(_X_) (_X_)
598 /* bits definitions for register REG_AON_APB_RES_REG0 */
599 #define BITS_RES_REG0(_X_) (_X_)
601 /* bits definitions for register REG_AON_APB_RES_REG1 */
602 #define BITS_RES_REG1(_X_) (_X_)
604 /* bits definitions for register REG_AON_APB_MPLL_CFG1 */
605 #define BITS_MPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
606 #define BIT_MPLL_DIV_S ( BIT(10) )
607 #define BITS_MPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
608 #define BIT_MPLL_MOD_EN ( BIT(7) )
609 #define BIT_MPLL_SDM_EN ( BIT(6) )
610 #define BITS_MPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
612 /* bits definitions for register REG_AON_APB_DPLL_CFG1 */
613 #define BITS_DPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
614 #define BIT_DPLL_DIV_S ( BIT(10) )
615 #define BITS_DPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
616 #define BIT_DPLL_MOD_EN ( BIT(7) )
617 #define BIT_DPLL_SDM_EN ( BIT(6) )
618 #define BITS_DPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
620 /* bits definitions for register REG_AON_APB_TDPLL_CFG1 */
621 #define BITS_TDPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
622 #define BIT_TDPLL_DIV_S ( BIT(10) )
623 #define BITS_TDPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
624 #define BIT_TDPLL_MOD_EN ( BIT(7) )
625 #define BIT_TDPLL_SDM_EN ( BIT(6) )
626 #define BITS_TDPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
628 /* bits definitions for register REG_AON_APB_CPLL_CFG1 */
629 #define BITS_CPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
630 #define BIT_CPLL_DIV_S ( BIT(10) )
631 #define BITS_CPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
632 #define BIT_CPLL_MOD_EN ( BIT(7) )
633 #define BIT_CPLL_SDM_EN ( BIT(6) )
634 #define BITS_CPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
636 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */
637 #define BITS_WIFIPLL1_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
638 #define BIT_WIFIPLL1_DIV_S ( BIT(10) )
639 #define BITS_WIFIPLL1_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
640 #define BIT_WIFIPLL1_MOD_EN ( BIT(7) )
641 #define BIT_WIFIPLL1_SDM_EN ( BIT(6) )
642 #define BITS_WIFIPLL1_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
644 /* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */
645 #define BITS_WIFIPLL2_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
646 #define BIT_WIFIPLL2_DIV_S ( BIT(10) )
647 #define BITS_WIFIPLL2_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
648 #define BIT_WIFIPLL2_MOD_EN ( BIT(7) )
649 #define BIT_WIFIPLL2_SDM_EN ( BIT(6) )
650 #define BITS_WIFIPLL2_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
652 /* bits definitions for register REG_AON_APB_AON_QOS_CFG */
653 #define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
654 #define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
655 #define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
656 #define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
658 /* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
659 #define BIT_BB_LDO_CAL_START ( BIT(0) )
661 /* bits definitions for register REG_AON_APB_WBT_BG_LDO */
662 #define BITS_WBT_BG_RESERVED(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
663 #define BITS_WBT_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
665 /* bits definitions for register REG_AON_APB_ANA_BB_MISC */
666 #define BITS_ANA_BB_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
668 /* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */
669 #define BIT_DJTAG_AON_SEL ( BIT(6) )
670 #define BIT_DJTAG_PUB_SEL ( BIT(5) )
671 #define BIT_DJTAG_CP2_SEL ( BIT(4) )
672 #define BIT_DJTAG_CP0_SEL ( BIT(3) )
673 #define BIT_DJTAG_GPU_SEL ( BIT(2) )
674 #define BIT_DJTAG_MM_SEL ( BIT(1) )
675 #define BIT_DJTAG_AP_SEL ( BIT(0) )
677 /* bits definitions for register REG_AON_APB_BBPLL_RESERVED_0 */
678 #define BITS_WPLL_RESERVED(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
679 #define BITS_TDPLL_RESERVED(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
680 #define BITS_MPLL_RESERVED(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
681 #define BITS_CPLL_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
683 /* bits definitions for register REG_AON_APB_BBPLL_RESERVED_1 */
684 #define BITS_LVDSRF_LVPLL_RESERVED(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
685 #define BITS_RPLL_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
687 /* bits definitions for register REG_AON_APB_RPLL_CFG0 */
688 #define BIT_LVDS_LVPLL_REF_SEL_CTRL ( BIT(10) )
689 #define BIT_LVDS_LVPLL_REF_SEL ( BIT(9) )
690 #define BITS_RPLL_PD_CTRL(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) )
691 #define BIT_RPLL_RST_CTRL ( BIT(6) )
692 #define BIT_BBPLL_REFCLK_SEL_CTRL ( BIT(5) )
693 #define BIT_RPLL_26MTESTOUT_EN ( BIT(4) )
694 #define BIT_CLK26MHZ_MUXTUNE_EN ( BIT(3) )
695 #define BIT_BBPLL_REFCLK_SEL ( BIT(2) )
696 #define BIT_RPLL_RST ( BIT(1) )
697 #define BIT_RPLL_PD ( BIT(0) )
699 /* bits definitions for register REG_AON_APB_AON_DEBUG_CFG */
700 #define BITS_AON_DEBUG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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