arch/arm/include/asm/arch-sc8830/chip_x15/__regs_pmu_apb.h

   1 /*
   2  * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  */
  10
  11 //#ifndef __SCI_GLB_REGS_H__
  12 //#error  "Don't include this file directly, Pls include sci_glb_regs.h"
  13 //#endif
  14
  15
  16 #ifndef __H_REGS_PMU_APB_HEADFILE_H__
  17 #define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
  18
  19 #define REGS_PMU_APB
  20
  21 /* registers definitions for PMU_APB */
  22 #define REG_PMU_APB_PD_CA7_TOP_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)
  23 #define REG_PMU_APB_PD_CA7_C0_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)
  24 #define REG_PMU_APB_PD_CA7_C1_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)
  25 #define REG_PMU_APB_PD_CA7_C2_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)
  26 #define REG_PMU_APB_PD_CA7_C3_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)
  27 #define REG_PMU_APB_PD_AP_DISP_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)
  28 #define REG_PMU_APB_PD_AP_SYS_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)
  29 #define REG_PMU_APB_PD_MM_TOP_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)
  30 #define REG_PMU_APB_PD_GPU_TOP_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)
  31 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)
  32 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)
  33 #define REG_PMU_APB_PD_CP0_ARM9_2_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)
  34 #define REG_PMU_APB_PD_CP0_HU3GE_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)
  35 #define REG_PMU_APB_PD_CP0_GSM_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)
  36 #define REG_PMU_APB_PD_CP0_L1RAM_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)
  37 #define REG_PMU_APB_PD_CP0_SYS_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)
  38 #define REG_PMU_APB_PD_CP1_ARM9_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)
  39 #define REG_PMU_APB_PD_CP1_GSM_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)
  40 #define REG_PMU_APB_PD_CP1_TD_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)
  41 #define REG_PMU_APB_PD_CP1_L1RAM_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)
  42 #define REG_PMU_APB_PD_CP1_SYS_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)
  43 #define REG_PMU_APB_PD_CP2_ARM9_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)
  44 #define REG_PMU_APB_PD_CP2_WIFI_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)
  45 #define REG_PMU_APB_AP_WAKEUP_POR_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)
  46 #define REG_PMU_APB_PD_CP2_SYS_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)
  47 #define REG_PMU_APB_PD_PUB_SYS_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)
  48 #define REG_PMU_APB_XTL_WAIT_CNT                          SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)
  49 #define REG_PMU_APB_XTLBUF_WAIT_CNT                       SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)
  50 #define REG_PMU_APB_PLL_WAIT_CNT1                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)
  51 #define REG_PMU_APB_PLL_WAIT_CNT2                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)
  52 #define REG_PMU_APB_XTL0_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)
  53 #define REG_PMU_APB_XTL1_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)
  54 #define REG_PMU_APB_XTL2_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)
  55 #define REG_PMU_APB_XTLBUF0_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)
  56 #define REG_PMU_APB_XTLBUF1_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)
  57 #define REG_PMU_APB_MPLL_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)
  58 #define REG_PMU_APB_DPLL_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)
  59 #define REG_PMU_APB_TDPLL_REL_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)
  60 #define REG_PMU_APB_WPLL_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)
  61 #define REG_PMU_APB_CPLL_REL_CFG                          SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)
  62 #define REG_PMU_APB_WIFIPLL1_REL_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)
  63 #define REG_PMU_APB_WIFIPLL2_REL_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)
  64 #define REG_PMU_APB_CP_SOFT_RST                           SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)
  65 #define REG_PMU_APB_CP_SLP_STATUS_DBG0                    SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)
  66 #define REG_PMU_APB_CP_SLP_STATUS_DBG1                    SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)
  67 #define REG_PMU_APB_PWR_STATUS0_DBG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)
  68 #define REG_PMU_APB_PWR_STATUS1_DBG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)
  69 #define REG_PMU_APB_PWR_STATUS2_DBG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)
  70 #define REG_PMU_APB_PWR_STATUS3_DBG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)
  71 #define REG_PMU_APB_SLEEP_CTRL                            SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)
  72 #define REG_PMU_APB_DDR_SLEEP_CTRL                        SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)
  73 #define REG_PMU_APB_SLEEP_STATUS                          SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)
  74 #define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN                  SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)
  75 #define REG_PMU_APB_PLL_DIV_EN1                           SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)
  76 #define REG_PMU_APB_PLL_DIV_EN2                           SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)
  77 #define REG_PMU_APB_CA7_TOP_CFG                           SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)
  78 #define REG_PMU_APB_CA7_C0_CFG                            SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)
  79 #define REG_PMU_APB_CA7_C1_CFG                            SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)
  80 #define REG_PMU_APB_CA7_C2_CFG                            SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)
  81 #define REG_PMU_APB_CA7_C3_CFG                            SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)
  82 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0                   SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)
  83 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1                   SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)
  84 #define REG_PMU_APB_BISR_CFG                              SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)
  85 #define REG_PMU_APB_CGM_AP_AUTO_GATE_EN                   SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)
  86 #define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN               SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)
  87 #define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)
  88 #define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)
  89 #define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN                  SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)
  90 #define REG_PMU_APB_CGM_AP_EN                             SCI_ADDR(REGS_PMU_APB_BASE, 0x00110)
  91 #define REG_PMU_APB_CGM_GPU_MM_EN                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)
  92 #define REG_PMU_APB_CGM_CP0_EN                            SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)
  93 #define REG_PMU_APB_CGM_CP1_EN                            SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)
  94 #define REG_PMU_APB_CGM_CP2_EN                            SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)
  95 #define REG_PMU_APB_DDR_OP_MODE_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)
  96 #define REG_PMU_APB_DDR_PHY_RET_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)
  97
  98
  99
 100 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
 101 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN                    ( BIT(28) )
 102 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN                     ( BIT(25) )
 103 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN                   ( BIT(24) )
 104 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 105 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 106 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 107
 108 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
 109 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN                     ( BIT(28) )
 110 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN                      ( BIT(25) )
 111 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 112 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 113 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 114 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 115
 116 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
 117 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN                     ( BIT(28) )
 118 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN                      ( BIT(25) )
 119 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 120 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 121 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 122 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 123
 124 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
 125 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN                     ( BIT(28) )
 126 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN                      ( BIT(25) )
 127 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 128 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 129 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 130 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 131
 132 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
 133 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN                     ( BIT(28) )
 134 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN                      ( BIT(25) )
 135 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 136 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 137 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 138 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 139
 140 /* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
 141
 142 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
 143 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN                      ( BIT(25) )
 144 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 145 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 146 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 147 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 148
 149 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
 150 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN                      ( BIT(25) )
 151 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 152 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 153 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 154 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 155
 156 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
 157 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN                     ( BIT(25) )
 158 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN                   ( BIT(24) )
 159 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 160 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 161 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 162
 163 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
 164 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN                  ( BIT(25) )
 165 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN                ( BIT(24) )
 166 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 167 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 168 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 169
 170 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
 171 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN                  ( BIT(25) )
 172 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN                ( BIT(24) )
 173 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 174 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 175 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 176
 177 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
 178 #define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN                  ( BIT(25) )
 179 #define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN                ( BIT(24) )
 180 #define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 181 #define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 182 #define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 183
 184 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
 185 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN                   ( BIT(25) )
 186 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN                 ( BIT(24) )
 187 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 188 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 189 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 190
 191 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
 192 #define BIT_PD_CP0_GSM_FORCE_SHUTDOWN                     ( BIT(25) )
 193 #define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN                   ( BIT(24) )
 194 #define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 195 #define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 196 #define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 197
 198 /* bits definitions for register REG_PMU_APB_PD_CP0_L1RAM_CFG */
 199 #define BIT_PD_CP0_L1RAM_FORCE_SHUTDOWN                   ( BIT(25) )
 200 #define BIT_PD_CP0_L1RAM_AUTO_SHUTDOWN_EN                 ( BIT(24) )
 201 #define BITS_PD_CP0_L1RAM_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 202 #define BITS_PD_CP0_L1RAM_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 203 #define BITS_PD_CP0_L1RAM_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 204
 205 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
 206 #define BIT_CP0_FORCE_DEEP_SLEEP                          ( BIT(28) )
 207 #define BIT_PD_CP0_SYS_FORCE_SHUTDOWN                     ( BIT(25) )
 208 #define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 209 #define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 210 #define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 211
 212 /* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
 213 #define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN                    ( BIT(25) )
 214 #define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN                  ( BIT(24) )
 215 #define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_)                  ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 216 #define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_)              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 217 #define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 218
 219 /* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
 220 #define BIT_PD_CP1_GSM_FORCE_SHUTDOWN                     ( BIT(25) )
 221 #define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN                   ( BIT(24) )
 222 #define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 223 #define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 224 #define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 225
 226 /* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
 227 #define BIT_PD_CP1_TD_FORCE_SHUTDOWN                      ( BIT(25) )
 228 #define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN                    ( BIT(24) )
 229 #define BITS_PD_CP1_TD_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 230 #define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 231 #define BITS_PD_CP1_TD_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 232
 233 /* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
 234 #define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN                   ( BIT(25) )
 235 #define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN                 ( BIT(24) )
 236 #define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 237 #define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 238 #define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 239
 240 /* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
 241 #define BIT_CP1_FORCE_DEEP_SLEEP                          ( BIT(28) )
 242 #define BIT_PD_CP1_SYS_FORCE_SHUTDOWN                     ( BIT(25) )
 243 #define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 244 #define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 245 #define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 246
 247 /* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
 248 #define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN                    ( BIT(25) )
 249 #define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN                  ( BIT(24) )
 250 #define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_)                  ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 251 #define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_)              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 252 #define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 253
 254 /* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
 255 #define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN                    ( BIT(25) )
 256 #define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN                  ( BIT(24) )
 257 #define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_)                  ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 258 #define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_)              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 259 #define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 260
 261 /* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
 262 #define BIT_AP_WAKEUP_POR_N                               ( BIT(0) )
 263
 264 /* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
 265 #define BIT_CP2_FORCE_DEEP_SLEEP                          ( BIT(28) )
 266 #define BIT_PD_CP2_SYS_FORCE_SHUTDOWN                     ( BIT(25) )
 267 #define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 268 #define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 269 #define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 270
 271 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
 272 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN                     ( BIT(25) )
 273 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN                   ( BIT(24) )
 274 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 275 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 276 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 277
 278 /* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
 279 #define BITS_XTL1_WAIT_CNT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 280 #define BITS_XTL0_WAIT_CNT(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 281
 282 /* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
 283 #define BITS_XTLBUF1_WAIT_CNT(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 284 #define BITS_XTLBUF0_WAIT_CNT(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 285
 286 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
 287 #define BITS_WPLL_WAIT_CNT(_X_)                           ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
 288 #define BITS_TDPLL_WAIT_CNT(_X_)                          ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 289 #define BITS_DPLL_WAIT_CNT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 290 #define BITS_MPLL_WAIT_CNT(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 291
 292 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
 293 #define BITS_WIFIPLL2_WAIT_CNT(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 294 #define BITS_WIFIPLL1_WAIT_CNT(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 295 #define BITS_CPLL_WAIT_CNT(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 296
 297 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
 298 #define BIT_XTL0_CP2_SEL                                  ( BIT(3) )
 299 #define BIT_XTL0_CP1_SEL                                  ( BIT(2) )
 300 #define BIT_XTL0_CP0_SEL                                  ( BIT(1) )
 301 #define BIT_XTL0_AP_SEL                                   ( BIT(0) )
 302
 303 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
 304 #define BIT_XTL1_CP2_SEL                                  ( BIT(3) )
 305 #define BIT_XTL1_CP1_SEL                                  ( BIT(2) )
 306 #define BIT_XTL1_CP0_SEL                                  ( BIT(1) )
 307 #define BIT_XTL1_AP_SEL                                   ( BIT(0) )
 308
 309 /* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
 310 #define BIT_XTL2_CP2_SEL                                  ( BIT(3) )
 311 #define BIT_XTL2_CP1_SEL                                  ( BIT(2) )
 312 #define BIT_XTL2_CP0_SEL                                  ( BIT(1) )
 313 #define BIT_XTL2_AP_SEL                                   ( BIT(0) )
 314
 315 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
 316 #define BIT_XTLBUF0_CP2_SEL                               ( BIT(3) )
 317 #define BIT_XTLBUF0_CP1_SEL                               ( BIT(2) )
 318 #define BIT_XTLBUF0_CP0_SEL                               ( BIT(1) )
 319 #define BIT_XTLBUF0_AP_SEL                                ( BIT(0) )
 320
 321 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
 322 #define BIT_XTLBUF1_CP2_SEL                               ( BIT(3) )
 323 #define BIT_XTLBUF1_CP1_SEL                               ( BIT(2) )
 324 #define BIT_XTLBUF1_CP0_SEL                               ( BIT(1) )
 325 #define BIT_XTLBUF1_AP_SEL                                ( BIT(0) )
 326
 327 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
 328 #define BIT_MPLL_REF_SEL                                  ( BIT(4) )
 329 #define BIT_MPLL_CP2_SEL                                  ( BIT(3) )
 330 #define BIT_MPLL_CP1_SEL                                  ( BIT(2) )
 331 #define BIT_MPLL_CP0_SEL                                  ( BIT(1) )
 332 #define BIT_MPLL_AP_SEL                                   ( BIT(0) )
 333
 334 /* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
 335 #define BIT_DPLL_REF_SEL                                  ( BIT(4) )
 336 #define BIT_DPLL_CP2_SEL                                  ( BIT(3) )
 337 #define BIT_DPLL_CP1_SEL                                  ( BIT(2) )
 338 #define BIT_DPLL_CP0_SEL                                  ( BIT(1) )
 339 #define BIT_DPLL_AP_SEL                                   ( BIT(0) )
 340
 341 /* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
 342 #define BIT_TDPLL_REF_SEL                                 ( BIT(4) )
 343 #define BIT_TDPLL_CP2_SEL                                 ( BIT(3) )
 344 #define BIT_TDPLL_CP1_SEL                                 ( BIT(2) )
 345 #define BIT_TDPLL_CP0_SEL                                 ( BIT(1) )
 346 #define BIT_TDPLL_AP_SEL                                  ( BIT(0) )
 347
 348 /* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
 349 #define BIT_WPLL_REF_SEL                                  ( BIT(4) )
 350 #define BIT_WPLL_CP2_SEL                                  ( BIT(3) )
 351 #define BIT_WPLL_CP1_SEL                                  ( BIT(2) )
 352 #define BIT_WPLL_CP0_SEL                                  ( BIT(1) )
 353 #define BIT_WPLL_AP_SEL                                   ( BIT(0) )
 354
 355 /* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
 356 #define BIT_CPLL_REF_SEL                                  ( BIT(4) )
 357 #define BIT_CPLL_CP2_SEL                                  ( BIT(3) )
 358 #define BIT_CPLL_CP1_SEL                                  ( BIT(2) )
 359 #define BIT_CPLL_CP0_SEL                                  ( BIT(1) )
 360 #define BIT_CPLL_AP_SEL                                   ( BIT(0) )
 361
 362 /* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
 363 #define BIT_WIFIPLL1_REF_SEL                              ( BIT(4) )
 364 #define BIT_WIFIPLL1_CP2_SEL                              ( BIT(3) )
 365 #define BIT_WIFIPLL1_CP1_SEL                              ( BIT(2) )
 366 #define BIT_WIFIPLL1_CP0_SEL                              ( BIT(1) )
 367 #define BIT_WIFIPLL1_AP_SEL                               ( BIT(0) )
 368
 369 /* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
 370 #define BIT_WIFIPLL2_REF_SEL                              ( BIT(4) )
 371 #define BIT_WIFIPLL2_CP2_SEL                              ( BIT(3) )
 372 #define BIT_WIFIPLL2_CP1_SEL                              ( BIT(2) )
 373 #define BIT_WIFIPLL2_CP0_SEL                              ( BIT(1) )
 374 #define BIT_WIFIPLL2_AP_SEL                               ( BIT(0) )
 375
 376 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
 377 #define BIT_PUB_SOFT_RST                                  ( BIT(6) )
 378 #define BIT_AP_SOFT_RST                                   ( BIT(5) )
 379 #define BIT_GPU_SOFT_RST                                  ( BIT(4) )
 380 #define BIT_MM_SOFT_RST                                   ( BIT(3) )
 381 #define BIT_CP2_SOFT_RST                                  ( BIT(2) )
 382 #define BIT_CP1_SOFT_RST                                  ( BIT(1) )
 383 #define BIT_CP0_SOFT_RST                                  ( BIT(0) )
 384
 385 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
 386 #define BITS_CP1_DEEP_SLP_DBG(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
 387 #define BITS_CP0_DEEP_SLP_DBG(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 388
 389 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
 390 #define BITS_CP2_DEEP_SLP_DBG(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 391
 392 /* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
 393 #define BITS_PD_MM_TOP_STATE(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
 394 #define BITS_PD_GPU_TOP_STATE(_X_)                        ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
 395 #define BITS_PD_CA7_C3_STATE(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
 396 #define BITS_PD_CA7_C2_STATE(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 397 #define BITS_PD_CA7_C1_STATE(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
 398 #define BITS_PD_CA7_C0_STATE(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 399 #define BITS_PD_CA7_TOP_STATE(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
 400
 401 /* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
 402 #define BITS_PD_CP0_SYS_STATE(_X_)                        ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
 403 #define BITS_PD_CP0_L1RAM_STATE(_X_)                      ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
 404 #define BITS_PD_CP0_GSM_STATE(_X_)                        ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 405 #define BITS_PD_CP0_HU3GE_STATE(_X_)                      ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
 406 #define BITS_PD_CP0_ARM9_2_STATE(_X_)                     ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 407 #define BITS_PD_CP0_ARM9_1_STATE(_X_)                     ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
 408 #define BITS_PD_CP0_ARM9_0_STATE(_X_)                     ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 409 #define BITS_PD_AP_SYS_STATE(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
 410
 411 /* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
 412 #define BITS_PD_CP2_WIFI_STATE(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
 413 #define BITS_PD_CP2_ARM9_STATE(_X_)                       ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 414 #define BITS_PD_CP1_SYS_STATE(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
 415 #define BITS_PD_CP1_L1RAM_STATE(_X_)                      ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 416 #define BITS_PD_CP1_TD_STATE(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
 417 #define BITS_PD_CP1_GSM_STATE(_X_)                        ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 418 #define BITS_PD_CP1_ARM9_STATE(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
 419
 420 /* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
 421 #define BITS_PD_PUB_SYS_STATE(_X_)                        ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 422 #define BITS_PD_CP2_SYS_STATE(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
 423
 424 /* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
 425 #define BIT_CP2_SLEEP_XTL_ON                              ( BIT(11) )
 426 #define BIT_CP1_SLEEP_XTL_ON                              ( BIT(10) )
 427 #define BIT_CP0_SLEEP_XTL_ON                              ( BIT(9) )
 428 #define BIT_AP_SLEEP_XTL_ON                               ( BIT(8) )
 429 #define BIT_DISP_DEEP_SLEEP                               ( BIT(6) )
 430 #define BIT_GPU_DEEP_SLEEP                                ( BIT(5) )
 431 #define BIT_MM_DEEP_SLEEP                                 ( BIT(4) )
 432 #define BIT_CP2_DEEP_SLEEP                                ( BIT(3) )
 433 #define BIT_CP1_DEEP_SLEEP                                ( BIT(2) )
 434 #define BIT_CP0_DEEP_SLEEP                                ( BIT(1) )
 435 #define BIT_AP_DEEP_SLEEP                                 ( BIT(0) )
 436
 437 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
 438 #define BIT_DDR_PUBL_APB_SOFT_RST                         ( BIT(12) )
 439 #define BIT_DDR_UMCTL_APB_SOFT_RST                        ( BIT(11) )
 440 #define BIT_DDR_PUBL_SOFT_RST                             ( BIT(10) )
 441 #define BIT_DDR_PHY_SOFT_RST                              ( BIT(8) )
 442 #define BIT_DDR_PHY_AUTO_GATE_EN                          ( BIT(6) )
 443 #define BIT_DDR_PUBL_AUTO_GATE_EN                         ( BIT(5) )
 444 #define BIT_DDR_UMCTL_AUTO_GATE_EN                        ( BIT(4) )
 445 #define BIT_DDR_PHY_EB                                    ( BIT(2) )
 446 #define BIT_DDR_UMCTL_EB                                  ( BIT(1) )
 447 #define BIT_DDR_PUBL_EB                                   ( BIT(0) )
 448
 449 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
 450 #define BITS_CP2_SLP_STATUS(_X_)                          ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 451 #define BITS_CP1_SLP_STATUS(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
 452 #define BITS_CP0_SLP_STATUS(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 453 #define BITS_AP_SLP_STATUS(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
 454
 455 /* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
 456 #define BIT_WIFIPLL2_DIV_AUTO_GATE_EN                     ( BIT(6) )
 457 #define BIT_WIFIPLL1_DIV_AUTO_GATE_EN                     ( BIT(5) )
 458 #define BIT_WPLL_DIV_AUTO_GATE_EN                         ( BIT(4) )
 459 #define BIT_TDPLL_DIV_AUTO_GATE_EN                        ( BIT(3) )
 460 #define BIT_CPLL_DIV_AUTO_GATE_EN                         ( BIT(2) )
 461 #define BIT_DPLL_DIV_AUTO_GATE_EN                         ( BIT(1) )
 462 #define BIT_MPLL_DIV_AUTO_GATE_EN                         ( BIT(0) )
 463
 464 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
 465 #define BIT_WIFIPLL2_80M_EN                               ( BIT(31) )
 466 #define BIT_WIFIPLL2_160M_EN                              ( BIT(30) )
 467 #define BIT_WIFIPLL2_120M_EN                              ( BIT(29) )
 468 #define BIT_WIFIPLL1_20M_EN                               ( BIT(28) )
 469 #define BIT_WIFIPLL1_40M_EN                               ( BIT(27) )
 470 #define BIT_WIFIPLL1_80M_EN                               ( BIT(26) )
 471 #define BIT_WIFIPLL1_44M_EN                               ( BIT(25) )
 472 #define BIT_WPLL_76M8_EN                                  ( BIT(24) )
 473 #define BIT_WPLL_51M2_EN                                  ( BIT(23) )
 474 #define BIT_WPLL_102M4_EN                                 ( BIT(22) )
 475 #define BIT_WPLL_307M2_EN                                 ( BIT(21) )
 476 #define BIT_WPLL_460M8_EN                                 ( BIT(20) )
 477 #define BIT_CPLL_52M_EN                                   ( BIT(19) )
 478 #define BIT_CPLL_104M_EN                                  ( BIT(18) )
 479 #define BIT_CPLL_208M_EN                                  ( BIT(17) )
 480 #define BIT_CPLL_312M_EN                                  ( BIT(16) )
 481 #define BIT_TDPLL_38M4_EN                                 ( BIT(15) )
 482 #define BIT_TDPLL_76M8_EN                                 ( BIT(14) )
 483 #define BIT_TDPLL_51M2_EN                                 ( BIT(13) )
 484 #define BIT_TDPLL_153M6_EN                                ( BIT(12) )
 485 #define BIT_TDPLL_64M_EN                                  ( BIT(11) )
 486 #define BIT_TDPLL_128M_EN                                 ( BIT(10) )
 487 #define BIT_TDPLL_256M_EN                                 ( BIT(9) )
 488 #define BIT_TDPLL_12M_EN                                  ( BIT(8) )
 489 #define BIT_TDPLL_24M_EN                                  ( BIT(7) )
 490 #define BIT_TDPLL_48M_EN                                  ( BIT(6) )
 491 #define BIT_TDPLL_96M_EN                                  ( BIT(5) )
 492 #define BIT_TDPLL_192M_EN                                 ( BIT(4) )
 493 #define BIT_TDPLL_384M_EN                                 ( BIT(3) )
 494 #define BIT_DPLL_44M_EN                                   ( BIT(2) )
 495 #define BIT_MPLL_37M5_EN                                  ( BIT(1) )
 496 #define BIT_MPLL_300M_EN                                  ( BIT(0) )
 497
 498 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
 499 #define BIT_WIFIPLL2_20M_EN                               ( BIT(1) )
 500 #define BIT_WIFIPLL2_40M_EN                               ( BIT(0) )
 501
 502 /* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
 503 #define BIT_CA7_L2RSTDISABLE                              ( BIT(0) )
 504
 505 /* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
 506 #define BIT_CA7_VINITHI_C0                                ( BIT(0) )
 507
 508 /* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
 509 #define BIT_CA7_VINITHI_C1                                ( BIT(0) )
 510
 511 /* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
 512 #define BIT_CA7_VINITHI_C2                                ( BIT(0) )
 513
 514 /* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
 515 #define BIT_CA7_VINITHI_C3                                ( BIT(0) )
 516
 517 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
 518 #define BIT_DDR_CTRL_AXI_LP_EN                            ( BIT(31) )
 519 #define BIT_DDR_CTRL_CGM_SEL                              ( BIT(30) )
 520 #define BIT_DDR_CHN9_AXI_LP_EN                            ( BIT(25) )
 521 #define BIT_DDR_CHN8_AXI_LP_EN                            ( BIT(24) )
 522 #define BIT_DDR_CHN7_AXI_LP_EN                            ( BIT(23) )
 523 #define BIT_DDR_CHN6_AXI_LP_EN                            ( BIT(22) )
 524 #define BIT_DDR_CHN5_AXI_LP_EN                            ( BIT(21) )
 525 #define BIT_DDR_CHN4_AXI_LP_EN                            ( BIT(20) )
 526 #define BIT_DDR_CHN3_AXI_LP_EN                            ( BIT(19) )
 527 #define BIT_DDR_CHN2_AXI_LP_EN                            ( BIT(18) )
 528 #define BIT_DDR_CHN1_AXI_LP_EN                            ( BIT(17) )
 529 #define BIT_DDR_CHN0_AXI_LP_EN                            ( BIT(16) )
 530 #define BIT_DDR_CHN9_CGM_SEL                              ( BIT(9) )
 531 #define BIT_DDR_CHN8_CGM_SEL                              ( BIT(8) )
 532 #define BIT_DDR_CHN7_CGM_SEL                              ( BIT(7) )
 533 #define BIT_DDR_CHN6_CGM_SEL                              ( BIT(6) )
 534 #define BIT_DDR_CHN5_CGM_SEL                              ( BIT(5) )
 535 #define BIT_DDR_CHN4_CGM_SEL                              ( BIT(4) )
 536 #define BIT_DDR_CHN3_CGM_SEL                              ( BIT(3) )
 537 #define BIT_DDR_CHN2_CGM_SEL                              ( BIT(2) )
 538 #define BIT_DDR_CHN1_CGM_SEL                              ( BIT(1) )
 539 #define BIT_DDR_CHN0_CGM_SEL                              ( BIT(0) )
 540
 541 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
 542 #define BIT_DDR_CHN9_AXI_STOP_SEL                         ( BIT(9) )
 543 #define BIT_DDR_CHN8_AXI_STOP_SEL                         ( BIT(8) )
 544 #define BIT_DDR_CHN7_AXI_STOP_SEL                         ( BIT(7) )
 545 #define BIT_DDR_CHN6_AXI_STOP_SEL                         ( BIT(6) )
 546 #define BIT_DDR_CHN5_AXI_STOP_SEL                         ( BIT(5) )
 547 #define BIT_DDR_CHN4_AXI_STOP_SEL                         ( BIT(4) )
 548 #define BIT_DDR_CHN3_AXI_STOP_SEL                         ( BIT(3) )
 549 #define BIT_DDR_CHN2_AXI_STOP_SEL                         ( BIT(2) )
 550 #define BIT_DDR_CHN1_AXI_STOP_SEL                         ( BIT(1) )
 551 #define BIT_DDR_CHN0_AXI_STOP_SEL                         ( BIT(0) )
 552
 553 /* bits definitions for register REG_PMU_APB_BISR_CFG */
 554 #define BIT_PD_CP1_TD_BISR_DONE                           ( BIT(29) )
 555 #define BIT_PD_CP1_SYS_BISR_DONE                          ( BIT(28) )
 556 #define BIT_PD_CP0_HU3GE_BISR_DONE                        ( BIT(27) )
 557 #define BIT_PD_CP0_SYS_BISR_DONE                          ( BIT(26) )
 558 #define BIT_PD_MM_TOP_BISR_DONE                           ( BIT(25) )
 559 #define BIT_PD_GPU_TOP_BISR_DONE                          ( BIT(24) )
 560 #define BIT_PD_CP1_TD_BISR_BUSY                           ( BIT(21) )
 561 #define BIT_PD_CP1_SYS_BISR_BUSY                          ( BIT(20) )
 562 #define BIT_PD_CP0_HU3GE_BISR_BUSY                        ( BIT(19) )
 563 #define BIT_PD_CP0_SYS_BISR_BUSY                          ( BIT(18) )
 564 #define BIT_PD_MM_TOP_BISR_BUSY                           ( BIT(17) )
 565 #define BIT_PD_GPU_TOP_BISR_BUSY                          ( BIT(16) )
 566 #define BIT_PD_CP1_TD_BISR_FORCE_EN                       ( BIT(13) )
 567 #define BIT_PD_CP1_SYS_BISR_FORCE_EN                      ( BIT(12) )
 568 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN                    ( BIT(11) )
 569 #define BIT_PD_CP0_SYS_BISR_FORCE_EN                      ( BIT(10) )
 570 #define BIT_PD_MM_TOP_BISR_FORCE_EN                       ( BIT(9) )
 571 #define BIT_PD_GPU_TOP_BISR_FORCE_EN                      ( BIT(8) )
 572 #define BIT_PD_CP1_TD_BISR_FORCE_BYP                      ( BIT(5) )
 573 #define BIT_PD_CP1_SYS_BISR_FORCE_BYP                     ( BIT(4) )
 574 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP                   ( BIT(3) )
 575 #define BIT_PD_CP0_SYS_BISR_FORCE_BYP                     ( BIT(2) )
 576 #define BIT_PD_MM_TOP_BISR_FORCE_BYP                      ( BIT(1) )
 577 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP                     ( BIT(0) )
 578
 579 /* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
 580 #define BIT_CGM_208M_AP_AUTO_GATE_EN                      ( BIT(20) )
 581 #define BIT_CGM_12M_AP_AUTO_GATE_EN                       ( BIT(19) )
 582 #define BIT_CGM_24M_AP_AUTO_GATE_EN                       ( BIT(18) )
 583 #define BIT_CGM_48M_AP_AUTO_GATE_EN                       ( BIT(17) )
 584 #define BIT_CGM_51M2_AP_AUTO_GATE_EN                      ( BIT(16) )
 585 #define BIT_CGM_64M_AP_AUTO_GATE_EN                       ( BIT(15) )
 586 #define BIT_CGM_76M8_AP_AUTO_GATE_EN                      ( BIT(14) )
 587 #define BIT_CGM_96M_AP_AUTO_GATE_EN                       ( BIT(13) )
 588 #define BIT_CGM_128M_AP_AUTO_GATE_EN                      ( BIT(12) )
 589 #define BIT_CGM_153M6_AP_AUTO_GATE_EN                     ( BIT(11) )
 590 #define BIT_CGM_192M_AP_AUTO_GATE_EN                      ( BIT(10) )
 591 #define BIT_CGM_256M_AP_AUTO_GATE_EN                      ( BIT(9) )
 592 #define BIT_CGM_384M_AP_AUTO_GATE_EN                      ( BIT(8) )
 593 #define BIT_CGM_312M_AP_AUTO_GATE_EN                      ( BIT(7) )
 594 #define BIT_CGM_MPLL_AP_AUTO_GATE_EN                      ( BIT(6) )
 595 #define BIT_CGM_WPLL_AP_AUTO_GATE_EN                      ( BIT(5) )
 596 #define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN                  ( BIT(4) )
 597 #define BIT_CGM_TDPLL_AP_AUTO_GATE_EN                     ( BIT(3) )
 598 #define BIT_CGM_CPLL_AP_AUTO_GATE_EN                      ( BIT(2) )
 599 #define BIT_CGM_DPLL_AP_AUTO_GATE_EN                      ( BIT(1) )
 600 #define BIT_CGM_26M_AP_AUTO_GATE_EN                       ( BIT(0) )
 601
 602 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
 603 #define BIT_CGM_12M_MM_AUTO_GATE_EN                       ( BIT(26) )
 604 #define BIT_CGM_24M_MM_AUTO_GATE_EN                       ( BIT(25) )
 605 #define BIT_CGM_48M_MM_AUTO_GATE_EN                       ( BIT(24) )
 606 #define BIT_CGM_64M_MM_AUTO_GATE_EN                       ( BIT(23) )
 607 #define BIT_CGM_76M8_MM_AUTO_GATE_EN                      ( BIT(22) )
 608 #define BIT_CGM_96M_MM_AUTO_GATE_EN                       ( BIT(21) )
 609 #define BIT_CGM_128M_MM_AUTO_GATE_EN                      ( BIT(20) )
 610 #define BIT_CGM_153M6_MM_AUTO_GATE_EN                     ( BIT(19) )
 611 #define BIT_CGM_192M_MM_AUTO_GATE_EN                      ( BIT(18) )
 612 #define BIT_CGM_256M_MM_AUTO_GATE_EN                      ( BIT(17) )
 613 #define BIT_CGM_26M_MM_AUTO_GATE_EN                       ( BIT(16) )
 614 #define BIT_CGM_256M_GPU_AUTO_GATE_EN                     ( BIT(3) )
 615 #define BIT_CGM_208M_GPU_AUTO_GATE_EN                     ( BIT(2) )
 616 #define BIT_CGM_312M_GPU_AUTO_GATE_EN                     ( BIT(1) )
 617 #define BIT_CGM_300M_GPU_AUTO_GATE_EN                     ( BIT(0) )
 618
 619 /* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
 620 #define BIT_CGM_384M_CP0_AUTO_GATE_EN                     ( BIT(15) )
 621 #define BIT_CGM_256M_CP0_AUTO_GATE_EN                     ( BIT(14) )
 622 #define BIT_CGM_460M8_CP0W_AUTO_GATE_EN                   ( BIT(13) )
 623 #define BIT_CGM_307M2_CP0W_AUTO_GATE_EN                   ( BIT(12) )
 624 #define BIT_CGM_51M2_CP0W_AUTO_GATE_EN                    ( BIT(11) )
 625 #define BIT_CGM_76M8_CP0W_AUTO_GATE_EN                    ( BIT(10) )
 626 #define BIT_CGM_102M4_CP0W_AUTO_GATE_EN                   ( BIT(9) )
 627 #define BIT_CGM_192M_CP0_AUTO_GATE_EN                     ( BIT(8) )
 628 #define BIT_CGM_51M2_CP0_AUTO_GATE_EN                     ( BIT(7) )
 629 #define BIT_CGM_76M8_CP0_AUTO_GATE_EN                     ( BIT(6) )
 630 #define BIT_CGM_153M6_CP0_AUTO_GATE_EN                    ( BIT(5) )
 631 #define BIT_CGM_48M_CP0_AUTO_GATE_EN                      ( BIT(4) )
 632 #define BIT_CGM_64M_CP0_AUTO_GATE_EN                      ( BIT(3) )
 633 #define BIT_CGM_96M_CP0_AUTO_GATE_EN                      ( BIT(2) )
 634 #define BIT_CGM_128M_CP0_AUTO_GATE_EN                     ( BIT(1) )
 635 #define BIT_CGM_26M_CP0_AUTO_GATE_EN                      ( BIT(0) )
 636
 637 /* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
 638 #define BIT_CGM_312M_CP1_AUTO_GATE_EN                     ( BIT(10) )
 639 #define BIT_CGM_256M_CP1_AUTO_GATE_EN                     ( BIT(9) )
 640 #define BIT_CGM_192M_CP1_AUTO_GATE_EN                     ( BIT(8) )
 641 #define BIT_CGM_51M2_CP1_AUTO_GATE_EN                     ( BIT(7) )
 642 #define BIT_CGM_76M8_CP1_AUTO_GATE_EN                     ( BIT(6) )
 643 #define BIT_CGM_153M6_CP1_AUTO_GATE_EN                    ( BIT(5) )
 644 #define BIT_CGM_48M_CP1_AUTO_GATE_EN                      ( BIT(4) )
 645 #define BIT_CGM_96M_CP1_AUTO_GATE_EN                      ( BIT(3) )
 646 #define BIT_CGM_64M_CP1_AUTO_GATE_EN                      ( BIT(2) )
 647 #define BIT_CGM_128M_CP1_AUTO_GATE_EN                     ( BIT(1) )
 648 #define BIT_CGM_26M_CP1_AUTO_GATE_EN                      ( BIT(0) )
 649
 650 /* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
 651 #define BIT_CGM_76M8_CP2_AUTO_GATE_EN                     ( BIT(12) )
 652 #define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN                   ( BIT(11) )
 653 #define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN                   ( BIT(10) )
 654 #define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN                  ( BIT(9) )
 655 #define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN                  ( BIT(8) )
 656 #define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN                   ( BIT(7) )
 657 #define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN                   ( BIT(6) )
 658 #define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN                   ( BIT(5) )
 659 #define BIT_CGM_256M_CP2_AUTO_GATE_EN                     ( BIT(4) )
 660 #define BIT_CGM_104M_CP2_AUTO_GATE_EN                     ( BIT(3) )
 661 #define BIT_CGM_208M_CP2_AUTO_GATE_EN                     ( BIT(2) )
 662 #define BIT_CGM_312M_CP2_AUTO_GATE_EN                     ( BIT(1) )
 663 #define BIT_CGM_26M_CP2_AUTO_GATE_EN                      ( BIT(0) )
 664
 665 /* bits definitions for register REG_PMU_APB_CGM_AP_EN */
 666 #define BIT_CGM_208M_AP_EN                                ( BIT(20) )
 667 #define BIT_CGM_12M_AP_EN                                 ( BIT(19) )
 668 #define BIT_CGM_24M_AP_EN                                 ( BIT(18) )
 669 #define BIT_CGM_48M_AP_EN                                 ( BIT(17) )
 670 #define BIT_CGM_51M2_AP_EN                                ( BIT(16) )
 671 #define BIT_CGM_64M_AP_EN                                 ( BIT(15) )
 672 #define BIT_CGM_76M8_AP_EN                                ( BIT(14) )
 673 #define BIT_CGM_96M_AP_EN                                 ( BIT(13) )
 674 #define BIT_CGM_128M_AP_EN                                ( BIT(12) )
 675 #define BIT_CGM_153M6_AP_EN                               ( BIT(11) )
 676 #define BIT_CGM_192M_AP_EN                                ( BIT(10) )
 677 #define BIT_CGM_256M_AP_EN                                ( BIT(9) )
 678 #define BIT_CGM_384M_AP_EN                                ( BIT(8) )
 679 #define BIT_CGM_312M_AP_EN                                ( BIT(7) )
 680 #define BIT_CGM_MPLL_AP_EN                                ( BIT(6) )
 681 #define BIT_CGM_WPLL_AP_EN                                ( BIT(5) )
 682 #define BIT_CGM_WIFIPLL1_AP_EN                            ( BIT(4) )
 683 #define BIT_CGM_TDPLL_AP_EN                               ( BIT(3) )
 684 #define BIT_CGM_CPLL_AP_EN                                ( BIT(2) )
 685 #define BIT_CGM_DPLL_AP_EN                                ( BIT(1) )
 686 #define BIT_CGM_26M_AP_EN                                 ( BIT(0) )
 687
 688 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
 689 #define BIT_CGM_12M_MM_EN                                 ( BIT(26) )
 690 #define BIT_CGM_24M_MM_EN                                 ( BIT(25) )
 691 #define BIT_CGM_48M_MM_EN                                 ( BIT(24) )
 692 #define BIT_CGM_64M_MM_EN                                 ( BIT(23) )
 693 #define BIT_CGM_76M8_MM_EN                                ( BIT(22) )
 694 #define BIT_CGM_96M_MM_EN                                 ( BIT(21) )
 695 #define BIT_CGM_128M_MM_EN                                ( BIT(20) )
 696 #define BIT_CGM_153M6_MM_EN                               ( BIT(19) )
 697 #define BIT_CGM_192M_MM_EN                                ( BIT(18) )
 698 #define BIT_CGM_256M_MM_EN                                ( BIT(17) )
 699 #define BIT_CGM_26M_MM_EN                                 ( BIT(16) )
 700 #define BIT_CGM_256M_GPU_EN                               ( BIT(3) )
 701 #define BIT_CGM_208M_GPU_EN                               ( BIT(2) )
 702 #define BIT_CGM_312M_GPU_EN                               ( BIT(1) )
 703 #define BIT_CGM_300M_GPU_EN                               ( BIT(0) )
 704
 705 /* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
 706 #define BIT_CGM_384M_CP0_EN                               ( BIT(15) )
 707 #define BIT_CGM_256M_CP0_EN                               ( BIT(14) )
 708 #define BIT_CGM_460M8_CP0W_EN                             ( BIT(13) )
 709 #define BIT_CGM_307M2_CP0W_EN                             ( BIT(12) )
 710 #define BIT_CGM_51M2_CP0W_EN                              ( BIT(11) )
 711 #define BIT_CGM_76M8_CP0W_EN                              ( BIT(10) )
 712 #define BIT_CGM_102M4_CP0W_EN                             ( BIT(9) )
 713 #define BIT_CGM_192M_CP0_EN                               ( BIT(8) )
 714 #define BIT_CGM_51M2_CP0_EN                               ( BIT(7) )
 715 #define BIT_CGM_76M8_CP0_EN                               ( BIT(6) )
 716 #define BIT_CGM_153M6_CP0_EN                              ( BIT(5) )
 717 #define BIT_CGM_48M_CP0_EN                                ( BIT(4) )
 718 #define BIT_CGM_64M_CP0_EN                                ( BIT(3) )
 719 #define BIT_CGM_96M_CP0_EN                                ( BIT(2) )
 720 #define BIT_CGM_128M_CP0_EN                               ( BIT(1) )
 721 #define BIT_CGM_26M_CP0_EN                                ( BIT(0) )
 722
 723 /* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
 724 #define BIT_CGM_312M_CP1_EN                               ( BIT(10) )
 725 #define BIT_CGM_256M_CP1_EN                               ( BIT(9) )
 726 #define BIT_CGM_192M_CP1_EN                               ( BIT(8) )
 727 #define BIT_CGM_51M2_CP1_EN                               ( BIT(7) )
 728 #define BIT_CGM_76M8_CP1_EN                               ( BIT(6) )
 729 #define BIT_CGM_153M6_CP1_EN                              ( BIT(5) )
 730 #define BIT_CGM_48M_CP1_EN                                ( BIT(4) )
 731 #define BIT_CGM_96M_CP1_EN                                ( BIT(3) )
 732 #define BIT_CGM_64M_CP1_EN                                ( BIT(2) )
 733 #define BIT_CGM_128M_CP1_EN                               ( BIT(1) )
 734 #define BIT_CGM_26M_CP1_EN                                ( BIT(0) )
 735
 736 /* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
 737 #define BIT_CGM_76M8_CP2_EN                               ( BIT(12) )
 738 #define BIT_CGM_20M_CP2WF2_EN                             ( BIT(11) )
 739 #define BIT_CGM_80M_CP2WF2_EN                             ( BIT(10) )
 740 #define BIT_CGM_120M_CP2WF2_EN                            ( BIT(9) )
 741 #define BIT_CGM_160M_CP2WF2_EN                            ( BIT(8) )
 742 #define BIT_CGM_20M_CP2WF1_EN                             ( BIT(7) )
 743 #define BIT_CGM_44M_CP2WF1_EN                             ( BIT(6) )
 744 #define BIT_CGM_80M_CP2WF1_EN                             ( BIT(5) )
 745 #define BIT_CGM_256M_CP2_EN                               ( BIT(4) )
 746 #define BIT_CGM_104M_CP2_EN                               ( BIT(3) )
 747 #define BIT_CGM_208M_CP2_EN                               ( BIT(2) )
 748 #define BIT_CGM_312M_CP2_EN                               ( BIT(1) )
 749 #define BIT_CGM_26M_CP2_EN                                ( BIT(0) )
 750
 751 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
 752 #define BIT_DDR_PHY_ISO_RST_EN                            ( BIT(26) )
 753 #define BIT_DDR_UMCTL_RET_EN                              ( BIT(25) )
 754 #define BIT_DDR_PHY_AUTO_RET_EN                           ( BIT(24) )
 755 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 756 #define BITS_DDR_OPERATE_MODE(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
 757 #define BITS_DDR_OPERATE_MODE_IDLE(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
 758
 759 /* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
 760 #define BIT_DDR_UMCTL_SOFT_RST                            ( BIT(16) )
 761 #define BIT_DDR_PHY_RET_EN                                ( BIT(0) )
 762
 763 #endif