arch/arm/include/asm/arch-sc8830/chip_x15/__regs_mm_ahb_rf.h

   1 /*
   2  * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  */
  10
  11 //#ifndef __SCI_GLB_REGS_H__
  12 //#error  "Don't include this file directly, Pls include sci_glb_regs.h"
  13 //#endif
  14
  15
  16 #ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__
  17 #define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__
  18
  19 #define REGS_MM_AHB
  20
  21 /* registers definitions for MM_AHB_RF */
  22 #define REG_MM_AHB_AHB_EB                              SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)
  23 #define REG_MM_AHB_AHB_RST                             SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)
  24 #define REG_MM_AHB_GEN_CKG_CFG                         SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)
  25
  26
  27
  28 /* bits definitions for register REG_MM_AHB_RF_AHB_EB */
  29 #define BIT_MMU_EB                                        ( BIT(7) )
  30 #define BIT_MM_CKG_EB                                        ( BIT(6) )
  31 #define BIT_JPG_EB                                        ( BIT(5) )
  32 #define BIT_CSI_EB                                        ( BIT(4) )
  33 #define BIT_VSP_EB                                        ( BIT(3) )
  34 #define BIT_ISP_EB                                        ( BIT(2) )
  35 #define BIT_CCIR_EB                                       ( BIT(1) )
  36 #define BIT_DCAM_EB                                       ( BIT(0) )
  37
  38 /* bits definitions for register REG_MM_AHB_RF_AHB_RST */
  39 #define BIT_MMU_SOFT_RST                                  ( BIT(14) )
  40 #define BIT_MM_CKG_SOFT_RST                                  ( BIT(13) )
  41 #define BIT_MM_MTX_SOFT_RST                               ( BIT(12) )
  42 #define BIT_OR1200_SOFT_RST                               ( BIT(11) )
  43 #define BIT_ROT_SOFT_RST                                  ( BIT(10) )
  44 #define BIT_CAM2_SOFT_RST                                 ( BIT(9) )
  45 #define BIT_CAM1_SOFT_RST                                 ( BIT(8) )
  46 #define BIT_CAM0_SOFT_RST                                 ( BIT(7) )
  47 #define BIT_JPG_SOFT_RST                                  ( BIT(6) )
  48 #define BIT_CSI_SOFT_RST                                  ( BIT(5) )
  49 #define BIT_VSP_SOFT_RST                                  ( BIT(4) )
  50 #define BIT_ISP_CFG_SOFT_RST                              ( BIT(3) )
  51 #define BIT_ISP_LOG_SOFT_RST                              ( BIT(2) )
  52 #define BIT_CCIR_SOFT_RST                                 ( BIT(1) )
  53 #define BIT_DCAM_SOFT_RST                                 ( BIT(0) )
  54
  55 /* bits definitions for register REG_MM_AHB_RF_GEN_CKG_CFG */
  56 #define BIT_MM_MTX_AXI_CKG_EN                             ( BIT(8) )
  57 #define BIT_MM_AXI_CKG_EN                                 ( BIT(7) )
  58 #define BIT_JPG_AXI_CKG_EN                                ( BIT(6) )
  59 #define BIT_VSP_AXI_CKG_EN                                ( BIT(5) )
  60 #define BIT_ISP_AXI_CKG_EN                                ( BIT(4) )
  61 #define BIT_DCAM_AXI_CKG_EN                               ( BIT(3) )
  62 #define BIT_SENSOR_CKG_EN                                 ( BIT(2) )
  63 #define BIT_MIPI_CSI_CKG_EN                               ( BIT(1) )
  64 #define BIT_CPHY_CFG_CKG_EN                               ( BIT(0) )
  65
  66 #endif