2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
16 #ifndef __H_REGS_APB_IF_HEADFILE_H__
17 #define __H_REGS_APB_IF_HEADFILE_H__ __FILE__
21 /* registers definitions for APB_IF */
22 #define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0000)
23 #define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0004)
24 #define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0008)
25 #define ANA_REG_GLB_ARM_RST SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x000C)
26 #define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0010)
27 #define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0014)
28 #define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0018)
29 #define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x001C)
30 #define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0020)
31 #define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0024)
32 #define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0028)
33 #define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x002C)
34 #define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0030)
35 #define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0034)
36 #define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0038)
37 #define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x003C)
38 #define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0040)
39 #define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0044)
40 #define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0048)
41 #define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x004C)
42 #define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0050)
43 #define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0054)
44 #define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0058)
45 #define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x005C)
46 #define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0060)
47 #define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0064)
48 #define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0068)
49 #define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x006C)
50 #define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0070)
51 #define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0074)
52 #define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0078)
53 #define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x007C)
54 #define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0080)
55 #define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0084)
56 #define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0088)
57 #define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x008C)
58 #define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0090)
59 #define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0094)
60 #define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0098)
61 #define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x009C)
62 #define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A0)
63 #define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A4)
64 #define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A8)
65 #define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00AC)
66 #define ANA_REG_GLB_RTC_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B0)
67 #define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B4)
68 #define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B8)
69 #define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00BC)
70 #define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C0)
71 #define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C4)
72 #define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C8)
73 #define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00CC)
74 #define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D0)
75 #define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D4)
76 #define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D8)
77 #define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00DC)
78 #define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E0)
79 #define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E4)
80 #define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E8)
81 #define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00EC)
82 #define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F0)
83 #define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F4)
84 #define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F8)
85 #define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00FC)
86 #define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0100)
87 #define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0104)
88 #define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0108)
89 #define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x010C)
90 #define ANA_REG_GLB_MIXED_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0110)
91 #define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0114)
92 #define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0118)
93 #define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x011C)
94 #define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0120)
95 #define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0124)
96 #define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0128)
97 #define ANA_REG_GLB_INT_GPI_DEBUG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x012C)
98 #define ANA_REG_GLB_HWRST_RTC SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0130)
99 #define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0134)
100 #define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0138)
101 #define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x013C)
102 #define ANA_REG_GLB_ARCH_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0140)
103 #define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0144)
104 #define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0148)
105 #define ANA_REG_GLB_BA_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x014C)
106 #define ANA_REG_GLB_BA_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0150)
107 #define ANA_REG_GLB_BA_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0154)
108 #define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0160)
109 #define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0164)
110 #define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0168)
111 #define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x016C)
112 #define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0174)
113 #define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x017C)
117 /* bits definitions for register REG_APB_IF_ARM_MODULE_EN */
118 #define BIT_ANA_TPC_EN ( BIT(10) )
119 #define BIT_ANA_PINREG_EN ( BIT(9) )
120 #define BIT_ANA_FGU_EN ( BIT(8) )
121 #define BIT_ANA_ADC_EN ( BIT(6) )
122 #define BIT_ANA_HDT_EN ( BIT(5) )
123 #define BIT_ANA_AUD_EN ( BIT(4) )
124 #define BIT_ANA_EIC_EN ( BIT(3) )
125 #define BIT_ANA_WDG_EN ( BIT(2) )
126 #define BIT_ANA_RTC_EN ( BIT(1) )
127 #define BIT_ANA_CAL_EN ( BIT(0) )
129 /* bits definitions for register REG_APB_IF_ARM_CLK_EN */
130 #define BIT_CLK_AUXAD_EN ( BIT(9) )
131 #define BIT_CLK_AUXADC_EN ( BIT(8) )
132 #define BITS_CLK_CAL_SRC_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
133 #define BIT_CLK_CAL_EN ( BIT(5) )
134 #define BIT_CLK_AUD_HID_EN ( BIT(4) )
135 #define BIT_CLK_AUD_HBD_EN ( BIT(3) )
136 #define BIT_CLK_AUD_LOOP_EN ( BIT(2) )
137 #define BIT_CLK_AUD_6P5M_EN ( BIT(1) )
138 #define BIT_CLK_AUDIF_EN ( BIT(0) )
140 /* bits definitions for register REG_APB_IF_RTC_CLK_EN */
141 #define BIT_RTC_FLASH_EN ( BIT(12) )
142 #define BIT_RTC_TPC_EN ( BIT(8) )
143 #define BIT_RTC_FGU_EN ( BIT(7) )
144 #define BIT_RTC_FGUA_EN ( BIT(6) )
145 #define BIT_RTC_VIBR_EN ( BIT(5) )
146 #define BIT_RTC_AUD_EN ( BIT(4) )
147 #define BIT_RTC_EIC_EN ( BIT(3) )
148 #define BIT_RTC_WDG_EN ( BIT(2) )
149 #define BIT_RTC_RTC_EN ( BIT(1) )
150 #define BIT_RTC_ARCH_EN ( BIT(0) )
152 /* bits definitions for register REG_APB_IF_ARM_RST */
153 #define BIT_ANA_TPC_SOFT_RST ( BIT(13) )
154 #define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) )
155 #define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) )
156 #define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) )
157 #define BIT_ANA_AUD_SOFT_RST ( BIT(9) )
158 #define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) )
159 #define BIT_ANA_ADC_SOFT_RST ( BIT(6) )
160 #define BIT_ANA_PWM0_SOFT_RST ( BIT(5) )
161 #define BIT_ANA_FGU_SOFT_RST ( BIT(4) )
162 #define BIT_ANA_EIC_SOFT_RST ( BIT(3) )
163 #define BIT_ANA_WDG_SOFT_RST ( BIT(2) )
164 #define BIT_ANA_RTC_SOFT_RST ( BIT(1) )
165 #define BIT_ANA_CAL_SOFT_RST ( BIT(0) )
167 /* bits definitions for register REG_APB_IF_LDO_DCDC_PD */
168 #define BIT_DCDC_TOP_CLKF_EN ( BIT(14) )
169 #define BIT_DCDC_TOP_OSC_EN ( BIT(13) )
170 #define BIT_DCDC_GEN_PD ( BIT(12) )
171 #define BIT_DCDC_MEM_PD ( BIT(11) )
172 #define BIT_DCDC_ARM_PD ( BIT(10) )
173 #define BIT_DCDC_CORE_PD ( BIT(9) )
174 #define BIT_LDO_RF0_PD ( BIT(8) )
175 #define BIT_LDO_EMMCCORE_PD ( BIT(7) )
176 #define BIT_LDO_EMMCIO_PD ( BIT(6) )
177 #define BIT_LDO_DCXO_PD ( BIT(5) )
178 #define BIT_LDO_CON_PD ( BIT(4) )
179 #define BIT_LDO_VDD25_PD ( BIT(3) )
180 #define BIT_LDO_VDD28_PD ( BIT(2) )
181 #define BIT_LDO_VDD18_PD ( BIT(1) )
182 #define BIT_BG_PD ( BIT(0) )
184 /* bits definitions for register REG_APB_IF_LDO_PD_CTRL */
185 #define BIT_LDO_LPREF_PD_SW ( BIT(11) )
186 #define BIT_DCDC_WPA_PD ( BIT(10) )
187 #define BIT_LDO_CLSG_PD ( BIT(9) )
188 #define BIT_LDO_USB_PD ( BIT(8) )
189 #define BIT_LDO_CAMMOT_PD ( BIT(7) )
190 #define BIT_LDO_CAMIO_PD ( BIT(6) )
191 #define BIT_LDO_CAMD_PD ( BIT(5) )
192 #define BIT_LDO_CAMA_PD ( BIT(4) )
193 #define BIT_LDO_SIM2_PD ( BIT(3) )
194 #define BIT_LDO_SIM1_PD ( BIT(2) )
195 #define BIT_LDO_SIM0_PD ( BIT(1) )
196 #define BIT_LDO_SD_PD ( BIT(0) )
198 /* bits definitions for register REG_APB_IF_LDO_V_CTRL0 */
199 #define BITS_LDO_RF0_V_18(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
200 #define BITS_LDO_RF0_V_28(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
202 /* bits definitions for register REG_APB_IF_LDO_V_CTRL1 */
203 #define BITS_LDO_CAMIO_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
204 #define BITS_LDO_CAMD_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
206 /* bits definitions for register REG_APB_IF_LDO_V_CTRL2 */
207 #define BITS_LDO_CLSG_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
208 #define BITS_LDO_EMMCIO_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
210 /* bits definitions for register REG_APB_IF_LDO_V_CTRL3 */
211 #define BITS_LDO_VDD25_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
212 #define BITS_LDO_VDD28_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
214 /* bits definitions for register REG_APB_IF_LDO_V_CTRL4 */
215 #define BITS_LDO_SIM0_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
216 #define BITS_LDO_SD_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
218 /* bits definitions for register REG_APB_IF_LDO_V_CTRL5 */
219 #define BITS_LDO_SIM2_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
220 #define BITS_LDO_SIM1_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
222 /* bits definitions for register REG_APB_IF_LDO_V_CTRL6 */
223 #define BITS_LDO_CON_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
224 #define BITS_LDO_CAMA_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
226 /* bits definitions for register REG_APB_IF_LDO_V_CTRL7 */
227 #define BITS_LDO_EMMCCORE_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
228 #define BITS_LDO_CAMMOT_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
230 /* bits definitions for register REG_APB_IF_LDO_V_CTRL8 */
231 #define BITS_LDO_DCXO_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
232 #define BITS_LDO_DCXO_LP_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
234 /* bits definitions for register REG_APB_IF_LDO_V_CTRL9 */
235 #define BIT_BONDOPT4 ( BIT(15) )
236 #define BITS_LDO_VDD18_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
237 #define BITS_LDO_USB_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
239 /* bits definitions for register REG_APB_IF_LDO_V_CTRL10 */
240 #define BITS_VBATBK_RES(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
241 #define BITS_VBATBK_V(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
242 #define BITS_LDOA_CAL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
243 #define BITS_LDOD_CAL_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
244 #define BITS_LDODCDC_CAL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
246 /* bits definitions for register REG_APB_IF_LDO_LP_CTRL */
247 #define BITS_LDOD_LP_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
248 #define BITS_LDOA_LP_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
249 #define BITS_LDODCDC_LP_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
251 /* bits definitions for register REG_APB_IF_DCDC_CTRL0 */
252 #define BITS_DCDC_CORE_DEADTIME(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
253 #define BITS_DCDC_CORE_STBOP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
254 #define BITS_DCDC_CORE_PDRSLOW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
255 #define BIT_DCDC_CORE_CL_CTRL ( BIT(3) )
256 #define BIT_DCDC_CORE_PFM ( BIT(2) )
257 #define BIT_DCDC_CORE_DCM ( BIT(1) )
258 #define BIT_DCDC_CORE_LP_EN ( BIT(0) )
260 /* bits definitions for register REG_APB_IF_DCDC_CTRL1 */
261 #define BITS_DCDC_MEM_DEADTIME(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
262 #define BITS_DCDC_MEM_STBOP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
263 #define BITS_DCDC_MEM_PDRSLOW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
264 #define BIT_DCDC_MEM_CL_CTRL ( BIT(3) )
265 #define BIT_DCDC_MEM_PFM ( BIT(2) )
266 #define BIT_DCDC_MEM_DCM ( BIT(1) )
267 #define BIT_DCDC_MEM_LP_EN ( BIT(0) )
269 /* bits definitions for register REG_APB_IF_DCDC_CTRL2 */
270 #define BITS_DCDC_GEN_DEADTIME(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
271 #define BITS_DCDC_GEN_STBOP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
272 #define BITS_DCDC_GEN_PDRSLOW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
273 #define BIT_DCDC_GEN_CL_CTRL ( BIT(3) )
274 #define BIT_DCDC_GEN_PFM ( BIT(2) )
275 #define BIT_DCDC_GEN_DCM ( BIT(1) )
276 #define BIT_DCDC_GEN_LP_EN ( BIT(0) )
278 /* bits definitions for register REG_APB_IF_DCDC_CTRL3 */
279 #define BITS_DCDC_ARM_DEADTIME(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
280 #define BITS_DCDC_ARM_STBOP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
281 #define BITS_DCDC_ARM_PDRSLOW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
282 #define BIT_DCDC_ARM_CL_CTRL ( BIT(3) )
283 #define BIT_DCDC_ARM_PFM ( BIT(2) )
284 #define BIT_DCDC_ARM_DCM ( BIT(1) )
285 #define BIT_DCDC_ARM_LP_EN ( BIT(0) )
287 /* bits definitions for register REG_APB_IF_DCDC_CTRL4 */
288 #define BITS_DCDC_WPA_DEADTIME(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
289 #define BITS_DCDC_WPA_STBOP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
290 #define BITS_DCDC_WPA_PDRSLOW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
291 #define BIT_DCDC_WPA_CL_CTRL ( BIT(3) )
292 #define BIT_DCDC_WPA_PFM ( BIT(2) )
293 #define BIT_DCDC_WPA_LP_EN ( BIT(0) )
295 /* bits definitions for register REG_APB_IF_DCDC_CTRL5 */
296 #define BIT_DCDC_WPA_ZXOP ( BIT(15) )
297 #define BIT_DCDC_WPA_APTEN ( BIT(14) )
298 #define BIT_DCDC_WPA_VOUTDOWN ( BIT(12) )
299 #define BIT_DCDC_ARM_VOUTDOWN ( BIT(11) )
300 #define BIT_DCDC_GEN_VOUTDOWN ( BIT(10) )
301 #define BIT_DCDC_MEM_VOUTDOWN ( BIT(9) )
302 #define BIT_DCDC_CORE_VOUTDOWN ( BIT(8) )
303 #define BIT_DCDC_TOP_SD_MODE ( BIT(4) )
304 #define BIT_DCDC_TOP_DELAYF ( BIT(3) )
305 #define BIT_DCDC_TOP_DELAY4 ( BIT(2) )
306 #define BIT_DCDC_CLK_SP_SEL ( BIT(1) )
307 #define BIT_DCDC_CLK_SP_EN ( BIT(0) )
309 /* bits definitions for register REG_APB_IF_DCDC_CTRL6 */
310 #define BITS_DCDC_TOP_CHNG_FRQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
312 /* bits definitions for register REG_APB_IF_DCDC_CTRL7 */
313 #define BITS_DCDC_TOP_CLKB_CAL_SW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
314 #define BITS_DCDC_TOP_CLKF_CAL_SW(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
315 #define BITS_DCDC_TOP_CLK4_CAL_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
317 /* bits definitions for register REG_APB_IF_DCDC_CTRL8 */
318 #define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) )
319 #define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) )
320 #define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) )
321 #define BITS_DCDC_CORE_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
322 #define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) )
323 #define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) )
324 #define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) )
325 #define BITS_DCDC_ARM_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
327 /* bits definitions for register REG_APB_IF_DCDC_CTRL9 */
328 #define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) )
329 #define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) )
330 #define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) )
331 #define BITS_DCDC_MEM_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
332 #define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) )
333 #define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) )
334 #define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) )
335 #define BITS_DCDC_GEN_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
337 /* bits definitions for register REG_APB_IF_DCDC_CTRL10 */
338 #define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) )
339 #define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) )
340 #define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) )
341 #define BITS_DCDC_WPA_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
342 #define BIT_DCDC_TOP_OSCSYCEN_SW ( BIT(7) )
343 #define BIT_DCDC_TOP_OSCSYCEN_HW_EN ( BIT(6) )
344 #define BIT_DCDC_TOP_OSCSYC_DIV_EN ( BIT(5) )
345 #define BITS_DCDC_TOP_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
347 /* bits definitions for register REG_APB_IF_SLP_WAIT_DCDCARM */
348 #define BITS_SLP_IN_WAIT_DCDCARM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
349 #define BITS_SLP_OUT_WAIT_DCDCARM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
351 /* bits definitions for register REG_APB_IF_PWR_SLP_CTRL0 */
352 #define BIT_SLP_IO_EN ( BIT(15) )
353 #define BIT_SLP_DCDCGEN_PD_EN ( BIT(10) )
354 #define BIT_SLP_DCDCWPA_PD_EN ( BIT(9) )
355 #define BIT_SLP_DCDCARM_PD_EN ( BIT(8) )
356 #define BIT_SLP_LDORF0_PD_EN ( BIT(7) )
357 #define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) )
358 #define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(5) )
359 #define BIT_SLP_LDODCXO_PD_EN ( BIT(4) )
360 #define BIT_SLP_LDOCON_PD_EN ( BIT(3) )
361 #define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) )
362 #define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) )
363 #define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) )
365 /* bits definitions for register REG_APB_IF_PWR_SLP_CTRL1 */
366 #define BIT_SLP_LDO_PD_EN ( BIT(11) )
367 #define BIT_SLP_LDOLPREF_PD_EN ( BIT(10) )
368 #define BIT_SLP_LDOCLSG_PD_EN ( BIT(9) )
369 #define BIT_SLP_LDOUSB_PD_EN ( BIT(8) )
370 #define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) )
371 #define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) )
372 #define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) )
373 #define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) )
374 #define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) )
375 #define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) )
376 #define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) )
377 #define BIT_SLP_LDOSD_PD_EN ( BIT(0) )
379 /* bits definitions for register REG_APB_IF_PWR_SLP_CTRL2 */
380 #define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) )
381 #define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) )
382 #define BIT_SLP_DCDCARM_LP_EN ( BIT(10) )
383 #define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) )
384 #define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) )
385 #define BIT_SLP_LDORF0_LP_EN ( BIT(7) )
386 #define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) )
387 #define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(5) )
388 #define BIT_SLP_LDODCXO_LP_EN ( BIT(4) )
389 #define BIT_SLP_LDOCON_LP_EN ( BIT(3) )
390 #define BIT_SLP_LDOVDD25_LP_EN ( BIT(2) )
391 #define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) )
392 #define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) )
394 /* bits definitions for register REG_APB_IF_PWR_SLP_CTRL3 */
395 #define BIT_SLP_BG_LP_EN ( BIT(15) )
396 #define BIT_SLP_LDOCLSG_LP_EN ( BIT(9) )
397 #define BIT_SLP_LDOUSB_LP_EN ( BIT(8) )
398 #define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) )
399 #define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) )
400 #define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) )
401 #define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) )
402 #define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) )
403 #define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) )
404 #define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) )
405 #define BIT_SLP_LDOSD_LP_EN ( BIT(0) )
407 /* bits definitions for register REG_APB_IF_AUD_SLP_CTRL */
408 #define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(10) )
409 #define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(9) )
410 #define BIT_SLP_AUD_PA_PD_EN ( BIT(8) )
411 #define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(7) )
412 #define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(6) )
413 #define BIT_SLP_AUD_VB_PD_EN ( BIT(5) )
414 #define BIT_SLP_AUD_VBO_PD_EN ( BIT(4) )
415 #define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(3) )
416 #define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) )
417 #define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) )
418 #define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) )
420 /* bits definitions for register REG_APB_IF_DCDC_SLP_CTRL0 */
421 #define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
422 #define BITS_DCDC_CORE_CTL_DS_SW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
423 #define BIT_PWR_OFF_SEQ_EN ( BIT(3) )
424 #define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) )
425 #define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) )
427 /* bits definitions for register REG_APB_IF_DCDC_SLP_CTRL1 */
428 #define BITS_DCDC_CORE_CAL_SLP_STEP2(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
429 #define BITS_DCDC_CORE_CTL_SLP_STEP2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
430 #define BITS_DCDC_CORE_CAL_SLP_STEP1(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
431 #define BITS_DCDC_CORE_CTL_SLP_STEP1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
433 /* bits definitions for register REG_APB_IF_DCDC_SLP_CTRL2 */
434 #define BITS_DCDC_CORE_CAL_SLP_STEP4(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
435 #define BITS_DCDC_CORE_CTL_SLP_STEP4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
436 #define BITS_DCDC_CORE_CAL_SLP_STEP3(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
437 #define BITS_DCDC_CORE_CTL_SLP_STEP3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
439 /* bits definitions for register REG_APB_IF_DCDC_SLP_CTRL3 */
440 #define BITS_DCDC_CORE_CAL_SLP_STEP5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
441 #define BITS_DCDC_CORE_CTL_SLP_STEP5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
443 /* bits definitions for register REG_APB_IF_PWR_XTL_EN0 */
444 #define BIT_LDO_XTL_EN ( BIT(15) )
445 #define BIT_LDO_DCXO_EXT_XTL1_EN ( BIT(11) )
446 #define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(10) )
447 #define BIT_LDO_DCXO_XTL2_EN ( BIT(9) )
448 #define BIT_LDO_DCXO_XTL0_EN ( BIT(8) )
449 #define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(7) )
450 #define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(6) )
451 #define BIT_LDO_VDD18_XTL2_EN ( BIT(5) )
452 #define BIT_LDO_VDD18_XTL0_EN ( BIT(4) )
453 #define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(3) )
454 #define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) )
455 #define BIT_LDO_VDD28_XTL2_EN ( BIT(1) )
456 #define BIT_LDO_VDD28_XTL0_EN ( BIT(0) )
458 /* bits definitions for register REG_APB_IF_PWR_XTL_EN1 */
459 #define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(11) )
460 #define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(10) )
461 #define BIT_LDO_RF0_XTL2_EN ( BIT(9) )
462 #define BIT_LDO_RF0_XTL0_EN ( BIT(8) )
463 #define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(7) )
464 #define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(6) )
465 #define BIT_LDO_VDD25_XTL2_EN ( BIT(5) )
466 #define BIT_LDO_VDD25_XTL0_EN ( BIT(4) )
467 #define BIT_LDO_CON_EXT_XTL1_EN ( BIT(3) )
468 #define BIT_LDO_CON_EXT_XTL0_EN ( BIT(2) )
469 #define BIT_LDO_CON_XTL2_EN ( BIT(1) )
470 #define BIT_LDO_CON_XTL0_EN ( BIT(0) )
472 /* bits definitions for register REG_APB_IF_PWR_XTL_EN2 */
473 #define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(11) )
474 #define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(10) )
475 #define BIT_LDO_SIM2_XTL2_EN ( BIT(9) )
476 #define BIT_LDO_SIM2_XTL0_EN ( BIT(8) )
477 #define BIT_LDO_SIM1_EXT_XTL1_EN ( BIT(7) )
478 #define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(6) )
479 #define BIT_LDO_SIM1_XTL2_EN ( BIT(5) )
480 #define BIT_LDO_SIM1_XTL0_EN ( BIT(4) )
481 #define BIT_LDO_SIM0_EXT_XTL1_EN ( BIT(3) )
482 #define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) )
483 #define BIT_LDO_SIM0_XTL2_EN ( BIT(1) )
484 #define BIT_LDO_SIM0_XTL0_EN ( BIT(0) )
486 /* bits definitions for register REG_APB_IF_PWR_XTL_EN3 */
487 #define BIT_XO_EXT_XTL1_EN ( BIT(7) )
488 #define BIT_XO_EXT_XTL0_EN ( BIT(6) )
489 #define BIT_XO_XTL2_EN ( BIT(5) )
490 #define BIT_XO_XTL0_EN ( BIT(4) )
491 #define BIT_BG_EXT_XTL1_EN ( BIT(3) )
492 #define BIT_BG_EXT_XTL0_EN ( BIT(2) )
493 #define BIT_BG_XTL2_EN ( BIT(1) )
494 #define BIT_BG_XTL0_EN ( BIT(0) )
496 /* bits definitions for register REG_APB_IF_PWR_XTL_EN4 */
497 #define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(15) )
498 #define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(14) )
499 #define BIT_DCDC_WPA_XTL2_EN ( BIT(13) )
500 #define BIT_DCDC_WPA_XTL0_EN ( BIT(12) )
501 #define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(11) )
502 #define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(10) )
503 #define BIT_DCDC_MEM_XTL2_EN ( BIT(9) )
504 #define BIT_DCDC_MEM_XTL0_EN ( BIT(8) )
505 #define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(7) )
506 #define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(6) )
507 #define BIT_DCDC_GEN_XTL2_EN ( BIT(5) )
508 #define BIT_DCDC_GEN_XTL0_EN ( BIT(4) )
509 #define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(3) )
510 #define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) )
511 #define BIT_DCDC_CORE_XTL2_EN ( BIT(1) )
512 #define BIT_DCDC_CORE_XTL0_EN ( BIT(0) )
514 /* bits definitions for register REG_APB_IF_RTC_CTRL */
515 #define BITS_XOSC32K_CTL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
517 /* bits definitions for register REG_APB_IF_32KLESS_CTRL0 */
518 #define BIT_BONDOPT3 ( BIT(15) )
519 #define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) )
520 #define BIT_XO_LOW_CUR_FLAG ( BIT(13) )
521 #define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) )
522 #define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) )
523 #define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) )
524 #define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) )
525 #define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) )
526 #define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) )
527 #define BIT_XO_LOW_CUR_EN ( BIT(4) )
528 #define BIT_XO_LOW_CUR_FRC ( BIT(3) )
529 #define BIT_EXT_32K_PD ( BIT(2) )
530 #define BIT_RC_32K_SEL ( BIT(1) )
531 #define BIT_RC_32K_EN ( BIT(0) )
533 /* bits definitions for register REG_APB_IF_32KLESS_CTRL1 */
534 #define BITS_RC_MODE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
536 /* bits definitions for register REG_APB_IF_32KLESS_CTRL2 */
537 #define BITS_XO_LOW_CUR_CNT_LOW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
539 /* bits definitions for register REG_APB_IF_32KLESS_CTRL3 */
540 #define BITS_XO_LOW_CUR_CNT_HIGH(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
542 /* bits definitions for register REG_APB_IF_AUXAD_CTL */
543 #define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) )
544 #define BIT_AUXAD_CURRENTSEL ( BIT(5) )
545 #define BITS_AUXAD_CURRENT_IBS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
547 /* bits definitions for register REG_APB_IF_DDR2_CTRL */
548 #define BITS_DDR2_BUF_S_DS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
549 #define BITS_DDR2_BUF_CHNS_DS(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
550 #define BIT_DDR2_BUF_PD_HW ( BIT(5) )
551 #define BIT_DDR2_BUF_PD ( BIT(4) )
552 #define BITS_DDR2_BUF_S(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
553 #define BITS_DDR2_BUF_CHNS(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
555 /* bits definitions for register REG_APB_IF_XTL_WAIT_CTRL */
556 #define BIT_SLP_XTLBUF_PD_EN ( BIT(9) )
557 #define BIT_XTL_EN ( BIT(8) )
558 #define BITS_XTL_WAIT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
560 /* bits definitions for register REG_APB_IF_FLASH_CTRL */
561 #define BIT_FLASH_PON ( BIT(15) )
562 #define BIT_FLASH_V_HW_EN ( BIT(6) )
563 #define BITS_FLASH_V_HW_STEP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
564 #define BITS_FLASH_V_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
566 /* bits definitions for register REG_APB_IF_WHTLED_CTRL0 */
567 #define BITS_WHTLED_DC(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
568 #define BIT_WHTLED_BOOST_EN ( BIT(8) )
569 #define BIT_WHTLED_SERIES_EN ( BIT(7) )
570 #define BITS_WHTLED_V(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
571 #define BIT_WHTLED_PD ( BIT(0) )
573 /* bits definitions for register REG_APB_IF_WHTLED_CTRL1 */
574 #define BIT_RTC_PWM0_EN ( BIT(15) )
575 #define BIT_PWM0_EN ( BIT(14) )
576 #define BITS_WHTLED_ISET(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
577 #define BITS_WHTLED_CLMIT_OP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
578 #define BITS_WHTLED_FRE_AD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
580 /* bits definitions for register REG_APB_IF_WHTLED_CTRL2 */
581 #define BIT_WHTLED_EXT_RES_CTRL ( BIT(15) )
582 #define BIT_WHTLED_PD_SEL ( BIT(14) )
583 #define BIT_WHTLED_DIS_OVST ( BIT(13) )
584 #define BIT_WHTLED_DIM_SEL ( BIT(12) )
585 #define BIT_WHTLED_DE_BIAS ( BIT(11) )
586 #define BIT_WHTLED_BUFF_SHT ( BIT(10) )
587 #define BITS_WHTLED_STB_OP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
588 #define BIT_WHTLED_CAP_OPTION ( BIT(7) )
589 #define BIT_WHTLED_OVP_DIS ( BIT(6) )
590 #define BITS_WHTLED_REF_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
592 /* bits definitions for register REG_APB_IF_KPLED_CTRL */
593 #define BITS_KPLED_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
594 #define BIT_KPLED_PD ( BIT(0) )
596 /* bits definitions for register REG_APB_IF_VIBR_CTRL0 */
597 #define BITS_VIBR_STABLE_V_HW(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
598 #define BITS_VIBR_INIT_V_HW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
599 #define BITS_VIBR_V_SW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
600 #define BIT_VIBR_PON ( BIT(1) )
601 #define BIT_VIBR_SW_EN ( BIT(0) )
603 /* bits definitions for register REG_APB_IF_VIBR_CTRL1 */
604 #define BITS_VIBR_V_CONVERT_CNT_HW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
606 /* bits definitions for register REG_APB_IF_VIBR_CTRL2 */
607 #define BIT_VIBR_PWR_ON_STS ( BIT(15) )
608 #define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) )
609 #define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) )
611 /* bits definitions for register REG_APB_IF_VIBR_WR_PROT_VALUE */
612 #define BIT_VIBR_WR_PROT ( BIT(15) )
613 #define BITS_VIBR_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
615 /* bits definitions for register REG_APB_IF_AUDIO_CTRL0 */
616 #define BIT_AUD_SLP_APP_RST_EN ( BIT(15) )
617 #define BITS_CLK_AUD_HBD_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
618 #define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) )
619 #define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) )
620 #define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) )
621 #define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) )
622 #define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) )
624 /* bits definitions for register REG_APB_IF_AUDIO_CTRL1 */
625 #define BIT_HEAD_INSERT_EIC_EN ( BIT(6) )
626 #define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) )
627 #define BITS_AUDIO_CHP_CLK_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
629 /* bits definitions for register REG_APB_IF_CHGR_CTRL0 */
630 #define BITS_CHGR_CV_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
631 #define BITS_CHGR_END_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
632 #define BIT_CHGR_PD ( BIT(0) )
634 /* bits definitions for register REG_APB_IF_CHGR_CTRL1 */
635 #define BITS_CHGR_CC_I(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
636 #define BITS_VBAT_OVP_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
637 #define BITS_VCHG_OVP_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
639 /* bits definitions for register REG_APB_IF_CHGR_CTRL2 */
640 #define BIT_CHGR_INT_EN ( BIT(15) )
641 #define BIT_CHGR_DRV ( BIT(7) )
642 #define BIT_CHGR_OSC ( BIT(6) )
643 #define BITS_CHGR_DPM(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
644 #define BITS_CHGR_ITERM(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
645 #define BIT_CHGR_CC_EN ( BIT(1) )
646 #define BIT_RECHG ( BIT(0) )
648 /* bits definitions for register REG_APB_IF_CHGR_DET_FGU_CTRL */
649 #define BIT_SD_CHOP_CAP_EN ( BIT(8) )
650 #define BITS_SD_CLK_P(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
651 #define BIT_DCOFFSET_EN ( BIT(5) )
652 #define BIT_CHOP_EN ( BIT(4) )
653 #define BIT_DP_DM_AUX_EN ( BIT(1) )
654 #define BIT_DP_DM_SW_EN ( BIT(0) )
656 /* bits definitions for register REG_APB_IF_CHGR_STATUS */
657 #define BIT_CHG_DET_DONE ( BIT(11) )
658 #define BIT_DP_LOW ( BIT(10) )
659 #define BIT_DCP_DET ( BIT(9) )
660 #define BIT_CHG_DET ( BIT(8) )
661 #define BIT_SDP_INT ( BIT(7) )
662 #define BIT_DCP_INT ( BIT(6) )
663 #define BIT_CDP_INT ( BIT(5) )
664 #define BIT_CHGR_CV_STATUS ( BIT(4) )
665 #define BIT_CHGR_ON ( BIT(3) )
666 #define BIT_CHGR_INT ( BIT(2) )
667 #define BIT_VBAT_OVI ( BIT(1) )
668 #define BIT_VCHG_OVI ( BIT(0) )
670 /* bits definitions for register REG_APB_IF_MIXED_CTRL */
671 #define BIT_PTEST_PD_RTCSET ( BIT(15) )
672 #define BIT_BG_LP_EN ( BIT(12) )
673 #define BIT_OVLO_EN ( BIT(9) )
674 #define BITS_OVLO_CAL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
675 #define BITS_OVLO_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
676 #define BITS_OVLO_T(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
678 /* bits definitions for register REG_APB_IF_SWRST_CTRL */
679 #define BIT_EXT_RSTN_PD_EN ( BIT(10) )
680 #define BIT_PB_7S_RST_PD_EN ( BIT(9) )
681 #define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) )
682 #define BIT_SW_RST_EMMCIO_PD_EN ( BIT(7) )
683 #define BIT_WDG_RST_PD_EN ( BIT(6) )
684 #define BITS_SW_RST_PD_THRESHOLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
686 /* bits definitions for register REG_APB_IF_POR_RST_MONITOR */
687 #define BITS_POR_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
689 /* bits definitions for register REG_APB_IF_WDG_RST_MONITOR */
690 #define BITS_WDG_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
692 /* bits definitions for register REG_APB_IF_POR_PIN_RST_MONITOR */
693 #define BITS_POR_PIN_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
695 /* bits definitions for register REG_APB_IF_POR_SRC_FLAG */
696 #define BIT_POR_SW_FORCE_ON ( BIT(15) )
697 #define BITS_POR_SRC_FLAG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
699 /* bits definitions for register REG_APB_IF_POR_7S_CTRL */
700 #define BIT_PBINT_7S_FLAG_CLR ( BIT(15) )
701 #define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) )
702 #define BIT_CHGR_INT_FLAG_CLR ( BIT(13) )
703 #define BIT_PBINT2_FLAG_CLR ( BIT(12) )
704 #define BIT_PBINT_FLAG_CLR ( BIT(11) )
705 #define BIT_PBINT_7S_RST_SWMODE ( BIT(8) )
706 #define BITS_PBINT_7S_RST_THRESHOLD(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
707 #define BIT_PBINT_7S_RST_DISABLE ( BIT(1) )
708 #define BIT_PBINT_7S_RST_MODE ( BIT(0) )
710 /* bits definitions for register REG_APB_IF_INT_GPI_DEBUG */
711 #define BIT_ALL_GPI_DEB ( BIT(5) )
712 #define BIT_GPI_DEBUG_EN ( BIT(4) )
713 #define BIT_ALL_INT_DEB ( BIT(1) )
714 #define BIT_INT_DEBUG_EN ( BIT(0) )
716 /* bits definitions for register REG_APB_IF_HWRST_RTC */
717 #define BITS_HWRST_RTC_REG_STS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
718 #define BITS_HWRST_RTC_REG_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
720 /* bits definitions for register REG_APB_IF_CHIP_ID_LOW */
721 #define BITS_CHIP_ID_LOW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
723 /* bits definitions for register REG_APB_IF_CHIP_ID_HIGH */
724 #define BITS_CHIP_ID_HIGH(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
726 /* bits definitions for register REG_APB_IF_ARM_MF_REG */
727 #define BITS_ARM_MF_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
729 /* bits definitions for register REG_APB_IF_ARCH_EN */
730 #define BIT_ARCH_EN ( BIT(0) )
732 /* bits definitions for register REG_APB_IF_MCU_WR_PROT_VALUE */
733 #define BIT_MCU_WR_PROT ( BIT(15) )
734 #define BITS_MCU_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
736 /* bits definitions for register REG_APB_IF_PWR_WR_PROT_VALUE */
737 #define BIT_PWR_WR_PROT ( BIT(15) )
738 #define BITS_PWR_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
740 /* bits definitions for register REG_APB_IF_DCDC_CORE_ADI */
741 #define BITS_DCDC_CORE_CTL_SW_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
742 #define BITS_DCDC_CORE_CAL_SW_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
744 /* bits definitions for register REG_APB_IF_DCDC_ARM_ADI */
745 #define BITS_DCDC_ARM_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
746 #define BITS_DCDC_ARM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
748 /* bits definitions for register REG_APB_IF_DCDC_MEM_ADI */
749 #define BIT_BONDOPT2 ( BIT(7) )
750 #define BIT_BONDOPT1 ( BIT(6) )
751 #define BIT_DCDC_MEM_CTL_ADI ( BIT(5) )
752 #define BITS_DCDC_MEM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
754 /* bits definitions for register REG_APB_IF_DCDC_GEN_ADI */
755 #define BITS_DCDC_GEN_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
756 #define BITS_DCDC_GEN_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
758 /* bits definitions for register REG_APB_IF_DCDC_WPA_ADI */
759 #define BITS_DCDC_WPA_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
761 /* bits definitions for register REG_APB_IF_DCDC_WPA_DCM_ADI */
762 #define BIT_DCDC_WPA_DCM_ADI ( BIT(0) )
764 /* bits definitions for register ANA_REG_GLB_BA_CTRL0 */
765 #define BITS_SMPL_THRESHOLD(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) )
766 #define BITS_SMPL_ENABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
768 /* bits definitions for register ANA_REG_GLB_BA_CTRL1 */
769 #define BIT_IS_SMPL_ON_SW_FLAG ( BIT(15) )
770 #define BIT_SMPL_WR_ACK_FLAG ( BIT(14) )
771 #define BIT_IS_SMPL_ON_SW_CLR ( BIT(13) )
772 #define BIT_SMPL_WR_ACK_CLR ( BIT(12) )
773 #define BIT_IS_SMPL_ON ( BIT(11) )
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