1 #ifndef __LOW_POWER_H__
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2 #define __LOW_POWER_H__
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5 #define DCDC_BG (1 << 0)
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6 #define LDO_VDD18 (1 << 1)
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7 #define LDO_VDD28 (1 << 2)
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8 #define LDO_VDD25 (1 << 3)
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9 #define LDO_CON (1 << 4)
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10 #define LDO_DCXO (1 << 5)
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11 #define LDO_EMMCIO (1 << 6)
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12 #define LDO_EMMCCORE (1 << 7)
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13 #define LDO_RF0 (1 << 8)
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14 #define DCDC_CORE (1 << 9)
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15 #define DCDC_ARM (1 << 10)
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16 #define DCDC_MEM (1 << 11)
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17 #define DCDC_GEN (1 << 12)
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18 #define LDO_SD (1 << 13)
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19 #define LDO_SIM0 (1 << 14)
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20 #define LDO_SIM1 (1 << 15)
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21 #define LDO_SIM2 (1 << 16)
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22 #define LDO_CAMA (1 << 17)
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23 #define LDO_CAMD (1 << 18)
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24 #define LDO_CAMIO (1 << 19)
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25 #define LDO_CAMMOT (1 << 20)
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26 #define LDO_USB (1 << 21)
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27 #define LDO_CLSG (1 << 22)
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28 #define DCDC_WPA (1 << 23)
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29 #define LDO_LPREF (1 << 24)
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30 #define LDO_XO (1 << 25)
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31 #define RESERVED_NUM (-1)
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33 #define NO_USED (-2)/*for all no use*/
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37 #define BIT3(_X_) ((BIT(3)-1)<<(3*_X_))
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38 #define BIT8(_X_) ((BIT(8)-1)<<(8*_X_))
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42 #define PLL_MPLL (1 << 0)
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43 #define PLL_DPLL (1 << 1)
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44 #define PLL_TDPLL (1 << 2)
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45 #define PLL_WPLL (1 << 3)
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46 #define PLL_CPLL (1 << 4)
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47 #define PLL_WIFIPLL1 (1 << 5)
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48 #define PLL_WIFIPLL2 (1 << 6)
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49 #define PLL_XTL0 (1 << 7)
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50 #define PLL_XTL1 (1 << 8)
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51 #define PLL_XTL2 (1 << 9)
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52 #define PLL_XTLBUF0 (1 << 10)
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53 #define PLL_XTLBUF1 (1 << 11)
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56 #define PD_CA7_TOP (1 << 0)
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57 #define PD_CA7_C0 (1 << 1)
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58 #define PD_CA7_C1 (1 << 2)
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59 #define PD_CA7_C2 (1 << 3)
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60 #define PD_CA7_C3 (1 << 4)
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61 #define PD_AP_SYS (1 << 5)
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62 #define PD_MM_TOP (1 << 6)
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63 #define PD_GPU_TOP (1 << 7)
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64 #define PD_PUB_SYS (1 << 8)
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67 some ldos can only controled by ap. for example(shark):
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68 ldo_cam/ldo_emmc/ldo_clsg/ldo_usb/ldo_sd
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70 All ldos lowpower mode and powerdown mode can triggered by ap(chip_sleep)
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73 struct ldo_reg_bit {
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74 unsigned int ldo_id;
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76 unsigned int ldo_pd_reg;
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77 unsigned int ldo_pd_reg_bitmsk;
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79 unsigned int slp_pd_reg;
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80 unsigned int slp_pd_reg_bitmsk;
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82 unsigned int slp_lp_reg;
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83 unsigned int slp_lp_reg_bitmsk;
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85 unsigned int xtl_reg;
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86 unsigned int xtl_reg_bitmsk;
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88 unsigned int ext_xtl_reg;
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89 unsigned int ext_xtl_reg_bitmsk;
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92 static struct ldo_reg_bit ldo_reg_tb[] = {
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93 /* chip_id */ /* ldo_pd_reg */ /*slp_pd_reg*/ /*slp_lp_reg*/ /*xtl_reg*/ /*ext_xtl_reg*/
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94 { DCDC_BG, ANA_REG_GLB_LDO_DCDC_PD, BIT(0), -1, -1, ANA_REG_GLB_PWR_SLP_CTRL3, BIT(15), ANA_REG_GLB_PWR_XTL_EN3, BIT(0)|BIT(1), ANA_REG_GLB_PWR_XTL_EN3, BIT(0)|BIT(1) },
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95 { LDO_VDD18, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(0), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(0), ANA_REG_GLB_PWR_XTL_EN0, BIT(4)|BIT(5), ANA_REG_GLB_PWR_XTL_EN0, BIT(6)|BIT(7) },
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96 { LDO_VDD28, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(1), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(1), ANA_REG_GLB_PWR_XTL_EN0, BIT(0)|BIT(1), ANA_REG_GLB_PWR_XTL_EN0, BIT(2)|BIT(3) },
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97 { LDO_VDD25, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(2), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(2), ANA_REG_GLB_PWR_XTL_EN1, BIT(4)|BIT(5), ANA_REG_GLB_PWR_XTL_EN1, BIT(6)|BIT(7) },
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98 { LDO_CON, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(3), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(3), ANA_REG_GLB_PWR_XTL_EN1, BIT(0)|BIT(1), ANA_REG_GLB_PWR_XTL_EN1, BIT(2)|BIT(3) },
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99 { LDO_DCXO, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(4), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(4), ANA_REG_GLB_PWR_XTL_EN0, BIT(8)|BIT(9), ANA_REG_GLB_PWR_XTL_EN1, BIT(10)|BIT(11) },
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100 { LDO_EMMCIO, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(5), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(5), -1, -1, -1, -1 },
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101 { LDO_EMMCCORE, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(6), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(6), -1, -1, -1, -1 },
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102 { LDO_RF0, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(7), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(7), ANA_REG_GLB_PWR_XTL_EN1, BIT(8)|BIT(9), ANA_REG_GLB_PWR_XTL_EN1, BIT(10)|BIT(11) },
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103 { DCDC_CORE, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), -1, -1, ANA_REG_GLB_PWR_SLP_CTRL2, BIT(12), ANA_REG_GLB_PWR_XTL_EN4, BIT(0)|BIT(1), ANA_REG_GLB_PWR_XTL_EN4, BIT(2)|BIT(3) },
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104 { DCDC_ARM, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(8), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(10), -1, -1, -1, -1 },
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105 { DCDC_MEM, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), -1, -1, ANA_REG_GLB_PWR_SLP_CTRL2, BIT(11), ANA_REG_GLB_PWR_XTL_EN4, BIT(8)|BIT(9), ANA_REG_GLB_PWR_XTL_EN4, BIT(10)|BIT(11) },
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106 { DCDC_GEN, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(10), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(9), ANA_REG_GLB_PWR_XTL_EN4, BIT(4)|BIT(5), ANA_REG_GLB_PWR_XTL_EN4, BIT(6)|BIT(7) },
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107 { LDO_SD, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(0), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(0), -1, -1, -1, -1 },
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108 { LDO_SIM0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(1), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(1), ANA_REG_GLB_PWR_XTL_EN2, BIT(0)|BIT(2), ANA_REG_GLB_PWR_XTL_EN2, BIT(2)|BIT(3) },
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109 { LDO_SIM1, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(2), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(2), ANA_REG_GLB_PWR_XTL_EN2, BIT(4)|BIT(5), ANA_REG_GLB_PWR_XTL_EN2, BIT(6)|BIT(7) },
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110 { LDO_SIM2, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(3), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(3), ANA_REG_GLB_PWR_XTL_EN2, BIT(8)|BIT(9), ANA_REG_GLB_PWR_XTL_EN2, BIT(10)|BIT(11) },
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111 { LDO_CAMA, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(4), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(4), -1, -1, -1, -1 },
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112 { LDO_CAMD, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(5), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(5), -1, -1, -1, -1 },
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113 { LDO_CAMIO, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(6), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(6), -1, -1, -1, -1 },
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114 { LDO_CAMMOT, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(7), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(7), -1, -1, -1, -1 },
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115 { LDO_USB, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(8), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(8), -1, -1, -1, -1 },
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116 { LDO_CLSG, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(9), ANA_REG_GLB_PWR_SLP_CTRL3, BIT(9), -1, -1, -1, -1 },
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117 { DCDC_WPA, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), ANA_REG_GLB_PWR_SLP_CTRL0, BIT(9), ANA_REG_GLB_PWR_SLP_CTRL2, BIT(8), ANA_REG_GLB_PWR_XTL_EN4, BIT(12)|BIT(13), ANA_REG_GLB_PWR_XTL_EN4, BIT(14)|BIT(15) },
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118 { LDO_LPREF, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), ANA_REG_GLB_PWR_SLP_CTRL1, BIT(10), -1, -1, -1, -1, -1, -1 },
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119 { LDO_XO, -1, -1, -1, -1, -1, -1, ANA_REG_GLB_PWR_XTL_EN3, BIT(4)|BIT(5), ANA_REG_GLB_PWR_XTL_EN3, BIT(6)|BIT(7) },
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121 { RESERVED_NUM, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }
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125 struct pll_reg_bit {
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126 unsigned int pll_id;
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128 unsigned int pll_sys_reg;
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129 unsigned int pll_sys_reg_bitmsk;
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131 unsigned int cgm_ap_reg;
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132 unsigned int cgm_ap_reg_bitmsk;
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134 /*unsigned int cgm_ap_auto_reg; */
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135 /*unsigned int cgm_ap_auto_reg_bitmsk; */
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137 unsigned int pll_wait_reg;
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138 unsigned int pll_wait_reg_bitmsk;
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141 static struct pll_reg_bit pll_reg_tb[] = {
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142 { PLL_MPLL, REG_PMU_APB_MPLL_REL_CFG, BIT3(0)|BIT(3), REG_PMU_APB_CGM_AP_EN, BIT(6), REG_PMU_APB_PLL_WAIT_CNT1, BIT8(0) },
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143 { PLL_DPLL, REG_PMU_APB_DPLL_REL_CFG, BIT3(0)|BIT(3), REG_PMU_APB_CGM_AP_EN, BIT(1), REG_PMU_APB_PLL_WAIT_CNT1, BIT8(1) },
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144 { PLL_TDPLL, REG_PMU_APB_TDPLL_REL_CFG, BIT3(0)|BIT(3)|BIT(4), REG_PMU_APB_CGM_AP_EN, BIT(3), REG_PMU_APB_PLL_WAIT_CNT1, BIT8(2) },
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145 { PLL_WPLL, REG_PMU_APB_WPLL_REL_CFG, BIT3(0)|BIT(3)|BIT(4), REG_PMU_APB_CGM_AP_EN, BIT(5), REG_PMU_APB_PLL_WAIT_CNT1, BIT8(3) },
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146 { PLL_CPLL, REG_PMU_APB_CPLL_REL_CFG, BIT3(0)|BIT(3), REG_PMU_APB_CGM_AP_EN, BIT(2), REG_PMU_APB_PLL_WAIT_CNT2, BIT8(0) },
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147 { PLL_WIFIPLL1, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT3(0)|BIT(3), REG_PMU_APB_CGM_AP_EN, BIT(4), REG_PMU_APB_PLL_WAIT_CNT2, BIT8(1) },
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148 { PLL_WIFIPLL2, REG_PMU_APB_WIFIPLL2_REL_CFG, BIT3(0)|BIT(3), -1, -1, REG_PMU_APB_PLL_WAIT_CNT2, BIT8(2) },
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149 { PLL_XTL0, REG_PMU_APB_XTL0_REL_CFG, BIT3(0)|BIT(3), -1, -1, REG_PMU_APB_XTL_WAIT_CNT, BIT8(0) },
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150 { PLL_XTL1, REG_PMU_APB_XTL1_REL_CFG, BIT3(0)|BIT(3), -1, -1, REG_PMU_APB_XTL_WAIT_CNT, BIT8(1) },
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151 { PLL_XTL2, REG_PMU_APB_XTL2_REL_CFG, BIT3(0)|BIT(3), -1, -1, -1, -1 },
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152 { PLL_XTLBUF0, REG_PMU_APB_XTLBUF0_REL_CFG, BIT3(0)|BIT(3), -1, -1, REG_PMU_APB_XTLBUF_WAIT_CNT,BIT8(0) },
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153 { PLL_XTLBUF1, REG_PMU_APB_XTLBUF1_REL_CFG, BIT3(0)|BIT(3), -1, -1, REG_PMU_APB_XTLBUF_WAIT_CNT,BIT8(1) },
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154 { RESERVED_NUM, -1, -1, -1, -1, -1, -1 }
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157 struct pd_reg_bit {
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158 unsigned int pd_shutdown_id;
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159 unsigned int pd_reg;
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160 unsigned int iso_on_delay_bitmsk;
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161 unsigned int pwr_on_seq_delay_bitmsk;
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162 unsigned int pwr_on_delay_bitmsk;
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163 unsigned int auto_shutdown_bitmsk;
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164 unsigned int force_shutdown_bitmsk;
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165 unsigned int debug_shutdown_bitmsk;
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168 static struct pd_reg_bit shutdown_tb[] = {
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169 { PD_CA7_TOP, REG_PMU_APB_PD_CA7_TOP_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), BIT(28) },
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170 { PD_CA7_C0, REG_PMU_APB_PD_CA7_C0_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), BIT(28) },
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171 { PD_CA7_C1, REG_PMU_APB_PD_CA7_C1_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), BIT(28) },
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172 { PD_CA7_C2, REG_PMU_APB_PD_CA7_C2_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), BIT(28) },
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173 { PD_CA7_C3, REG_PMU_APB_PD_CA7_C3_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), BIT(28) },
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174 { PD_AP_SYS, REG_PMU_APB_PD_AP_SYS_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), -1 },
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175 { PD_MM_TOP, REG_PMU_APB_PD_MM_TOP_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), -1 },
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176 { PD_GPU_TOP, REG_PMU_APB_PD_GPU_TOP_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), -1 },
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177 { PD_PUB_SYS, REG_PMU_APB_PD_PUB_SYS_CFG, BIT8(0), BIT8(1), BIT8(2), BIT(24), BIT(25), -1 },
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178 { RESERVED_NUM, -1, -1, -1, -1, -1, -1, -1 }
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182 /*ldo chip definition*/
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183 //typedef void (*ldo_status_in_sleep)(struct ldo_lowpower_cfg *ldo_lowpower_cfg);
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184 #define SLP_LP_MODE (1 << 0) /* low power in ap sleep mode */
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185 #define SLP_PD_MODE (1 << 1) /* power down in ap sleep mode */
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186 #define SLP_NO_MODE (1 << 2) /* all no used in ap sleep mode */
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188 #define BY_XTL0 (1 << 0)
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189 //#define BY_XTL1 (1 << 1)
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190 #define BY_XTL2 (1 << 2)
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191 #define BY_XTL_ALL (BY_XTL0 | BY_XTL2)
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193 #define BY_EXT_XTL0 (1 << 0)
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194 #define BY_EXT_XTL1 (1 << 1)
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195 //#define BY_EXT_XTL2 (1 << 2)
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196 #define BY_EXT_XTL_ALL (BY_EXT_XTL0 | BY_EXT_XTL1)
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198 struct ldo_lowpower_cfg {
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199 unsigned int ldo_id;
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201 unsigned int ldo_pd;
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202 unsigned int status_in_sleep;
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203 unsigned int select_by_xtl;
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204 unsigned int select_by_ext_xtl;
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206 unsigned int priority;
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209 #define AP_SYS (1 << 0)
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210 #define CP0_SYS (1 << 1)
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211 #define CP1_SYS (1 << 2)
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212 #define CP2_SYS (1 << 3)
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213 #define REF_SYS (1 << 4)
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216 unsigned int pll_id;
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218 unsigned int sys;/*pls config acoording the real exist subsystem*/
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220 unsigned int cgm_ap_en;
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222 unsigned int priority;
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225 struct shutdown_cfg {
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226 unsigned int pd_shutdown_id;
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227 unsigned int iso_on_delay;
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228 unsigned int pwr_on_seq_delay;
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229 unsigned int pwr_on_delay;
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230 //#define AUTO_SHUTDOWN_DISEN 1
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231 //#define AUTO_SHUTDOWN_EN 2
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232 unsigned int auto_shutdown;
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233 //#define FORCE_SHUTDOWN_DISEN 1
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234 //#define FORCE_SHUTDOWN_EN 2
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235 unsigned int force_shutdown;
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236 //#define DEBUG_SHUTDOWN_DISEN 1
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237 //#define DEBUG_SHUTDOWN_EN 2
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238 unsigned int debug_shutdown;
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239 unsigned int priority;
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243 struct ldo_reg_bit *ldo_reg;
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244 struct pll_reg_bit *pll_reg;
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245 struct pd_reg_bit *pd_reg;
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247 struct ldo_lowpower_cfg *ldo_cfg;
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249 struct pll_cfg *pll_sys_cfg;
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251 struct shutdown_cfg *pd_shutdown_cfg;
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254 void customize_low_power_init_prepare(struct ldo_lowpower_cfg *ldo,
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255 struct pll_cfg *pll,
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256 struct shutdown_cfg *shutdown);
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257 void low_power_init(void);
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projects / kernel / u-boot-tm1.git / blob