2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __AUDIO_GLB_REG_H
15 #define __AUDIO_GLB_REG_H
19 #include <ubi_uboot.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/regs_glb.h>
22 #include <asm/arch/regs_ana_glb.h>
23 #include <asm/arch/sci.h>
24 #include <asm/arch/adi.h>
26 #ifdef CONFIG_SOUND_USE_DMA
27 #include <asm/arch/dma.h>
29 #ifdef CONFIG_SOUND_USE_INT
30 #include <mach/irqs.h>
33 /* OKAY, this is for other else owner
34 if you do not care the audio config
35 you can set FIXED_AUDIO to 0
53 #define SPRD_VB_BASE SPRD_VB_PHYS
58 #define SPRD_MISC_BASE SPRD_MISC_PHYS
60 #define VBC_BASE SPRD_VB_BASE
61 #define CODEC_DP_BASE (SPRD_VB_BASE + 0x1000)
62 #define CODEC_AP_BASE (SPRD_MISC_BASE + 0x0700)
63 #define VBC_PHY_BASE SPRD_VB_PHYS
64 #define CODEC_DP_PHY_BASE (SPRD_VB_PHYS + 0x1000)
65 #define CODEC_AP_PHY_BASE (SPRD_MISC_PHYS + 0x0700)
67 #ifdef CONFIG_SOUND_USE_INT
68 #define CODEC_AP_IRQ (IRQ_ANA_AUD_INT)
69 #define CODEC_DP_IRQ (IRQ_REQ_AUD_INT)
72 #ifdef CONFIG_SPRD_AUDIO_BUFFER_USE_IRAM
73 #define SPRD_IRAM_ALL_PHYS 0X00000000
74 #define SPRD_IRAM_ALL_SIZE SZ_32K
78 /* ------------------------------------------------------------------------- */
80 /* NOTE: all function maybe will call by atomic funtion
81 don NOT any complex oprations. Just register.
89 static inline int arch_audio_vbc_reg_enable(void)
94 sci_glb_set(REG_GLB_GEN1, BIT_VBC_EN);
100 static inline int arch_audio_vbc_reg_disable(void)
105 sci_glb_clr(REG_GLB_GEN1, BIT_VBC_EN);
111 static inline int arch_audio_vbc_enable(void)
116 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON);
122 static inline int arch_audio_vbc_disable(void)
127 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON);
133 static inline int arch_audio_vbc_switch(int master)
139 case AUDIO_TO_ARM_CTRL:
140 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC);
141 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP);
143 case AUDIO_TO_ARM_CP_CTRL:
144 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC);
145 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP);
147 case AUDIO_TO_DSP_CTRL:
148 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC);
150 case AUDIO_NO_CHANGE:
151 ret = sci_glb_read(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC);
153 ret = AUDIO_TO_DSP_CTRL;
155 ret = sci_glb_read(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP);
157 ret = AUDIO_TO_ARM_CTRL;
159 ret = AUDIO_TO_ARM_CP_CTRL;
171 static inline int arch_audio_vbc_ad_enable(int chan)
178 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_AD0ON);
181 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_AD1ON);
192 static inline int arch_audio_vbc_ad_disable(int chan)
199 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_AD0ON);
202 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_AD1ON);
213 static inline int arch_audio_vbc_da_enable(int chan)
220 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_DA0ON);
223 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_DA1ON);
234 static inline int arch_audio_vbc_da_disable(int chan)
241 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_DA0ON);
244 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_DA1ON);
255 static inline int arch_audio_vbc_da_dma_info(int chan)
260 #ifdef CONFIG_SOUND_USE_DMA
278 static inline int arch_audio_vbc_ad_dma_info(int chan)
283 #ifdef CONFIG_SOUND_USE_DMA
301 static inline int arch_audio_vbc_reset(void)
306 sci_glb_set(REG_GLB_SOFT_RST, BIT_VBC_RST);
308 sci_glb_clr(REG_GLB_SOFT_RST, BIT_VBC_RST);
314 /* some SOC will move this into vbc module */
315 static inline int arch_audio_vbc_ad_int_clr(void)
325 /* some SOC will move this into vbc module */
326 static inline int arch_audio_vbc_da_int_clr(void)
336 /* some SOC will move this into vbc module */
337 static inline int arch_audio_vbc_is_ad_int(void)
347 /* some SOC will move this into vbc module */
348 static inline int arch_audio_vbc_is_da_int(void)
358 /* ------------------------------------------------------------------------- */
361 static inline int arch_audio_codec_write_mask(int reg, int val, int mask)
366 ret = sci_adi_write(reg, val, mask);
372 static inline int arch_audio_codec_write(int reg, int val)
377 ret = sci_adi_write(reg, val, 0xFFFF);
383 static inline int arch_audio_codec_read(int reg)
388 ret = sci_adi_read(reg);
394 static inline int arch_audio_codec_audif_enable(int auto_clk)
400 sci_glb_clr(REG_GLB_GEN1, BIT_AUD_IF_EB);
401 sci_glb_set(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN);
403 sci_glb_set(REG_GLB_GEN1, BIT_AUD_IF_EB);
404 sci_glb_clr(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN);
411 static inline int arch_audio_codec_audif_disable(void)
416 sci_glb_clr(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN);
417 sci_glb_clr(REG_GLB_GEN1, BIT_AUD_IF_EB);
423 static inline int arch_audio_codec_digital_reg_enable(void)
428 sci_glb_set(REG_GLB_GEN1, BIT_AUD_TOP_EB);
430 arch_audio_codec_audif_enable(1);
436 static inline int arch_audio_codec_digital_reg_disable(void)
441 arch_audio_codec_audif_disable();
442 sci_glb_clr(REG_GLB_GEN1, BIT_AUD_TOP_EB);
448 static inline int arch_audio_codec_analog_reg_enable(void)
454 sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, BIT_AUD_ARM_EN,
461 static inline int arch_audio_codec_analog_reg_disable(void)
466 ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, BIT_AUD_ARM_EN);
472 static inline int arch_audio_codec_enable(void)
477 int mask = BIT_AUD6M5_CLK_TX_INV_ARM_EN |
478 BIT_RTC_AUD_ARM_EN | BIT_CLK_AUD_6M5_ARM_EN | BIT_CLK_AUDIF_ARM_EN;
479 ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, mask, mask);
485 static inline int arch_audio_codec_disable(void)
491 BIT_RTC_AUD_ARM_EN | BIT_CLK_AUD_6M5_ARM_EN | BIT_CLK_AUDIF_ARM_EN;
492 ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, mask);
498 static inline int arch_audio_codec_switch(int master)
504 case AUDIO_TO_ARM_CTRL:
505 sci_glb_set(REG_GLB_GEN1, BIT_AUD_CTL_SEL | BIT_AUD_CLK_SEL);
506 sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VB_SEL);
508 sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST,
509 BIT_AUD_ARM_ACC, BIT_AUD_ARM_ACC);
511 case AUDIO_TO_DSP_CTRL:
512 sci_glb_clr(REG_GLB_GEN1, BIT_AUD_CTL_SEL | BIT_AUD_CLK_SEL);
513 sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VB_SEL);
515 sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0,
518 case AUDIO_NO_CHANGE:
520 sci_adi_read(ANA_REG_GLB_ARM_AUD_CLK_RST) & BIT_AUD_ARM_ACC;
522 ret = AUDIO_TO_DSP_CTRL;
524 ret = AUDIO_TO_ARM_CTRL;
535 static inline int arch_audio_codec_reset(void)
541 BIT_AUD_ARM_SOFT_RST | BIT_AUDTX_ARM_SOFT_RST |
542 BIT_AUDRX_ARM_SOFT_RST;
543 sci_glb_set(REG_GLB_SOFT_RST, BIT_AUD_TOP_RST);
544 sci_glb_set(REG_GLB_SOFT_RST, BIT_AUD_IF_RST);
545 ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, mask, mask);
547 sci_glb_clr(REG_GLB_SOFT_RST, BIT_AUD_TOP_RST);
548 sci_glb_clr(REG_GLB_SOFT_RST, BIT_AUD_IF_RST);
550 ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, mask);
556 /* ------------------------------------------------------------------------- */
559 static inline const char * arch_audio_i2s_clk_name(int id)
576 static inline int arch_audio_i2s_enable(int id)
583 sci_glb_set(REG_GLB_GEN0, BIT_IIS0_EB);
586 sci_glb_set(REG_GLB_GEN0, BIT_IIS1_EB);
597 static inline int arch_audio_i2s_disable(int id)
604 sci_glb_clr(REG_GLB_GEN0, BIT_IIS0_EB);
607 sci_glb_clr(REG_GLB_GEN0, BIT_IIS1_EB);
618 static inline int arch_audio_i2s_tx_dma_info(int id)
623 #ifdef CONFIG_SOUND_USE_DMA
641 static inline int arch_audio_i2s_rx_dma_info(int id)
646 #ifdef CONFIG_SOUND_USE_DMA
665 static inline int arch_audio_i2s_reset(int id)
672 sci_glb_set(REG_GLB_SOFT_RST, BIT_IIS0_RST);
674 sci_glb_clr(REG_GLB_SOFT_RST, BIT_IIS0_RST);
677 sci_glb_set(REG_GLB_SOFT_RST, BIT_IIS1_RST);
679 sci_glb_clr(REG_GLB_SOFT_RST, BIT_IIS1_RST);
690 static inline int arch_audio_i2s_switch(int id, int master)
698 case AUDIO_TO_ARM_CTRL:
699 sci_glb_clr(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL);
701 case AUDIO_TO_DSP_CTRL:
702 sci_glb_set(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL);
704 case AUDIO_NO_CHANGE:
705 ret = sci_glb_read(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL);
707 ret = AUDIO_TO_DSP_CTRL;
709 ret = AUDIO_TO_ARM_CTRL;
718 case AUDIO_TO_ARM_CTRL:
719 sci_glb_clr(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL);
721 case AUDIO_TO_DSP_CTRL:
722 sci_glb_set(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL);
724 case AUDIO_NO_CHANGE:
725 ret = sci_glb_read(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL);
727 ret = AUDIO_TO_DSP_CTRL;
729 ret = AUDIO_TO_ARM_CTRL;