arch/arm/include/asm/arch-sc8825/sdram.h

   1 #ifndef _SDRAM_H_
   2 #define _SDRAM_H_
   3
   4 #if defined(CONFIG_SC8810)
   5 typedef enum EMC_ENDIAN_SWITCH_TAG
   6 {
   7     EMC_ENDIAN_SWITCH_NONE = 3,
   8     EMC_ENDIAN_SWITCH_BYTE = 0,
   9     EMC_ENDIAN_SWITCH_HALF = 1,
  10     EMC_ENDIAN_SWITCH_WORD = 2,
  11 }
  12 EMC_ENDIAN_SWITCH_E;
  13
  14 typedef enum EMC_DVC_ENDIAN_TAG
  15 {
  16     EMC_DVC_ENDIAN_DEFAULT = 0,
  17     EMC_DVC_ENDIAN_LITTLE = 0,
  18     EMC_DVC_ENDIAN_BIG = 1
  19 }
  20 EMC_DVC_ENAIDN_E;
  21
  22 typedef enum EMC_AUTO_GATE_TAG
  23 {
  24     EMC_AUTO_GATE_DEFAULT = 0,
  25     EMC_AUTO_GATE_DIS = 0,
  26     EMC_AUTO_GATE_EN = 1
  27 }
  28 EMC_AUTO_GATE_E;
  29
  30 typedef enum EMC_AUTO_SLEEP_TAG
  31 {
  32     EMC_AUTO_SLEEP_DEFAULT = 0,
  33     EMC_AUTO_SLEEP_DIS = 0,
  34     EMC_AUTO_SLEEP_EN = 1
  35 }
  36 EMC_AUTO_SLEEP_E;
  37
  38 typedef enum EMC_CMD_QUEUE_TAG
  39 {
  40     EMC_2DB = 0,                // 2 stage device burst
  41     EMC_2DB_1CB,                // 2-stage device burst and 1-stage channel burst
  42     EMC_2DB_2CB         // 2-stage device burst and 2-stage channel burst
  43 }
  44 EMC_CMD_QUEUE_E;
  45
  46 typedef enum EMC_CS_MODE_TAG
  47 {
  48     EMC_CS_MODE_DEFAULT = 0,
  49     EMC_CS0_ENLARGE = 1,
  50     EMC_CS1_ENLARGE = 2
  51 }
  52 EMC_CS_MODE_E;
  53
  54 typedef enum EMC_CS_MAP_TAG
  55 {
  56     EMC_CS_MAP_DEFAULT = 5,
  57     EMC_CS_MAP_32M = 0,
  58     EMC_CS_MAP_64M = 1,
  59     EMC_CS_MAP_128M = 2,
  60     EMC_CS_MAP_256M = 3,
  61     EMC_CS_MAP_512M = 4,
  62     EMC_CS_MAP_1G = 5,
  63     EMC_CS_MAP_2G = 6,
  64     EMC_CS_MAP_4G = 7
  65 }
  66 EMC_CS_MAP_E;
  67
  68 typedef enum EMC_CS_NUM_TAG
  69 {
  70     EMC_CS0 = 0,
  71     EMC_CS1
  72 }
  73 EMC_CS_NUM_E;
  74
  75 typedef enum EMC_BURST_MODE_TAG
  76 {
  77     BURST_WRAP = 0,
  78     BURST_INCR
  79 }
  80 EMC_BURST_MODE_E;
  81
  82 typedef enum EMC_BURST_INVERT_TAG
  83 {
  84     HBURST_TO_SINGLE = 0,
  85     HBURST_TO_BURST
  86 }
  87 EMC_BURST_INVERT_E;
  88
  89 typedef enum EMC_CHL_NUM_TAG
  90 {
  91     EMC_AXI_ARM = 0,
  92     EMC_AXI_GPU = 1,
  93     EMC_AHB_MTX1 = 2,
  94     EMC_AHB_MTX2 = 3,
  95     EMC_DSP_CHL = 4,
  96     EMC_DSP_MTX = 5,
  97     EMC_DCAM_CHL = 6,
  98     EMC_LCD_CHL = 7,
  99     EMC_VSP_CHL = 8
 100 }
 101 EMC_CHL_NUM_E;
 102
 103
 104 typedef enum EMC_CLK_SYNC_TAG
 105 {
 106     EMC_CLK_ASYNC = 0,
 107     EMC_CLK_SYNC
 108 }
 109 EMC_CLK_SYNC_E;
 110
 111 typedef enum EMC_REF_CS_TAG
 112 {
 113     EMC_CS_REF_OBO = 0, //CSs auto-refresh one by one
 114     EMC_CS_REF_SAME     //CSs auto-refresh at same time
 115 }
 116 EMC_CS_REF_E;
 117
 118 typedef enum EMC_PRE_BIT_TAG
 119 {
 120     EMC_PRE_BIT_A10 = 0,
 121     EMC_PRE_BIT_A11,
 122     EMC_PRE_BIT_A12,
 123     EMC_PRE_BIT_A13
 124 }
 125 EMC_PRE_BIT_E;
 126
 127 typedef enum EMC_DL_SWTICH_TAG
 128 {
 129     EMC_DL_OFF = 0,
 130     EMC_DL_ON
 131 }
 132 EMC_DL_SWTICH_E;
 133
 134 typedef enum EMC_CKE_SEL_TAG
 135 {
 136     EMC_CKE_SEL_DEFAULT = 0,
 137     EMC_CKE_CS0 = 0,
 138     EMC_CKE_CS1 = 1,
 139     EMC_CKE_ALL_CS = 2
 140 }
 141 EMC_CKE_SEL_E;
 142
 143 typedef enum EMC_DQS_GATE_LOOP_TAG
 144 {
 145     EMC_DQS_GATE_DEFAULT = 0,
 146     EMC_DQS_GATE_DL = 0,
 147     EMC_DQS_GATE_DL_LB = 1,
 148     EMC_DQS_GATE_LB = 2
 149 }
 150 EMC_DQS_GATE_LOOP_E;
 151
 152 typedef enum EMC_DQS_GATE_MODE_TAG
 153 {
 154     EMC_DQS_GATE_MODE_DEFAULT = 0,
 155     EMC_DQS_GATE_MODE0 = 0,
 156     EMC_DQS_GATE_MODE1 = 1
 157 }
 158 EMC_DQS_GATE_MODE_E;
 159
 160 typedef enum EMC_PHY_TIMING_NUM_TAG
 161 {
 162     EMC_PHY_TIMING_SDRAM_LATENCY2 = 0,
 163     EMC_PHY_TIMING_SDRAM_LATENCY3,
 164     EMC_PHY_TIMING_DDRAM_LATENCY2,
 165     EMC_PHY_TIMING_DDRAM_LATENCY3,
 166     EMC_PHY_TIMING_MATRIX_MAX
 167 }EMC_PHY_TIMING_NUM_E;
 168
 169 typedef enum EMC_DLL_NUM_TAG
 170 {
 171         EMC_DMEM_DL0 = 0,
 172         EMC_DMEM_DL1,
 173         EMC_DMEM_DL2,
 174         EMC_DMEM_DL3,
 175         EMC_DMEM_DL4,
 176         EMC_DMEM_DL5,
 177         EMC_DMEM_DL7,
 178         EMC_DMEM_DL8,
 179         EMC_DMEM_DL9,
 180         EMC_DMEM_DL10,
 181         EMC_DMEM_DL11,
 182         EMC_DMEM_DL12,
 183         EMC_DMEM_DL13,
 184         EMC_DMEM_DL14,
 185         EMC_DMEM_DL15,
 186         EMC_DMEM_DL16,
 187         EMC_DMEM_DL17,
 188         EMC_DMEM_DL18,
 189         EMC_DMEM_DL19,
 190         EMC_DMEM_MAX
 191 }EMC_DLL_NUM_E;
 192
 193 typedef struct EMC_PHY_L1_TIMING_TAG
 194 {
 195         uint32 data_pad_ie_delay;
 196         uint32 data_pad_oe_delay;
 197         uint32 dqs_gate_pst_delay;
 198         uint32 dqs_gate_pre_delay;
 199         uint32 dqs_ie_delay;
 200         uint32 dqs_oe_delay;
 201 }EMC_PHY_L1_TIMING_T,*EMC_PHY_L1_TIMING_T_PTR;
 202
 203 typedef struct EMC_PHY_L2_TIMING_TAG
 204 {
 205         uint32 clkdmem_out_dl;
 206         uint32 dqs_ie_dl;
 207         uint32 dqs_out_dl;
 208         uint32 clkwr_dl;
 209         uint32 dqs_gate_pre_dl_0;
 210         uint32 dqs_gate_pre_dl_1;
 211         uint32 dqs_gate_pre_dl_2;
 212         uint32 dqs_gate_pre_dl_3;
 213         uint32 dqs_gate_pst_dl_0;
 214         uint32 dqs_gate_pst_dl_1;
 215         uint32 dqs_gate_pst_dl_2;
 216         uint32 dqs_gate_pst_dl_3;
 217         uint32 dqs_in_pos_dl_0;
 218         uint32 dqs_in_pos_dl_1;
 219         uint32 dqs_in_pos_dl_2;
 220         uint32 dqs_in_pos_dl_3;
 221         uint32 dqs_in_neg_dl_0;
 222         uint32 dqs_in_neg_dl_1;
 223         uint32 dqs_in_neg_dl_2;
 224         uint32 dqs_in_neg_dl_3;
 225 }EMC_PHY_L2_TIMING_T,*EMC_PHY_L2_TIMING_T_PTR;
 226
 227 /*
 228 #define EMC_BASEADDR 0x20000000
 229 #define EMC_CFG0  0x20000000
 230
 231 #define DMEM_CFG0   (EMC_BASEADDR + 0x40)
 232 */
 233 #define DCFG0_DQM_MODE_LOW             0           //DQM low in deactive
 234 #define DCFG0_DQM_MODE_W0R0            1           //DQM hihe in deactive,Write: 0 cycle delay; Read: 0 cycle delay;
 235 #define DCFG0_DQM_MODE_W0R1            2           //DQM hihe in deactive,Write: 0 cycle delay; Read: 1 cycle delay;
 236 #define DCFG0_DQM_MODE_W0R2            3           //DQM hihe in deactive,Write: 0 cycle delay; Read: 2 cycle delay;
 237
 238 #define DCFG0_DQM_TERM_EN              (1u << 2)
 239 #define DCFG0_DQM_FORCE_HIGH           (1u << 3)
 240
 241 #define DCFG0_BKPOS_HADDR3             (0u << 4)
 242 #define DCFG0_BKPOS_HADDR4             (1u << 4)
 243 #define DCFG0_BKPOS_HADDR5             (2u << 4)
 244 #define DCFG0_BKPOS_HADDR6             (3u << 4)
 245 #define DCFG0_BKPOS_HADDR8             (4u << 4)
 246 #define DCFG0_BKPOS_HADDR10             (5u << 4)
 247 #define DCFG0_BKPOS_HADDR13             (6u << 4)
 248 #define DCFG0_BKPOS_HADDR16             (7u << 4)
 249 #define DCFG0_BKPOS_HADDR18             (8u << 4)
 250 #define DCFG0_BKPOS_HADDR20             (9u << 4)
 251 #define DCFG0_BKPOS_HADDR22             (10u << 4)
 252 #define DCFG0_BKPOS_HADDR23             (11u << 4)
 253 #define DCFG0_BKPOS_HADDR24             (12u << 4)
 254 #define DCFG0_BKPOS_HADDR25             (13u << 4)
 255 #define DCFG0_BKPOS_HADDR26             (14u << 4)
 256 #define DCFG0_BKPOS_HADDR28             (15u << 4)
 257
 258 #define DCFG0_BKMODE_1                (0u << 8)
 259 #define DCFG0_BKMODE_2                (1u << 8)
 260 #define DCFG0_BKMODE_4                (2u << 8)
 261 #define DCFG0_BKMODE_8                (3u << 8)
 262
 263 #define DCFG0_ROWMODE_11              (0u << 10)
 264 #define DCFG0_ROWMODE_12              (1u << 10)
 265 #define DCFG0_ROWMODE_13              (2u << 10)
 266
 267 #define DCFG0_COLMODE_8               (0u << 12)
 268 #define DCFG0_COLMODE_9               (1u << 12)
 269 #define DCFG0_COLMODE_10               (2u << 12)
 270 #define DCFG0_COLMODE_11               (3u << 12)
 271 #define DCFG0_COLMODE_12               (4u << 12)
 272
 273 #define DCFG0_DWIDTH_16               (0u << 15)
 274 #define DCFG0_DWIDTH_32               (1u << 15)
 275
 276 #define DCFG0_BL_2                    (1u << 16)
 277 #define DCFG0_BL_4                    (2u << 16)
 278 #define DCFG0_BL_8                    (3u << 16)
 279 #define DCFG0_BL_16                   (4u << 16)
 280 #define DCFG0_BL_FULLPAGE             (7u << 16)
 281
 282 #define DCFG0_AUTOREF_ALLCS           (1u << 19)
 283
 284 #define DCFG0_RL_2                    (2u << 20)
 285 #define DCFG0_RL_3                    (3u << 20)
 286 #define DCFG0_RL_4                    (4u << 20)
 287 #define DCFG0_RL_5                    (5u << 20)
 288 #define DCFG0_RL_6                    (6u << 20)
 289 #define DCFG0_RL_7                    (7u << 20)
 290
 291 #define DCFG0_T_RW_0                  (0u << 29)
 292 #define DCFG0_T_RW_1                  (1u << 29)
 293
 294 #define DCFG0_ALTERNATIVE_EN          (1u << 30)
 295 #define DCFG0_ROWHIT_EN               (1u << 31)
 296 #define DCFG0_AUTOREF_EN             BIT_14
 297
 298 //define mode register domain..
 299
 300 #define MODE_REG_BL_1               (0)
 301 #define MODE_REG_BL_2               (1)
 302 #define MODE_REG_BL_4               (2)
 303 #define MODE_REG_BL_8               (3)
 304
 305 #define MODE_REG_BT_SEQ               (0)
 306 #define MODE_REG_BT_INT               (1)
 307
 308 #define MODE_REG_CL_1                 (1)
 309 #define MODE_REG_CL_2                 (2)
 310 #define MODE_REG_CL_3                 (3)
 311
 312 #define MODE_REG_OPMODE               (0)
 313
 314 #define MODE_REG_WB_PRORAM            (0)
 315 #define MODE_REG_WB_SINGLE            (1)
 316
 317 //define extended mode register domain...
 318 #define EX_MODE_REG_PASR_4_BANKS      (0)
 319 #define EX_MODE_REG_PASR_2_BANKS      (1)
 320 #define EX_MODE_REG_PASR_1_BANKS      (2)
 321 #define EX_MODE_REG_PASR_HALF_BANK      (5)
 322 #define EX_MODE_REG_PASR_QUART_BANK      (6)
 323
 324 #define EX_MODE_REG_DS_FULL           (0)
 325 #define EX_MODE_REG_DS_HALF           (1)
 326
 327 #elif defined(CONFIG_TIGER)
 328 typedef enum
 329 {
 330         STATE_INIT_MEM,
 331         STATE_CONFIG,
 332         STATE_CONFIG_REQ,
 333         STATE_ACCESS,
 334         STATE_ACCESS_REQ,
 335         STATE_LOW_POWER,
 336         STATE_LOW_POWER_ENTRY_REQ,
 337         STATE_LOW_POWER_EXIT_REQ
 338 }UPCTL_STATE_E;
 339 typedef enum
 340 {
 341         CMD_INIT,
 342         CMD_CFG,
 343         CMD_GO,
 344         CMD_SLEEP,
 345         CMD_WAKEUP
 346 }UPCTL_CMD_E;
 347
 348 #define LPDDR1_SDRAM 1
 349 #define LPDDR2_SDRAM 2
 350
 351
 352 #define UMCTL_REG_BASE      0x60200000
 353 #define PUBL_REG_BASE       0x60201000
 354 #define EMC_MEM_BASE_ADDR   0x80000000
 355 #define UMCTL_REG(X)        REG32(UMCTL_REG_BASE+X)
 356 #define PUBL_REG(X)         REG32(PUBL_REG_BASE+X)
 357
 358 #define DRAM_TYPE       1 //0:LPDDR2_S2_OR_LPDDR1_ROW14_COL9 1:0:LPDDR2_S4_OR_LPDDR1_ROW13_COL10
 359 #define DRAM_ADDR_MAP   1 //0:rank+bank+row+col 1:rank+row+bank+col 2:bank+row+rank+col
 360 #define DRAM_DENSITY    5 //0:64MBIT 1:128MBIT 2:256MBIT 3:512MBIT 4:1GBIT 5:2GBIT 6:4GBIT 7:8GBIT
 361 #define DRAM_IO_WIDTH   3 //1:X8 2:X16 3:X32
 362 #define DRAM_BT         0 //0:sequential 1:interleaving
 363 #define DRAM_BL         3 //1:BL2 2:BL4 3:BL8 4:BL16
 364                           //LPDDR1:2,4,8,16 seems must be 8 now
 365                           //LPDDR2:4,8,16
 366 #define DRAM_CL         3 //2:CL2 3:CL3 4:CL4
 367 #define DRAM_WC         1 //0:WRAP 1:NO_WRAP
 368
 369 //register
 370 #define UMCTL_CFG_SCFG          0x000
 371 #define UMCTL_CFG_SCTL          0x004
 372 #define UMCTL_CFG_STAT          0x008
 373 #define UMCTL_CFG_MCMD          0x040
 374 #define UMCTL_CFG_POWCTL        0x044
 375 #define UMCTL_CFG_POWSTAT       0x048
 376 #define UMCTL_CFG_MCFG          0x080
 377 #define UMCTL_CFG_TOGCNT1U      0x0c0
 378 #define UMCTL_CFG_TINIT         0x0c4
 379 #define UMCTL_CFG_TRSTH         0x0c8
 380 #define UMCTL_CFG_TOGCNT100N    0x0cc
 381 #define UMCTL_CFG_TREFI         0x0d0
 382 #define UMCTL_CFG_TMRD          0x0d4
 383 #define UMCTL_CFG_TRFC          0x0d8
 384 #define UMCTL_CFG_TRP           0x0dc
 385 #define UMCTL_CFG_TRTW          0x0e0
 386 #define UMCTL_CFG_TAL           0x0e4
 387 #define UMCTL_CFG_TCL           0x0e8
 388 #define UMCTL_CFG_TCWL          0x0ec
 389 #define UMCTL_CFG_TRAS          0x0f0
 390 #define UMCTL_CFG_TRC           0x0f4
 391 #define UMCTL_CFG_TRCD          0x0f8
 392 #define UMCTL_CFG_TRRD          0x0fc
 393 #define UMCTL_CFG_TRTP          0x100
 394 #define UMCTL_CFG_TWR           0x104
 395 #define UMCTL_CFG_TWTR          0x108
 396 #define UMCTL_CFG_TEXSR         0x10c
 397 #define UMCTL_CFG_TXP           0x110
 398 #define UMCTL_CFG_TXPDLL        0x114
 399 #define UMCTL_CFG_TZQCS         0x118
 400 #define UMCTL_CFG_TZQCSI        0x11c
 401 #define UMCTL_CFG_TDQS          0x120
 402 #define UMCTL_CFG_TCKSRE        0x124
 403 #define UMCTL_CFG_TCKSRX        0x128
 404 #define UMCTL_CFG_TCKE          0x12c
 405 #define UMCTL_CFG_TMOD          0x130
 406 #define UMCTL_CFG_TRSTL         0x134
 407 #define UMCTL_CFG_TZQCL         0x138
 408 #define UMCTL_CFG_TCKESR        0x13c
 409 #define UMCTL_CFG_TDPD          0x140
 410 #define UMCTL_CFG_DFITPHYWRDATA 0x250
 411 #define UMCTL_CFG_DFITPHYWRLAT  0x254
 412 #define UMCTL_CFG_DFITRDDATAEN  0x260
 413 #define UMCTL_CFG_DFITPHYRDLAT  0x264
 414 #define UMCTL_CFG_DFISTSTAT0    0x2c0
 415 #define UMCTL_CFG_DFISTCFG0     0x2c4
 416 #define UMCTL_CFG_DFISTCFG1     0x2c8
 417 #define UMCTL_CFG_DFISTCFG2     0x2d8
 418 #define UMCTL_CFG_DFILPCFG0     0x2f0
 419 #define UMCTL_CFG_PCFG0         0x400
 420 #define UMCTL_CFG_PCFG1         0x404
 421 #define UMCTL_CFG_PCFG2         0x408
 422 #define UMCTL_CFG_PCFG3         0x40c
 423 #define UMCTL_CFG_PCFG4         0x410
 424 #define UMCTL_CFG_PCFG5         0x414
 425 #define UMCTL_CFG_PCFG6         0x418
 426 #define UMCTL_CFG_PCFG7         0x41c
 427 #define UMCTL_CFG_DCFG          0x484
 428
 429 #define PUBL_CFG_RIDR           (0x00*4)
 430 #define PUBL_CFG_PIR            (0x01*4)
 431 #define PUBL_CFG_PGCR           (0x02*4)
 432 #define PUBL_CFG_PGSR           (0x03*4)
 433 #define PUBL_CFG_DLLGCR         (0x04*4)
 434 #define PUBL_CFG_ACDLLCR        (0x05*4)
 435 #define PUBL_CFG_PTR0           (0x06*4)
 436 #define PUBL_CFG_PTR1           (0x07*4)
 437 #define PUBL_CFG_PTR2           (0x08*4)
 438 #define PUBL_CFG_ACIOCR         (0x09*4)
 439 #define PUBL_CFG_DXCCR          (0x0A*4)
 440 #define PUBL_CFG_DSGCR          (0x0B*4)
 441 #define PUBL_CFG_DCR            (0x0C*4)
 442 #define PUBL_CFG_DTPR0          (0x0D*4)
 443 #define PUBL_CFG_DTPR1          (0x0E*4)
 444 #define PUBL_CFG_DTPR2          (0x0F*4)
 445 #define PUBL_CFG_MR0            (0x10*4)
 446 #define PUBL_CFG_MR1            (0x11*4)
 447 #define PUBL_CFG_MR2            (0x12*4)
 448 #define PUBL_CFG_MR3            (0x13*4)
 449 #define PUBL_CFG_ODTCR          (0x14*4)
 450 #define PUBL_CFG_DTAR           (0x15*4)
 451 #define PUBL_CFG_DTDR0          (0x16*4)
 452 #define PUBL_CFG_DTDR1          (0x17*4)
 453 #define PUBL_CFG_DX0GSR0        (0x71*4)
 454 #define PUBL_CFG_DX0DQSTR       (0x75*4)
 455 #define PUBL_CFG_DX1GSR0        (0x81*4)
 456 #define PUBL_CFG_DX1DQSTR       (0x85*4)
 457 #define PUBL_CFG_DX2GSR0        (0x91*4)
 458 #define PUBL_CFG_DX2DQSTR       (0x95*4)
 459 #define PUBL_CFG_DX3GSR0        (0xa1*4)
 460 #define PUBL_CFG_DX3DQSTR       (0xa5*4)
 461 #endif
 462
 463 #endif//end of file