arch/arm/include/asm/arch-sc8825/sc8825_emc_cfg.h

   1 /******************************************************************************\r
   2  ** File Name:      sc8825_emc_cfg.h                                          *\r
   3  ** Author:         Johnny.Wang                                               *\r
   4  ** DATE:           2012/12/04                                                *\r
   5  ** Copyright:      2005 Spreatrum, Incoporated. All Rights Reserved.         *\r
   6  ** Description:                                                              *\r
   7  ******************************************************************************/\r
   8 #include "sci_types.h"\r
   9 #include "sc_reg.h"\r
  10 \r
  11 \r
  12 /******************************************************************************\r
  13                           junior Macro define\r
  14 ******************************************************************************/\r
  15 #define UL_ONEBITS 0xffffffff\r
  16 #define UL_LEN 32\r
  17 #define ONE 0x00000001\r
  18 \r
  19 \r
  20 \r
  21 /******************************************************************************\r
  22                             Enum define\r
  23 ******************************************************************************/\r
  24 typedef enum \r
  25 {\r
  26         CTL_STATE_INIT_MEM,\r
  27         CTL_STATE_CONFIG,\r
  28         CTL_STATE_CONFIG_REQ,\r
  29         CTL_STATE_ACCESS,\r
  30         CTL_STATE_ACCESS_REQ,\r
  31         CTL_STATE_LOW_POWER,\r
  32         CTL_STATE_LOW_POWER_ENTRY_REQ,\r
  33         CTL_STATE_LOW_POWER_EXIT_REQ,\r
  34 }EMC_CTL_STATE_E; \r
  35 \r
  36 typedef enum \r
  37 {\r
  38         CTL_CMD_INIT,\r
  39         CTL_CMD_CFG,\r
  40         CTL_CMD_GO,\r
  41         CTL_CMD_SLEEP,\r
  42         CTL_CMD_WAKEUP,\r
  43 }EMC_CTL_CMD_E;\r
  44 \r
  45 \r
  46 typedef enum\r
  47 {\r
  48         DRAM_LPDDR1     = 1,\r
  49         DRAM_LPDDR2_S2  = 2,\r
  50         DRAM_LPDDR2_S4  = 3,\r
  51         DRAM_LPDDR2             = 0x2,\r
  52         DRAM_DDR3               = 4\r
  53 }DRAM_TYPE_E;\r
  54 \r
  55 typedef enum\r
  56 {\r
  57         DRAM_0BIT       = 0,\r
  58         DRAM_64MBIT             = 0x00800000,\r
  59         DRAM_128MBIT    = 0x01000000,\r
  60         DRAM_256MBIT    = 0x02000000,\r
  61         DRAM_512MBIT    = 0x04000000,\r
  62         DRAM_1GBIT      = 0x08000000,   \r
  63         DRAM_2GBIT      = 0x10000000,           \r
  64         DRAM_4GBIT      = 0x20000000,   \r
  65         DRAM_8GBIT      = 0x40000000,\r
  66         DRAM_16GBIT     = 0x80000000,   \r
  67 }DRAM_DENSITY_E;\r
  68 \r
  69 typedef enum\r
  70 {\r
  71         ONE_CS                  = 1,\r
  72         TWO_CS                  = 2,\r
  73         FIRST_CS                = 1,\r
  74         SECOND_CS               = 2,    \r
  75         THIRD_CS                = 4,\r
  76         FORTH_CS                = 8,\r
  77         ALL_TWO_CS              = 3,\r
  78         ALL_THREE_CS    = 7,\r
  79         ALL_FOUR_CS     = 0XF,\r
  80 }DRAM_CS_NUM_E;\r
  81 \r
  82 typedef enum\r
  83 {\r
  84         DRAM_BL2 = 0,\r
  85         DRAM_BL4 = 1,\r
  86         DRAM_BL8 = 2,\r
  87         DRAM_BL16 = 3\r
  88 }DRAM_BL_E;\r
  89 \r
  90 typedef enum\r
  91 {\r
  92         DRAM_BT_SEQ = 0, //burst type = sequential(default)\r
  93         DRAM_BT_INT = 1  //burst type = interleaved\r
  94 }DRAM_BT_E;\r
  95 \r
  96 typedef enum\r
  97 {\r
  98         DRAM_WRAP    = 0, //warp mode\r
  99         DRAM_NO_WRAP = 1  //no warp mode\r
 100 }DRAM_WC_E;\r
 101 \r
 102 typedef enum\r
 103 {\r
 104         LPDDR1_CL0 = 0,\r
 105         LPDDR1_CL2 = 2,\r
 106         LPDDR1_CL3 = 3,\r
 107         LPDDR1_CL4 = 4,\r
 108         LPDDR2_RL3 = 3,\r
 109         LPDDR2_RL4 = 4,\r
 110         LPDDR2_RL5 = 5,\r
 111         LPDDR2_RL6 = 6,\r
 112         LPDDR2_RL7 = 7,\r
 113         LPDDR2_RL8 = 8,\r
 114         LPDDR2_WL1 = 1,\r
 115         LPDDR2_WL2 = 2,\r
 116         LPDDR2_WL3 = 3,\r
 117         LPDDR2_WL4 = 4\r
 118 }DRAM_CL_E;\r
 119 \r
 120 typedef enum\r
 121 {\r
 122         IO_WIDTH_8  = 1,\r
 123         IO_WIDTH_16 = 2,\r
 124         IO_WIDTH_32 = 3\r
 125 }IO_WIDTH_E;\r
 126 \r
 127 typedef enum{\r
 128     CLK_24MHZ    = 24000000,\r
 129     CLK_26MHZ    = 26000000,\r
 130     CLK_38_4MHZ  = 38400000,\r
 131     CLK_48MHZ    = 48000000,\r
 132     CLK_64MHZ    = 64000000,\r
 133     CLK_76_8MHZ  = 76800000,\r
 134     CLK_96MHZ    = 96000000,\r
 135     CLK_100MHZ   = 100000000,    \r
 136     CLK_150MHZ   = 150000000,        \r
 137     CLK_153_6MHZ = 153600000,\r
 138     CLK_192MHZ   = 192000000,\r
 139         CLK_200MHZ   = 200000000,    \r
 140     CLK_333MHZ   = 333000000,\r
 141     CLK_400MHZ   = 400000000,\r
 142     CLK_427MHZ   = 427000000,\r
 143     CLK_450MHZ   = 450000000,\r
 144     CLK_500MHZ   = 500000000,\r
 145     CLK_525MHZ   = 525000000,\r
 146     CLK_537MHZ   = 537000000,\r
 147     CLK_540MHZ   = 540000000,\r
 148     CLK_550MHZ   = 550000000,\r
 149     CLK_800MHZ   = 800000000,\r
 150     CLK_1000MHZ  = 1000000000,\r
 151     EMC_CLK_400MHZ = 400000000,\r
 152     EMC_CLK_450MHZ = 450000000,\r
 153     EMC_CLK_500MHZ = 500000000\r
 154 }CLK_TYPE_E;\r
 155 \r
 156 \r
 157 typedef enum EMC_CS_NUM_TAG\r
 158 {\r
 159     EMC_CS0 = 0,\r
 160     EMC_CS1\r
 161 }\r
 162 EMC_CS_NUM_E;\r
 163 \r
 164 typedef enum EMC_PORT_NUM_TAG\r
 165 {\r
 166     EMC_PORT_MIN    = 0,\r
 167     EMC_PORT0_AP    = 0,\r
 168     EMC_PORT1_GPU   = 1,\r
 169     EMC_PORT2_MST   = 2,\r
 170     EMC_PORT3_DSPP  = 3,\r
 171     EMC_PORT4_DSPD  = 4,\r
 172     EMC_PORT5_DISP  = 5,\r
 173     EMC_PORT6_MM    = 6,\r
 174     EMC_PORT7_CP    = 7,\r
 175         EMC_PORT_MAX    = 8\r
 176 }\r
 177 EMC_PORT_NUM_E;\r
 178 \r
 179 typedef enum\r
 180 {\r
 181         RANK_BANK_ROW_COL = 0x000,\r
 182         RANK_ROW_BANK_COL = 0x100,\r
 183         BANK_ROW_RANK_COL = 0x200\r
 184 }EMC_ADDR_MAP_TYPE_E;\r
 185 \r
 186 typedef enum\r
 187 {\r
 188         EMC_PORT_BE = 0, //Best effot, low priority\r
 189         EMC_PORT_LL = 1, //Low latnecy,high priority\r
 190         EMC_PORT_DD = 2  //dynamic determind,normal priority\r
 191 }EMC_PORT_PRIORITY_E;\r
 192 \r
 193 typedef enum\r
 194 {\r
 195         PHY_ACT_INIT    = BIT_0,        //trigger DDR system initialization,include PHY initialization,DRAM initialization,and PHY training\r
 196         PHY_ACT_DLLSRST = BIT_1,        //dll soft reset\r
 197         PHY_ACT_DLLOCK  = BIT_2,        //waite dll lock done\r
 198         PHY_ACT_ZCAL    = BIT_3,        //impedance calibrate,perform PHY impedance calibration\r
 199         PHY_ACT_ITMSRST = BIT_4,        //interface timing module soft reset\r
 200         PHY_ACT_DDR3RST = BIT_5,        //ddr3 reset\r
 201         PHY_ACT_DRAMINIT= BIT_6,        //excute DRAM initialization\r
 202         PHY_ACT_DQSTRN  = BIT_7,        //excute dqs training routine\r
 203         PHY_ACT_EYETRN  = BIT_8,        //read data eye training,not support in this phy version\r
 204         PHY_ACT_ICPC    = BIT_16,       //initialization complete pin configuration\r
 205         PHY_ACT_DLLBYP  = BIT_17,       //DLL bypass\r
 206         PHY_ACT_CTLDINIT= BIT_18,       //Control DRAM initialization,if set DRAM initialization will be excute by controller,\r
 207         PHY_ACT_CLRSR   = BIT_28,       //Clear all status register,include PGSR and DXnGSR\r
 208         PHY_ACT_LOCKBYP = BIT_29,       //DLL lock bypass,if set,DLL lock wait will auto tigger after reset\r
 209         PHY_ACT_ZCALBYP = BIT_30,       //impedance calibration bypass, if set, impedance calibration will auto tigger after reset\r
 210         PHY_ACT_INITBYP = BIT_31        //Initialization bypass\r
 211 }EMC_PHY_ACT_E;\r
 212 \r
 213 typedef enum\r
 214 {\r
 215         PHY_STATE_INIT_DONE     = 0x1,\r
 216         PHY_STATE_DLL_LOCK_DONE = 0x2,\r
 217         PHY_STATE_ZQCL_DONE     = 0x4,\r
 218         PHY_STATE_DRAM_INIT_DONE= 0x8,\r
 219         PHY_STATE_DTDONE                = 0x10,\r
 220         PHY_STATE_DTERR                 = 0x20,\r
 221         PHY_STATE_DTIERR                = 0x40,\r
 222         PHY_STATE_DRIFT_ERR             = 0x80,\r
 223         PHY_STATE_TQ                    = 0x80000000,\r
 224 }EMC_PHY_STATE_E;\r
 225 \r
 226 \r
 227 typedef enum\r
 228 {\r
 229         MEM_ACCESS_BYTE  = 1,\r
 230         MEM_ACCESS_HWORD = 2,\r
 231         MEM_ACCESS_WORD =  4\r
 232 }MEM_ACCESS_TYPE_E;\r
 233 \r
 234 typedef enum\r
 235 {\r
 236         TWO_BANK   = 2,\r
 237         FOUR_BANK  = 4,\r
 238         EIGHT_BANK = 8\r
 239 }MEM_BANK_NUM_E;\r
 240 \r
 241 typedef enum\r
 242 {\r
 243         DQS_STEP_DLY_MIN  = 0,\r
 244         DQS_STEP_DLY_SUB3 = 0,\r
 245         DQS_STEP_DLY_SUB2 = 1,\r
 246         DQS_STEP_DLY_SUB1 = 2,\r
 247         DQS_STEP_DLY_NOM  = 3,\r
 248         DQS_STEP_DLY_DEF  = 3,\r
 249         DQS_STEP_DLY_ADD1 = 4,\r
 250         DQS_STEP_DLY_ADD2 = 5,\r
 251         DQS_STEP_DLY_ADD3 = 6,\r
 252         DQS_STEP_DLY_ADD4 = 7,\r
 253         DQS_STEP_DLY_MAX  = 7\r
 254 }DQS_STEP_DLY_E;\r
 255 \r
 256 //DQS gating phase select\r
 257 typedef enum\r
 258 {\r
 259         DQS_PHS_DLY_MIN = 0,\r
 260         DQS_PHS_DLY_90  = 0,\r
 261         DQS_PHS_DLY_180 = 1,\r
 262         DQS_PHS_DLY_DEF = 1,\r
 263         DQS_PHS_DLY_270 = 2,\r
 264         DQS_PHS_DLY_360 = 3,\r
 265         DQS_PHS_DLY_MAX = 3\r
 266 }DQS_PHS_DLY_E;\r
 267 \r
 268 //DQS gating system latency\r
 269 typedef enum\r
 270 {\r
 271         DQS_CLK_DLY_MIN  = 0,\r
 272         DQS_CLK_DLY_DEF  = 0,\r
 273         DQS_CLK_DLY_1CLK = 1,\r
 274         DQS_CLK_DLY_2CLK = 2,\r
 275         DQS_CLK_DLY_3CLK = 3,\r
 276         DQS_CLK_DLY_4CLK = 4,\r
 277         DQS_CLK_DLY_5CLK = 5,\r
 278         DQS_CLK_DLY_MAX  = 5    \r
 279 }DQS_CLK_DLY_E;\r
 280 \r
 281 //slave dll phase trim\r
 282 typedef enum\r
 283 {\r
 284         SDLL_PHS_DLY_DEF  = 0x0,\r
 285         SDLL_PHS_DLY_36   = 0x3,\r
 286         SDLL_PHS_DLY_54   = 0x2,\r
 287         SDLL_PHS_DLY_72   = 0x1,\r
 288         SDLL_PHS_DLY_90   = 0x0,\r
 289         SDLL_PHS_DLY_108  = 0x4,\r
 290         SDLL_PHS_DLY_126  = 0x8,\r
 291         SDLL_PHS_DLY_144  = 0x12\r
 292 }SDLL_PHS_DLY_E;\r
 293 \r
 294 typedef enum\r
 295 {\r
 296         LPDDR2_DS_34_OHM = 0xd,\r
 297         LPDDR2_DS_40_OHM = 0xb,\r
 298         LPDDR2_DS_48_OHM = 0x9,\r
 299         LPDDR2_DS_60_OHM = 0x7,\r
 300         LPDDR2_DS_80_OHM = 0x5\r
 301 }LPDDR2_MEM_DS_T_E;\r
 302 \r
 303 typedef enum\r
 304 {\r
 305         PUBL_DS_34OHM = 0xd,\r
 306         PUBL_DS_40OHM = 0xb,\r
 307         PUBL_DS_48OHM = 0x9,\r
 308         PUBL_DS_60OHM = 0x7,\r
 309         PUBL_DS_80OHM = 0x5\r
 310 }PUBL_DS_E;\r
 311 \r
 312 typedef enum\r
 313 {\r
 314         LPDDR1_DS_33_OHM = 0xa,\r
 315         LPDDR1_DS_31_OHM = 0xb,\r
 316         LPDDR1_DS_48_OHM = 0xc,\r
 317         LPDDR1_DS_43_OHM = 0xd,\r
 318         LPDDR1_DS_39_OHM = 0xe,\r
 319         LPDDR1_DS_55_OHM = 0x5,\r
 320         LPDDR1_DS_64_OHM = 0x4\r
 321 }LPDDR1_MEM_DS_T_E;\r
 322 \r
 323 typedef enum\r
 324 {\r
 325         DQS_PDU_MIN    = 1,\r
 326         DQS_PDU_688ohm = 1,\r
 327         DQS_PDU_611ohm = 2,\r
 328         DQS_PDU_550ohm = 3,\r
 329         DQS_PDU_500ohm = 4,\r
 330         DQS_PDU_DEF    = 4,\r
 331         DQS_PDU_458ohm = 5,\r
 332         DQS_PDU_393ohm = 6,\r
 333         DQS_PDU_344ohm = 7,     \r
 334         DQS_PDU_MAX    = 7\r
 335 }DQS_PDU_E;\r
 336 \r
 337 typedef enum\r
 338 {\r
 339         CMD_NOP         = 0,\r
 340         CMD_PREA        = 1,\r
 341         CMD_REF         = 2,\r
 342         CMD_MRS         = 3,\r
 343         CMD_ZQCS        = 4,\r
 344         CMD_ZQCL        = 5,\r
 345         CMD_RSTL        = 6,\r
 346         CMD_MRR         = 8,\r
 347         CMD_DPDE        = 9,\r
 348         CMD_ERR         = 0XA\r
 349 }MEM_CMD_TYPE_E;\r
 350 \r
 351 typedef enum\r
 352 {\r
 353         CMD_MDR_NOT_EXIT = 0,\r
 354         CMD_MDR_RD_ONLY = 1,\r
 355         CMD_MDR_WR_ONLY = 2,\r
 356         CMD_MDR_NOP             = 3,\r
 357         CMD_MDR_SUCCESS = 4\r
 358 }MEM_CMD_RESULT_E;\r
 359 \r
 360 \r
 361 /******************************************************************************\r
 362                             Structure define\r
 363 ******************************************************************************/\r
 364 typedef struct\r
 365 {\r
 366         // timing for lpddr1 and lpddr2\r
 367         uint32 tREFI;   // average Refresh interval time between each row,normall = 7800 ns     \r
 368         uint32 tRAS;    // ACTIVE to PERCHARGE command period   \r
 369         uint32 tRC;     // ACTIVE to ACTIVE command period      \r
 370         uint32 tRFC;    // AUTO REFRESH to ACTIVE/AUTO REFRESH command period   \r
 371         uint32 tRCD;    // ACTIVE to READ/WRITE delay   \r
 372         uint32 tRP;             // PRECHARGE command period     \r
 373         uint32 tRRD;    // ACTIVE to ACTIVE delay       \r
 374         uint32 tWR;     // WRITE recovery time\r
 375         uint32 tWTR;    // internal write to read command delay \r
 376         uint32 tXSR;    // Self Refresh Exit to next valid command delay        \r
 377         uint32 tXP;     // Exit Power Down to next valid command delay  \r
 378         // timing for lpddr2 and ddr3\r
 379         uint32 tMRR;    // MODE REGISTR READ command period\r
 380         uint32 tCKESR;  // CKE signal min pulse width during self-refresh\r
 381         uint32 tZQCS;   // ZQ Calibration short time\r
 382         uint32 tZQCL;   // ZQ Calibration long time\r
 383 }DRAM_TIMING_INFO_T, *DRAM_TIMING_INFO_T_PTR;\r
 384 \r
 385 typedef struct \r
 386 {\r
 387     DRAM_TYPE_E         mem_type;       //dram type: lpddr1,lpddr2-s2,lpddr2-s4\r
 388         uint32                  cs_num;         //cs number summary,should be 1 or 2\r
 389     MEM_BANK_NUM_E      bank_num;       //bank number,lpddr1 and lpddr2 usually 4,ddr3 usually 8        \r
 390     DRAM_DENSITY_E      cs0_cap;        //cs0 density\r
 391     DRAM_DENSITY_E      cs1_cap;        //cs1 density\r
 392 \r
 393         IO_WIDTH_E              io_width;   //data io width, usually=16 or 32\r
 394         DRAM_BL_E               bl;                     //burst lenght,usually=2,4,8,16\r
 395         DRAM_CL_E               rl;             //read cas latency, usually=1,2,3,4,5,6,7,8\r
 396         DRAM_CL_E               wl;             //write cas latency, usually=1,2,3,4,5,6,7,8    \r
 397 } DRAM_MODE_INFO_T, *DRAM_MODE_INFO_T_PTR;\r
 398 \r
 399 \r
 400 typedef struct\r
 401 {\r
 402         char* chip_name;\r
 403         DRAM_TIMING_INFO_T_PTR time_info;\r
 404         DRAM_MODE_INFO_T_PTR mode_info;\r
 405 }\r
 406 DRAM_INFO_T, *DRAM_INFO_T_PTR;\r
 407 \r
 408 #define RDWR_ORDER_OFF FALSE\r
 409 #define RDWR_ORDER_ON  TRUE\r
 410 typedef struct\r
 411 {\r
 412         uint32 port_data_quantum;\r
 413         uint32 rdwr_order;\r
 414         EMC_PORT_PRIORITY_E port_priority;\r
 415 }EMC_CHN_INFO_T, *EMC_CHN_INFO_T_PTR;\r
 416 \r
 417 \r
 418 typedef struct\r
 419 {\r
 420         BOOLEAN INIT_DONE;\r
 421         BOOLEAN DLL_LOCK_DONE;\r
 422         BOOLEAN ZC_DONE;\r
 423         BOOLEAN DRAM_INIT_DONE;\r
 424         BOOLEAN DATA_TR_DONE;\r
 425         BOOLEAN DATA_TR_ERR;\r
 426         BOOLEAN DATA_TR_INTER_ERR;\r
 427         BOOLEAN DQS_DRIFT_ERROR;\r
 428 }EMC_PHY_STATUS_T,*EMC_PHY_STATUS_T_PTR;\r
 429 \r
 430 typedef struct\r
 431 {\r
 432 //      MEM_DS_T_E              mem_ds;\r
 433         SDLL_PHS_DLY_E  sdll_phase_b0;\r
 434         SDLL_PHS_DLY_E  sdll_phase_b1;\r
 435         SDLL_PHS_DLY_E  sdll_phase_b2;\r
 436         SDLL_PHS_DLY_E  sdll_phase_b3;  \r
 437         DQS_STEP_DLY_E  dqs_step_b0;\r
 438         DQS_STEP_DLY_E  dqs_step_b1;\r
 439         DQS_STEP_DLY_E  dqs_step_b2;\r
 440         DQS_STEP_DLY_E  dqs_step_b3;            \r
 441 }ADJ_PAR_T,*ADJ_PAR_T_PTR;\r
 442 \r
 443 \r
 444 \r
 445 typedef enum \r
 446 {\r
 447         LPDDR2_DEFAULT = 0x00,\r
 448         LPDDR2_SAMSUNG = 0x01,\r
 449         LPDDR2_QIMONDA = 0x02,\r
 450         LPDDR2_ELPIDA  = 0x03,\r
 451         LPDDR2_ETRON   = 0x04,\r
 452         LPDDR2_NANYA   = 0X05,\r
 453         LPDDR2_HYNIX   = 0x06,  \r
 454         LPDDR2_MOSEL   = 0X07,\r
 455         LPDDR2_WINBOND = 0X08,\r
 456         LPDDR2_ESMT    = 0X09,\r
 457         LPDDR2_SPANSION= 0X0B,\r
 458         LPDDR2_SST     = 0X0C,\r
 459         LPDDR2_ZMOS    = 0X0D,\r
 460         LPDDR2_INTLE   = 0X0E,\r
 461         LPDDR2_NUMONYX = 0XFE,\r
 462         LPDDR2_MiCRON  = 0XFF\r
 463         \r
 464 }LPDDR2_MANUFACTURE_ID_E;\r
 465 typedef struct\r
 466 {\r
 467         LPDDR2_MANUFACTURE_ID_E cust_lpddr2_id;\r
 468         PUBL_DS_E               cust_publ_ds;\r
 469         LPDDR2_MEM_DS_T_E       cust_lpddr2_mem_ds;\r
 470         SDLL_PHS_DLY_E          cust_b0_sdll_phs;\r
 471         SDLL_PHS_DLY_E          cust_b1_sdll_phs;\r
 472         SDLL_PHS_DLY_E          cust_b2_sdll_phs;\r
 473         SDLL_PHS_DLY_E          cust_b3_sdll_phs;       \r
 474         DQS_STEP_DLY_E          cust_b0_dqs_step;\r
 475         DQS_STEP_DLY_E          cust_b1_dqs_step;\r
 476         DQS_STEP_DLY_E          cust_b2_dqs_step;\r
 477         DQS_STEP_DLY_E          cust_b3_dqs_step;       \r
 478 }customer_timing_t;\r
 479 \r
 480 /*******************************************************************************\r
 481                            Variable and Array definiation\r
 482 *******************************************************************************/                     \r
 483 #define DRAM_BURST_TYPE DRAM_BT_SEQ\r
 484 #define DRAM_BURST_WRAP DRAM_NO_WRAP\r
 485 #define NONE_MDR 0XFF\r
 486 #define DQS_PDU_RES DQS_PDU_500ohm      //dqs pull up and pull down resist\r
 487 \r
 488 #define EMC_SMALL_CODE_SIZE \r
 489 const EMC_CHN_INFO_T   EMC_CHN_INFO_ARRAY[EMC_PORT_MAX] = {{0x10,RDWR_ORDER_OFF,EMC_PORT_BE},//AP port set\r
 490                                                                                             {0x10,RDWR_ORDER_OFF,EMC_PORT_BE},//GPU port set\r
 491                                                                                             {0x10,RDWR_ORDER_ON, EMC_PORT_BE},//MST port set\r
 492                                                                                             {0x10,RDWR_ORDER_ON, EMC_PORT_LL},//DSPP port set\r
 493                                                                                             {0x10,RDWR_ORDER_ON, EMC_PORT_LL},//DSPD port set\r
 494                                                                                             {0x10,RDWR_ORDER_OFF,EMC_PORT_LL},//DISP port set\r
 495                                                                                             {0x10,RDWR_ORDER_OFF,EMC_PORT_LL},//MM port set\r
 496                                                                                             {0x10,RDWR_ORDER_ON, EMC_PORT_BE}};//CP port set\r
 497 const char* DRAM_CHIP_NAME_INFO_ARRAY[] =\r
 498 {\r
 499 //      "NORMAL_LPDDR1_1CS_1G_32BIT",\r
 500         "NORMAL_LPDDR1_1CS_2G_32BIT",\r
 501         "NORMAL_LPDDR1_2CS_4G_32BIT",\r
 502         "NORMAL_LPDDR2_1CS_4G_32BIT",\r
 503         "NORMAL_LPDDR2_2CS_8G_32BIT"\r
 504 //      "HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM",\r
 505 //      "SAMSUNG_LPDDR2_KMKJS000VM"\r
 506 };\r
 507 \r
 508 const DRAM_MODE_INFO_T DRAM_MODE_INFO_ARRAY[] =\r
 509 {\r
 510 //{DRAM_LPDDR1,   ONE_CS,FOUR_BANK,DRAM_1GBIT,DRAM_0BIT,  IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_1CS_1G_32BIT\r
 511 {DRAM_LPDDR1,   ONE_CS,FOUR_BANK,DRAM_2GBIT,DRAM_0BIT,  IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_1CS_2G_32BIT    \r
 512 {DRAM_LPDDR1,   TWO_CS,FOUR_BANK,DRAM_2GBIT,DRAM_2GBIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_2CS_4G_32BIT\r
 513 {DRAM_LPDDR2_S4,ONE_CS,FOUR_BANK,DRAM_4GBIT,DRAM_0BIT,  IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3},//NORMAL_LPDDR2_1CS_4G_32BIT\r
 514 {DRAM_LPDDR2_S4,TWO_CS,FOUR_BANK,DRAM_4GBIT,DRAM_4GBIT, IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3} //NORMAL_LPDDR2_2CS_8G_32BIT\r
 515 //{DRAM_LPDDR1,   TWO_CS,FOUR_BANK,DRAM_2GBIT,DRAM_2GBIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM\r
 516 //{DRAM_LPDDR2_S4,TWO_CS,FOUR_BANK,DRAM_4GBIT,DRAM_4GBIT, IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3} //SAMSUNG_LPDDR2_KMKJS000VM\r
 517 };\r
 518 \r
 519 \r
 520 const DRAM_TIMING_INFO_T DRAM_TIMING_INFO_ARRAY[] =\r
 521 {\r
 522 //  ns   ns          ns  tRFC(ns) ns  tRP(ns) ns   ns  clk  ns   ns  clk  ns     ns    ns\r
 523 //  tREFI tRAS    tRC  /tRFCab tRCD /tRPpb tRRD tWR tWTR tXSR tXP tMRR tCKESR tZQCS tZQCL\r
 524 //      {7800, 50,      80, 110,        30,  30,    15,  15, 3,   140, 20, 0,  0,               0,        0},//NORMAL_LPDDR1_1CS_1G_32BIT\r
 525         {7800, 40,      80, 90,         20,  15,    15,  15, 2,   140, 20, 0,  0,               0,        0},//NORMAL_LPDDR1_1CS_2G_32BIT\r
 526         {7800, 40,      80, 90,         20,  15,    15,  15, 2,   140, 20, 0,  0,               0,    0},//NORMAL_LPDDR1_2CS_4G_32BIT\r
 527         {3900, 43,      65, 130,        20,  20,    10,  15, 3,   140, 20, 2,  15,         90,  360},//NORMAL_LPDDR2_1CS_4G_32BIT                       \r
 528         {3900, 43,      65, 130,        20,  20,    10,  15, 3,   140, 20, 2,  15,         90,  360} //NORMAL_LPDDR2_2CS_8G_32BIT                               \r
 529 //      {7800, 50,      80, 90,         30,  30,    15,  15, 3,   140, 20, 0,  0,               0,    0},//HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM\r
 530 //      {3900, 50,      80, 130,        20,  30,    15,  15, 3,   140, 20, 2,  15,         90,  360} //SAMSUNG_LPDDR2_KMKJS000VM        \r
 531 };\r
 532 \r
 533 const customer_timing_t CUSTOMER_TIMING_INFO[] = \r
 534 {\r
 535                 {LPDDR2_DEFAULT,\r
 536                 PUBL_DS_40OHM,\r
 537                 LPDDR2_DS_40_OHM,\r
 538                 SDLL_PHS_DLY_72,\r
 539                 SDLL_PHS_DLY_72,\r
 540                 SDLL_PHS_DLY_72,\r
 541                 SDLL_PHS_DLY_72,\r
 542                 DQS_STEP_DLY_ADD3,\r
 543                 DQS_STEP_DLY_ADD1,\r
 544                 DQS_STEP_DLY_ADD1,\r
 545                 DQS_STEP_DLY_ADD2},\r
 546                 \r
 547                 {LPDDR2_SAMSUNG, //manufacturer \r
 548                 PUBL_DS_40OHM,\r
 549                 LPDDR2_DS_40_OHM,\r
 550                 SDLL_PHS_DLY_72,\r
 551                 SDLL_PHS_DLY_72,\r
 552                 SDLL_PHS_DLY_72,\r
 553                 SDLL_PHS_DLY_72,\r
 554                 DQS_STEP_DLY_ADD3,\r
 555                 DQS_STEP_DLY_ADD1,\r
 556                 DQS_STEP_DLY_ADD1,\r
 557                 DQS_STEP_DLY_ADD2},\r
 558                 \r
 559                 {LPDDR2_MiCRON, //manufacturer\r
 560                 PUBL_DS_40OHM,\r
 561                 LPDDR2_DS_40_OHM,\r
 562                 SDLL_PHS_DLY_72,\r
 563                 SDLL_PHS_DLY_72,\r
 564                 SDLL_PHS_DLY_72,\r
 565                 SDLL_PHS_DLY_72,\r
 566                 DQS_STEP_DLY_ADD3,\r
 567                 DQS_STEP_DLY_ADD1,\r
 568                 DQS_STEP_DLY_ADD1,\r
 569                 DQS_STEP_DLY_ADD2},\r
 570                 \r
 571                 {LPDDR2_HYNIX,  //manufacturer\r
 572                 PUBL_DS_48OHM,\r
 573                 LPDDR2_DS_34_OHM,\r
 574                 SDLL_PHS_DLY_72,\r
 575                 SDLL_PHS_DLY_72,\r
 576                 SDLL_PHS_DLY_72,\r
 577                 SDLL_PHS_DLY_72,\r
 578                 DQS_STEP_DLY_ADD3,\r
 579                 DQS_STEP_DLY_ADD1,\r
 580                 DQS_STEP_DLY_ADD1,\r
 581                 DQS_STEP_DLY_ADD2},\r
 582 \r
 583 };\r
 584 \r
 585 /*******************************************************************************\r
 586                           Function declare\r
 587 *******************************************************************************/\r
 588 \r