1 /******************************************************************************
2 ** File Name: pinmap.h *
3 ** Author: Richard.Yang *
5 ** Copyright: 2004 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: This file defines the structure of pin map. *
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION *
13 ** 03/08/2004 Richard.Yang Create. *
14 ******************************************************************************/
19 #include "sci_types.h"
20 #include "sc8810_reg_base.h"
27 //int pin_init(pinmap_t * pinmap);
29 #define CTL_PIN_BASE (PIN_CTL_BASE)
31 /* registers definitions for controller CTL_PIN */
32 #define REG_PIN_CTRL0 ( 0x0000 )
33 #define REG_PIN_CTRL1 ( 0x0004 )
34 #define REG_PIN_CTRL2 ( 0x0008 )
35 #define REG_PIN_CTRL3 ( 0x000c )
36 #define REG_PIN_CTRL4 ( 0x0010 )
37 #define REG_PIN_CTRL5 ( 0x0014 )
38 #define REG_PIN_SIMCLK0 ( 0x0018 )
39 #define REG_PIN_U0RTS ( 0x0134 )
40 #define REG_PIN_SIMDA0 ( 0x001c )
41 #define REG_PIN_SIMRST0 ( 0x0020 )
42 #define REG_PIN_SIMCLK1 ( 0x0024 )
43 #define REG_PIN_SIMDA1 ( 0x0028 )
44 #define REG_PIN_SIMRST1 ( 0x002c )
45 #define REG_PIN_SD0_CLK ( 0x0030 )
46 #define REG_PIN_SD0_CMD ( 0x0034 )
47 #define REG_PIN_SD0_D0 ( 0x0038 )
48 #define REG_PIN_SD0_D1 ( 0x003c )
49 #define REG_PIN_SD0_D2 ( 0x0040 )
50 #define REG_PIN_SD0_D3 ( 0x0044 )
51 #define REG_PIN_ANA_INT ( 0x0048 )
52 #define REG_PIN_EXT_RST_B ( 0x004c )
53 #define REG_PIN_CLK_26M ( 0x0050 )
54 #define REG_PIN_CHIP_SLEEP ( 0x0054 )
55 #define REG_PIN_XTL_BUF_EN ( 0x0058 )
56 #define REG_PIN_CLK_32K ( 0x005c )
57 #define REG_PIN_AUD_SCLK ( 0x0060 )
58 #define REG_PIN_AUD_ADD0 ( 0x0064 )
59 #define REG_PIN_AUD_ADSYNC ( 0x0068 )
60 #define REG_PIN_AUD_DAD1 ( 0x006c )
61 #define REG_PIN_AUD_DAD0 ( 0x0070 )
62 #define REG_PIN_AUD_DASYNC ( 0x0074 )
63 #define REG_PIN_TD_TXPD ( 0x0078 )
64 #define REG_PIN_TD_RXPD ( 0x007c )
65 #define REG_PIN_GSM_TXPD ( 0x0080 )
66 #define REG_PIN_GSM_RXPD ( 0x0084 )
67 #define REG_PIN_TD_RX_CLK ( 0x0088 )
68 #define REG_PIN_ADI_D ( 0x008c )
69 #define REG_PIN_ADI_SYNC ( 0x0090 )
70 #define REG_PIN_ADI_SCLK ( 0x0094 )
71 #define REG_PIN_ANA_INT2 ( 0x0098 )
72 #define REG_PIN_COM_TX_APCD ( 0x009c )
73 #define REG_PIN_COM_TX_DQ1 ( 0x00a0 )
74 #define REG_PIN_COM_TX_DQ0 ( 0x00a4 )
75 #define REG_PIN_COM_TX_DI1 ( 0x00a8 )
76 #define REG_PIN_COM_TX_DI0 ( 0x00ac )
77 #define REG_PIN_COM_TX_SYNC ( 0x00b0 )
78 #define REG_PIN_COM_TX_SCLK ( 0x00b4 )
79 #define REG_PIN_COM_RX_DQ1 ( 0x00b8 )
80 #define REG_PIN_COM_RX_DQ0 ( 0x00bc )
81 #define REG_PIN_COM_RX_DI1 ( 0x00c0 )
82 #define REG_PIN_COM_RX_DI0 ( 0x00c4 )
83 #define REG_PIN_COM_RX_SYNC ( 0x00c8 )
84 #define REG_PIN_COM_RX_SCLK ( 0x00cc )
85 #define REG_PIN_CCIRCK ( 0x00d0 )
86 #define REG_PIN_CCIRMCLK ( 0x00d4 )
87 #define REG_PIN_CCIRHS ( 0x00d8 )
88 #define REG_PIN_CCIRVS ( 0x00dc )
89 #define REG_PIN_CCIRD0 ( 0x00e0 )
90 #define REG_PIN_CCIRD1 ( 0x00e4 )
91 #define REG_PIN_CCIRD2 ( 0x00e8 )
92 #define REG_PIN_CCIRD3 ( 0x00ec )
93 #define REG_PIN_CCIRD4 ( 0x00f0 )
94 #define REG_PIN_CCIRD5 ( 0x00f4 )
95 #define REG_PIN_CCIRD6 ( 0x00f8 )
96 #define REG_PIN_CCIRD7 ( 0x00fc )
97 #define REG_PIN_CCIRD8 ( 0x0100 )
98 #define REG_PIN_CCIRD9 ( 0x0104 )
99 #define REG_PIN_CCIRRST ( 0x0108 )
100 #define REG_PIN_CCIRPD1 ( 0x010c )
101 #define REG_PIN_CCIRPD0 ( 0x0110 )
102 #define REG_PIN_SCL1 ( 0x0114 )
103 #define REG_PIN_SDA1 ( 0x0118 )
104 #define REG_PIN_KEYOUT0 ( 0x011c )
105 #define REG_PIN_KEYOUT1 ( 0x0120 )
106 #define REG_PIN_KEYOUT2 ( 0x0124 )
107 #define REG_PIN_KEYOUT3 ( 0x0128 )
108 #define REG_PIN_KEYOUT4 ( 0x012c )
109 #define REG_PIN_KEYOUT5 ( 0x0130 )
110 #define REG_PIN_GPIO135 ( 0x0134 )
111 #define REG_PIN_GPIO136 ( 0x0138 )
112 #define REG_PIN_GPIO137 ( 0x013c )
113 #define REG_PIN_GPIO138 ( 0x0140 )
114 #define REG_PIN_GPIO139 ( 0x0144 )
115 #define REG_PIN_GPIO140 ( 0x0148 )
116 #define REG_PIN_KEYOUT6 ( 0x014c )
117 #define REG_PIN_KEYOUT7 ( 0x0150 )
118 #define REG_PIN_KEYIN0 ( 0x0154 )
119 #define REG_PIN_KEYIN1 ( 0x0158 )
120 #define REG_PIN_KEYIN2 ( 0x015c )
121 #define REG_PIN_KEYIN3 ( 0x0160 )
122 #define REG_PIN_KEYIN4 ( 0x0164 )
123 #define REG_PIN_KEYIN5 ( 0x0168 )
124 #define REG_PIN_KEYIN6 ( 0x016c )
125 #define REG_PIN_KEYIN7 ( 0x0170 )
126 #define REG_PIN_NFWPN ( 0x0174 )
127 #define REG_PIN_NFRB ( 0x0178 )
128 #define REG_PIN_NFCLE ( 0x017c )
129 #define REG_PIN_NFALE ( 0x0180 )
130 #define REG_PIN_NFCEN ( 0x0184 )
131 #define REG_PIN_NFREN ( 0x0188 )
132 #define REG_PIN_NFWEN ( 0x018c )
133 #define REG_PIN_NFD0 ( 0x0190 )
134 #define REG_PIN_NFD1 ( 0x0194 )
135 #define REG_PIN_NFD2 ( 0x0198 )
136 #define REG_PIN_NFD3 ( 0x019c )
137 #define REG_PIN_NFD4 ( 0x01a0 )
138 #define REG_PIN_NFD5 ( 0x01a4 )
139 #define REG_PIN_NFD6 ( 0x01a8 )
140 #define REG_PIN_NFD7 ( 0x01ac )
141 #define REG_PIN_NFD8 ( 0x01b0 )
142 #define REG_PIN_NFD9 ( 0x01b4 )
143 #define REG_PIN_NFD10 ( 0x01b8 )
144 #define REG_PIN_NFD11 ( 0x01bc )
145 #define REG_PIN_NFD12 ( 0x01c0 )
146 #define REG_PIN_NFD13 ( 0x01c4 )
147 #define REG_PIN_NFD14 ( 0x01c8 )
148 #define REG_PIN_NFD15 ( 0x01cc )
149 #define REG_PIN_SD3_CLK ( 0x01d0 )
150 #define REG_PIN_SD3_CMD ( 0x01d4 )
151 #define REG_PIN_SD3_D0 ( 0x01d8 )
152 #define REG_PIN_SD3_D1 ( 0x01dc )
153 #define REG_PIN_SD3_D2 ( 0x01e0 )
154 #define REG_PIN_SD3_D3 ( 0x01e4 )
155 #define REG_PIN_SD3_D4 ( 0x01e8 )
156 #define REG_PIN_SD3_D5 ( 0x01ec )
157 #define REG_PIN_SD3_D6 ( 0x01f0 )
158 #define REG_PIN_SD3_D7 ( 0x01f4 )
159 #define REG_PIN_EMMC_RST ( 0x01f8 )
160 #define REG_PIN_SD1_CLK ( 0x01fc )
161 #define REG_PIN_SD1_CMD ( 0x0200 )
162 #define REG_PIN_SD1_D0 ( 0x0204 )
163 #define REG_PIN_SD1_D1 ( 0x0208 )
164 #define REG_PIN_SD1_D2 ( 0x020c )
165 #define REG_PIN_SD1_D3 ( 0x0210 )
166 #define REG_PIN_LCD_CSN1 ( 0x0214 )
167 #define REG_PIN_LCD_RSTN ( 0x0218 )
168 #define REG_PIN_LCD_CD ( 0x021c )
169 #define REG_PIN_LCD_D0 ( 0x0220 )
170 #define REG_PIN_LCD_D1 ( 0x0224 )
171 #define REG_PIN_LCD_D2 ( 0x0228 )
172 #define REG_PIN_LCD_D3 ( 0x022c )
173 #define REG_PIN_LCD_D4 ( 0x0230 )
174 #define REG_PIN_LCD_D5 ( 0x0234 )
175 #define REG_PIN_LCD_D6 ( 0x0238 )
176 #define REG_PIN_LCD_D7 ( 0x023c )
177 #define REG_PIN_LCD_D8 ( 0x0240 )
178 #define REG_PIN_LCD_WRN ( 0x0244 )
179 #define REG_PIN_LCD_RDN ( 0x0248 )
180 #define REG_PIN_LCD_CSN0 ( 0x024c )
181 #define REG_PIN_LCD_D9 ( 0x0250 )
182 #define REG_PIN_LCD_D10 ( 0x0254 )
183 #define REG_PIN_LCD_D11 ( 0x0258 )
184 #define REG_PIN_LCD_D12 ( 0x025c )
185 #define REG_PIN_LCD_D13 ( 0x0260 )
186 #define REG_PIN_LCD_D14 ( 0x0264 )
187 #define REG_PIN_LCD_D15 ( 0x0268 )
188 #define REG_PIN_LCD_D16 ( 0x026c )
189 #define REG_PIN_LCD_D17 ( 0x0270 )
190 #define REG_PIN_LCD_D18 ( 0x0274 )
191 #define REG_PIN_LCD_D19 ( 0x0278 )
192 #define REG_PIN_LCD_D20 ( 0x027c )
193 #define REG_PIN_LCD_D21 ( 0x0280 )
194 #define REG_PIN_LCD_D22 ( 0x0284 )
195 #define REG_PIN_LCD_D23 ( 0x0288 )
196 #define REG_PIN_LCD_FMARK ( 0x028c )
197 #define REG_PIN_SPI2_CSN ( 0x0290 )
198 #define REG_PIN_SPI2_DO ( 0x0294 )
199 #define REG_PIN_SPI2_DI ( 0x0298 )
200 #define REG_PIN_SPI2_CLK ( 0x029c )
201 #define REG_PIN_SCL0 ( 0x02a0 )
202 #define REG_PIN_SDA0 ( 0x02a4 )
203 #define REG_PIN_SCL2 ( 0x02a8 )
204 #define REG_PIN_SDA2 ( 0x02ac )
205 #define REG_PIN_SCL3 ( 0x02b0 )
206 #define REG_PIN_SDA3 ( 0x02b4 )
207 #define REG_PIN_CLK_AUX0 ( 0x02b8 )
208 #define REG_PIN_IIS0DI ( 0x02bc )
209 #define REG_PIN_IIS0DO ( 0x02c0 )
210 #define REG_PIN_IIS0CLK ( 0x02c4 )
211 #define REG_PIN_IIS0LRCK ( 0x02c8 )
212 #define REG_PIN_IIS0MCK ( 0x02cc )
213 #define REG_PIN_SPI0_CSN ( 0x02d0 )
214 #define REG_PIN_SPI0_DO ( 0x02d4 )
215 #define REG_PIN_SPI0_DI ( 0x02d8 )
216 #define REG_PIN_SPI0_CLK ( 0x02dc )
217 #define REG_PIN_GPIO141 ( 0x02e0 )
218 #define REG_PIN_GPIO142 ( 0x02e4 )
219 #define REG_PIN_MTDO ( 0x02e8 )
221 #define REG_PIN_MTDI ( 0x02ec )
222 #define REG_PIN_MTCK ( 0x02f0 )
223 #define REG_PIN_MTMS ( 0x02f4 )
224 #define REG_PIN_MTRST_N ( 0x02f8 )
225 #define REG_PIN_TRACECLK ( 0x02fc )
226 #define REG_PIN_TRACECTRL ( 0x0300 )
227 #define REG_PIN_TRACEDAT0 ( 0x0304 )
228 #define REG_PIN_TRACEDAT1 ( 0x0308 )
229 #define REG_PIN_TRACEDAT2 ( 0x030c )
230 #define REG_PIN_TRACEDAT3 ( 0x0310 )
231 #define REG_PIN_TRACEDAT4 ( 0x0314 )
232 #define REG_PIN_TRACEDAT5 ( 0x0318 )
233 #define REG_PIN_TRACEDAT6 ( 0x031c )
234 #define REG_PIN_TRACEDAT7 ( 0x0320 )
235 #define REG_PIN_U0TXD ( 0x0324 )
236 #define REG_PIN_U0RXD ( 0x0328 )
237 #define REG_PIN_U0CTS ( 0x032c )
239 #define REG_PIN_U1TXD ( 0x0334 )
240 #define REG_PIN_U1RXD ( 0x0338 )
241 #define REG_PIN_U2TXD ( 0x033c )
242 #define REG_PIN_U2RXD ( 0x0340 )
243 #define REG_PIN_U2CTS ( 0x0344 )
244 #define REG_PIN_U2RTS ( 0x0348 )
245 #define REG_PIN_U3TXD ( 0x034c )
246 #define REG_PIN_U3RXD ( 0x0350 )
247 #define REG_PIN_U3CTS ( 0x0354 )
248 #define REG_PIN_U3RTS ( 0x0358 )
249 #define REG_PIN_CLK_REQ1 ( 0x035c )
250 #define REG_PIN_CLK_REQ2 ( 0x0360 )
251 #define REG_PIN_RFSDA0 ( 0x0364 )
252 #define REG_PIN_RFSCK0 ( 0x0368 )
253 #define REG_PIN_RFSEN0 ( 0x036c )
254 #define REG_PIN_RFCTL0 ( 0x0370 )
255 #define REG_PIN_RFCTL1 ( 0x0374 )
256 #define REG_PIN_RFCTL2 ( 0x0378 )
257 #define REG_PIN_RFCTL3 ( 0x037c )
259 #define REG_PIN_RFCTL4 ( 0x0380 )
260 #define REG_PIN_RFCTL5 ( 0x0384 )
261 #define REG_PIN_RFCTL6 ( 0x0388 )
262 #define REG_PIN_RFCTL7 ( 0x038c )
263 #define REG_PIN_RFCTL8 ( 0x0390 )
264 #define REG_PIN_RFCTL9 ( 0x0394 )
265 #define REG_PIN_RFCTL10 ( 0x0398 )
266 #define REG_PIN_RFCTL11 ( 0x039c )
267 #define REG_PIN_RFCTL12 ( 0x03a0 )
268 #define REG_PIN_RFCTL13 ( 0x03a4 )
269 #define REG_PIN_RFCTL14 ( 0x03a8 )
270 #define REG_PIN_RFCTL15 ( 0x03ac )
271 #define REG_PIN_XTL_EN ( 0x03b0 )
272 #define REG_PIN_PTEST ( 0x03b4 )
273 #define REG_PIN_GPIO143 ( 0x03b8 )
274 #define REG_PIN_GPIO144 ( 0x03bc )
277 /* bits definitions for register REG_PIN_XXX */
278 #define BITS_PIN_DS(_x_) ( (_x_) << 8 & (BIT_8|BIT_9) )
279 #define BITS_PIN_DS_3(_x_) ( (_x_) << 8 & (BIT_8|BIT_9|BIT_10) )
280 #define BIT_PIN_WPU ( BIT_7 )
281 #define BIT_PIN_WPD ( BIT_6 )
282 #define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT_4|BIT_5) )
283 #define BIT_PIN_SLP_WPU ( BIT_3 )
284 #define BIT_PIN_SLP_WPD ( BIT_2 )
285 #define BIT_PIN_SLP_IE ( BIT_1 )
286 #define BIT_PIN_SLP_OE ( BIT_0 )
288 /* vars definitions for controller CTL_PIN */
289 #define BIT_PIN_NUL ( 0 )
290 #define BIT_PIN_SLP_NUL ( 0 )
291 #define BIT_PIN_SLP_Z ( 0 )