arch/arm/include/asm/arch-sc8810/emc_config.h

   1 #ifndef _EMC_CONFIG_H_\r
   2 #define _EMC_CONFIG_H_\r
   3 \r
   4 \r
   5 #include "sdram_sc7710g2.h"\r
   6 \r
   7 /******************************************************************************\r
   8                            Macro define\r
   9 ******************************************************************************/\r
  10     \r
  11 \r
  12 //only one chip maro definition can equal to 1, others should equal to 0\r
  13 //#define CHIP0_HYNIX_DDR_H8BCS0RJ0MCP          \r
  14 //#define CHIP1_TOSHIBA_SDR_TY9000A800JFGP40    \r
  15 //#define CHIP2_ST_SDR_M65K                     \r
  16 //#define CHIP3_SAMSUNG_SDR_K5D1G13DCA          \r
  17 //#define CHIP4_SAMSUNG_SDR_K5D5657DCBD090\r
  18 //#define CHIP5_HYNIX_SDR_HYC0SEH0AF3P\r
  19 //#define CHIP6_SAMSUNG_SDR_K5D1257ACFD090\r
  20 //#define CHIP7_HYNIX_SDR_H8ACUOCEOBBR\r
  21 //#define CHIP8_HYNIX_SDR_H8ACS0EJ0MCP\r
  22 //#define CHIP9_HYNIX_SDR_H8AES0SQ0MCP\r
  23 //#define CHIP10_HYNIX_SDR_HYC0SEH0AF3P\r
  24 //#define CHIP11_MICRON_SDR_MT48H\r
  25 //#define CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM\r
  26 //#define CHIP13_HYNIX_SDR_H8ACS0PH0MCP\r
  27 //#define CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR       \r
  28 //#define CHIP15_SAMSUNG_DDR_K522H1HACF         \r
  29 \r
  30 //#define SDR_SDRAM_SUPPORT\r
  31 \r
  32 #define SDRAM_AUTODETECT_SUPPORT\r
  33 \r
  34 /*******************************************************************************\r
  35                           Parameter declare\r
  36 *******************************************************************************/\r
  37    \r
  38 \r
  39 \r
  40 extern CONST EMC_PHY_L1_TIMING_T EMC_PHY_TIMING_L1_INFO[EMC_PHYL1_TIMING_MATRIX_MAX];\r
  41 extern CONST EMC_PHY_L2_TIMING_T EMC_PHY_TIMING_L2_INFO[EMC_PHYL2_TIMING_MATRIX_MAX];\r
  42 \r
  43 \r
  44 /*******************************************************************************\r
  45                           Function declare\r
  46 *******************************************************************************/\r
  47 \r
  48 extern SDRAM_CFG_INFO_T_PTR SDRAM_GetCfg(void);\r
  49 extern SDRAM_TIMING_PARA_T_PTR SDRAM_GetTimingPara(void);\r
  50 extern SDRAM_CHIP_FEATURE_T_PTR SDRAM_GetFeature(void);\r
  51 \r
  52 extern EMC_PHY_L1_TIMING_T_PTR EMC_GetPHYL1_Timing(DMEM_TYPE_E mem_type, uint32 cas_latency);\r
  53 extern void EMC_PHY_Latency_Set(SDRAM_CFG_INFO_T_PTR mem_info);\r
  54 extern void EMC_PHY_Timing_Set(SDRAM_CFG_INFO_T_PTR mem_info,\r
  55                         EMC_PHY_L1_TIMING_T_PTR emc_phy_l1_timing,\r
  56                         EMC_PHY_L2_TIMING_T_PTR emc_phy_l2_timing);\r
  57 extern EMC_PHY_L2_TIMING_T_PTR EMC_GetPHYL2_Timing(void);\r
  58 extern SDRAM_MODE_PTR SDRAM_GetModeTable(void);\r
  59 extern EMC_PARAM_PTR EMC_GetPara(void);\r
  60 extern EMC_CHL_INFO_PTR EMC_GetChlInfo(void);\r
  61 \r
  62 #endif\r
  63 \r